On 28.05.2024 9:43 PM, Barnabás Czémán wrote:
> From: Otto Pflüger
>
> Add support for Adreno 306A GPU what is found in MSM8917 SoC.
> This GPU marketing name is Adreno 308.
>
> Signed-off-by: Otto Pflüger
> [use internal name of the GPU, reword the commit message]
> Signed-off-by: Barnabás
formats, format)' failed.
>
> Signed-off-by: Junhao Xie
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 5/13/24 17:51, Rob Clark wrote:
From: Rob Clark
When debugging faults, it is useful to know how the BO is mapped (cached
vs WC, gpu readonly, etc).
Signed-off-by: Rob Clark
---
Acked-by: Konrad Dybcio
Konrad
the hack
introduced in commit b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt
status in hw_init").
Fixes: b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init")
Signed-off-by: Konrad Dybcio
---
Changes in v2:
* Introduce gpu_write_flush() and use it
* Don't acc
the hack
introduced in commit b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt
status in hw_init").
Fixes: b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 ++---
drivers/gpu/drm/msm/ad
On 30.04.2024 12:43 PM, Connor Abbott wrote:
> This isn't known to fix anything yet, but it's a good idea to add it.
>
> Signed-off-by: Connor Abbott
> ---
Reviewed-by: Konrad Dybcio
Konrad
ed by qcom_scm to fuse off certain features like
> raytracing in software. The fuse is default off, and is initialized by
> calling the method. Afterwards we have to read it to find out which
> features were enabled.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Connor A
On 30.04.2024 12:43 PM, Connor Abbott wrote:
> This will used by drm/msm to initialize GPU registers that Qualcomm's
> firmware doesn't make writeable to the kernel.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Connor Abbott
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 26.04.2024 8:34 PM, Connor Abbott wrote:
> This isn't known to fix anything yet, but it's a good idea to add it.
>
> Signed-off-by: Connor Abbott
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git
->has_ray_tracing;
> + return 0;
I'd personally go with MSM_PARAM_FEATURES as a u64 bitmap, but it's
not me that'll have to deal with this on the userland side, so:
Reviewed-by: Konrad Dybcio
Konrad
On 26.04.2024 8:34 PM, Connor Abbott wrote:
> On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> initialize cx_mem. Copy this from downstream (minus BCL which we
> currently don't support). On a750, this includes a new "fuse" register
> which can be used by qcom_scm to fuse
On 26.04.2024 8:34 PM, Connor Abbott wrote:
> This will used by drm/msm.
>
> Signed-off-by: Connor Abbott
> ---
[...]
> +/**
> + * Request TZ to program set of access controlled registers necessary
> + * irrespective of any features
> + */
kerneldoc abuse, please make it a regular comment
On 26.04.2024 8:33 PM, Connor Abbott wrote:
> This is doubled compared to previous GPUs. We can't access the new
> SW_FUSE_VALUE register without this.
>
> Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes")
> Signed-off-by: Connor Abbott
> ---
Reviewed-by: Konrad Dybcio
Konrad
Separate out Adreno from the rest of the drm/msm driver, add myself
as a reviewer for the former.
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (2):
MAINTAINERS: Add a separate entry for Qualcomm Adreno GPU drivers
MAINTAINERS: Add Konrad Dybcio as a reviewer for the Adreno driver
Add myself as a reviewer for Adreno driver changes.
Signed-off-by: Konrad Dybcio
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 179f989a1e4b..80aa006f10bb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6888,6 +6888,7 @@ F:drivers/gpu
of the display block OR the GPU. Separate the
latter, as it's both a functionally separate block and is of
interest to different folks.
Signed-off-by: Konrad Dybcio
---
MAINTAINERS | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
These are dummy wrappers that do literally nothing interesting.
Remove them.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 81 +++---
3
These are dummy wrappers that do literally nothing interesting.
Remove them.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 273 +---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
Shaving off some cruft
obj files seem to be identical pre and post cleanup which is always
a good sign
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (2):
drm/msm/dsi: Remove dsi_phy_read/write()
drm/msm/dsi: Remove dsi_phy_write_[un]delay()
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
On 18.04.2024 1:07 PM, Dmitry Baryshkov wrote:
> On Thu, Apr 18, 2024 at 11:51:16AM +0200, Konrad Dybcio wrote:
>> On 18.04.2024 1:43 AM, Dmitry Baryshkov wrote:
>>> On Wed, Apr 17, 2024 at 10:02:55PM +0200, Konrad Dybcio wrote:
>>>> On recent (SM8550+) Snapdragon pla
On 18.04.2024 1:49 AM, Dmitry Baryshkov wrote:
> On Wed, Apr 17, 2024 at 10:02:58PM +0200, Konrad Dybcio wrote:
>> There is no need to reinvent the wheel for simple read-match-set logic.
>>
>> Make speedbin discovery and assignment generation independent.
>>
>>
On 18.04.2024 1:39 AM, Dmitry Baryshkov wrote:
> On Wed, Apr 17, 2024 at 10:02:54PM +0200, Konrad Dybcio wrote:
>> Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely
>> identifying the specific SKU and the precise speed bin (in the general
>> meaning
On 18.04.2024 1:43 AM, Dmitry Baryshkov wrote:
> On Wed, Apr 17, 2024 at 10:02:55PM +0200, Konrad Dybcio wrote:
>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>> abstracted through SMEM, instead of being directly available in a fuse.
>>
>> Add s
Add the speedbin masks to ensure only the desired OPPs are available on
chips of a given bin.
Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 -
1 file changed, 20 insertions
There is no need to reinvent the wheel for simple read-match-set logic.
Make speedbin discovery and assignment generation independent.
This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx,
which has no representation in hardware whatshowever.
Signed-off-by: Konrad Dybcio
Add speebin data for A740, as found on SM8550 and derivative SoCs.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index
In preparation for commonizing the speedbin handling code.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index
em
to form something that lets us match OPPs against.
Due to the product code being ignored in the context of Adreno on
production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++---
drivers/gpu/drm/msm/ad
for
things such as Adreno. In the case of Adreno specifically, Pcode is
useless for non-prototype SoCs.
Introduce a getter for the feature code and export it.
Signed-off-by: Konrad Dybcio
---
drivers/soc/qcom/smem.c | 33 +
include/linux/soc/qcom/smem.h
h can only be picked if the drm patches are there.
Depends on:
https://lore.kernel.org/linux-arm-msm/20240412-topic-adreno_nullptr_supphw-v1-1-eb30a1c12...@linaro.org/
Signed-off-by: Konrad Dybcio
---
Changes in v2:
- Separate moving existing and adding new defines
- Fix kerneldoc copypasta
- Remove
In preparation for parsing the chip "feature code" (FC) and "product
code" (PC) (essentially the parameters that let us conclusively
characterize the sillicon we're running on, including various speed
bins), move the socinfo version defines to the public header.
Signed-o
s down the cleanup chain,
explicitly de-allocate the LLC data and free a6xx_gpu instead.
Fixes: 76efc2453d0e ("drm/msm/gpu: Fix crash during system suspend after
unbind")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletio
On 4/12/24 01:49, Elliot Berman wrote:
On Thu, Apr 11, 2024 at 10:24:08PM +0200, Konrad Dybcio wrote:
On 4/11/24 22:09, Elliot Berman wrote:
On Thu, Apr 11, 2024 at 10:05:30PM +0200, Konrad Dybcio wrote:
On 4/11/24 20:55, Elliot Berman wrote:
On Fri, Apr 05, 2024 at 10:41:29AM +0200
On 4/11/24 23:46, Dmitry Baryshkov wrote:
On Fri, 12 Apr 2024 at 00:35, Konrad Dybcio wrote:
On 4/10/24 21:26, Dmitry Baryshkov wrote:
On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
On 4/6/24 05:23, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:32AM +0200
On 4/10/24 21:26, Dmitry Baryshkov wrote:
On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
On 4/6/24 05:23, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted
On 4/11/24 22:09, Elliot Berman wrote:
On Thu, Apr 11, 2024 at 10:05:30PM +0200, Konrad Dybcio wrote:
On 4/11/24 20:55, Elliot Berman wrote:
On Fri, Apr 05, 2024 at 10:41:29AM +0200, Konrad Dybcio wrote:
In preparation for parsing the chip "feature code" (FC) and "pr
On 4/11/24 20:55, Elliot Berman wrote:
On Fri, Apr 05, 2024 at 10:41:29AM +0200, Konrad Dybcio wrote:
In preparation for parsing the chip "feature code" (FC) and "product
code" (PC) (essentially the parameters that let us conclusively
characterize the sillicon we're r
Totally useless.
Signed-off-by: Konrad Dybcio
---
only compile-tested
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 12 ++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++--
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 4
On 4/9/24 20:31, Dmitry Baryshkov wrote:
On Tue, 9 Apr 2024 at 21:27, Konrad Dybcio wrote:
On 4/9/24 20:15, Dmitry Baryshkov wrote:
On Tue, Apr 09, 2024 at 08:07:56PM +0200, Konrad Dybcio wrote:
On 4/9/24 20:04, Dmitry Baryshkov wrote:
On Tue, Apr 09, 2024 at 10:12:00AM -0700, Rob
On 4/6/24 05:23, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.
Add support for SMEM-based speed binning, which
On 4/9/24 20:15, Dmitry Baryshkov wrote:
On Tue, Apr 09, 2024 at 08:07:56PM +0200, Konrad Dybcio wrote:
On 4/9/24 20:04, Dmitry Baryshkov wrote:
On Tue, Apr 09, 2024 at 10:12:00AM -0700, Rob Clark wrote:
On Tue, Apr 9, 2024 at 8:23 AM Dmitry Baryshkov
wrote:
On Tue, Apr 09, 2024 at 05
On 4/9/24 17:24, Dmitry Baryshkov wrote:
On Tue, Apr 09, 2024 at 05:13:15PM +0200, Konrad Dybcio wrote:
On 4/6/24 05:25, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:33AM +0200, Konrad Dybcio wrote:
Add speebin data for A740, as found on SM8550 and derivative SoCs.
Signed-off
On 4/9/24 20:04, Dmitry Baryshkov wrote:
On Tue, Apr 09, 2024 at 10:12:00AM -0700, Rob Clark wrote:
On Tue, Apr 9, 2024 at 8:23 AM Dmitry Baryshkov
wrote:
On Tue, Apr 09, 2024 at 05:12:46PM +0200, Konrad Dybcio wrote:
On 4/6/24 04:56, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10
On 4/6/24 05:25, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:33AM +0200, Konrad Dybcio wrote:
Add speebin data for A740, as found on SM8550 and derivative SoCs.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++
1 file changed, 14
On 4/6/24 04:56, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:31AM +0200, Konrad Dybcio wrote:
From: Neil Armstrong
Usually, speedbin 0 is the "super SKU", a.k.a the one which can clock
the highest. Falling back to it when things go wrong is largely
suboptimal, as more
On 4/6/24 04:21, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:30AM +0200, Konrad Dybcio wrote:
Introduce getters for SoC product and feature codes and export them.
Signed-off-by: Konrad Dybcio
---
[...]
+ /* Ensure the value makes sense */
+ if (raw_code
m/msm/a6xx: Add skeleton A7xx support")
---
Reviewed-by: Konrad DYbcio
Thanks!
Konrad
Add speebin data for A740, as found on SM8550 and derivative SoCs.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno
em
to form something that lets us match OPPs against.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 39 +++---
drivers/gpu/drm/msm/adreno/
Introduce getters for SoC product and feature codes and export them.
Signed-off-by: Konrad Dybcio
---
drivers/soc/qcom/smem.c | 66 +++
include/linux/soc/qcom/smem.h | 2 ++
2 files changed, 68 insertions(+)
diff --git a/drivers/soc/qcom/smem.c b
Add the speedbin masks to ensure only the desired OPPs are available on
chips of a given bin.
Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 -
1 file changed, 20 insertions
e intended "lowest common denominator" bin
in struct adreno_info. If not specified, partial struct initialization
will ensure it's set to zero, retaining previous behavior.
Signed-off-by: Neil Armstrong
[Konrad: clean up, add commit message]
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/m
e more FC/PC defines.
Signed-off-by: Konrad Dybcio
---
drivers/soc/qcom/socinfo.c | 8
include/linux/soc/qcom/socinfo.h | 36
2 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.
in order if we want
to land this in the upcoming cycle.
FWIW I preferred the fuses myself..
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (5):
soc: qcom: Move some socinfo defines to the header, expand them
soc: qcom: smem: Add pcode/fcode getters
drm/msm/adreno: Implement
On 29.03.2024 8:45 AM, Luca Weiss wrote:
> Add the node for the DisplayPort controller found on the SM6350 SoC.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Luca Weiss
> ---
Reviewed-by: Konrad Dybcio
Konrad
uot;arm64: dts: qcom: sc8180x: Add display and gpu nodes")
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 26.03.2024 9:02 PM, Dmitry Baryshkov wrote:
> The property #stream-id-cells is legacy, it is not documented as valid
> for the GPU. Drop it now.
>
> Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
> Signed-off-by: Dmitry Baryshkov
> ---
On 2/23/24 23:48, Trilok Soni wrote:
On 2/23/2024 1:21 PM, Konrad Dybcio wrote:
+ /* Wait 50us for PLL_LOCK_DET bit to go high */
+ usleep_range(50, 55);
+
+ /* Enable PLL output */
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL
On 2/16/24 12:03, Neil Armstrong wrote:
Add GPU nodes for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++
1 file changed, 166 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi
On 2/28/24 19:05, Markus Elfring wrote:
From: Markus Elfring
Date: Wed, 28 Feb 2024 18:45:13 +0100
Add a jump target so that a bit of exception handling can be better reused
at the end of this function implementation.
This issue was transformed by using the Coccinelle software.
On 2/27/24 11:10, Will Deacon wrote:
On Fri, Feb 23, 2024 at 10:21:36PM +0100, Konrad Dybcio wrote:
Bit of a megaseries, bunched together for your testing convenience..
Needs mesa!27665 [1] on the userland part, kmscube happily spins.
I'm feeling quite lukewarm about the memory barriers
Enable the A702 GPU (also marketed as "3D accelerator by qcom [1], lol).
[1]
https://docs.qualcomm.com/bundle/publicresource/87-61720-1_REV_A_QUALCOMM_ROBOTICS_RB1_PLATFORM__QUALCOMM_QRB2210__PRODUCT_BRIEF.pdf
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boo
Add some defines required for A702. Can be substituted with a header
sync after merging mesa!27665 [1].
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27665
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 18 ++
1 file changed, 18
Describe the GPU hardware on the QCM2290.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 154 ++
1 file changed, 154 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
b/arch/arm64/boot/dts
support for it, tested with QCM2290 / RB1.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 92 +++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 18 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 16 +-
3 files changed, 117 insertions
different hardware.
Introduce another set of offsets and a new configure function for the
Huayra PLL found on QCM2290. This is required e.g. for the consumers
of GPUCC_PLL0 to properly start.
Signed-off-by: Konrad Dybcio
---
drivers/clk/qcom/clk-alpha-
Add a driver for the GPU clock controller block found on the QCM2290 SoC.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/gpucc-qcm2290.c | 423
Add device tree bindings for graphics clock controller for Qualcomm
Technology Inc's QCM2290 SoCs.
Signed-off-by: Konrad Dybcio
---
.../bindings/clock/qcom,qcm2290-gpucc.yaml | 77 ++
include/dt-bindings/clock/qcom,qcm2290-gpucc.h | 32 +
2 files changed
/mesa/-/merge_requests/27665
Signed-off-by: Konrad Dybcio
---
Changes in v2:
- Drop applied smmu-bindings patch
- Fix the gpucc bindings patch to be even better
- Reorder HUAYRA_2290 definitions near HUAYRA (..Add HUAYRA_2290
support..)
- Replace weird memory barriers copypasted from msm-5.4
On 2/22/24 10:46, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 11:28, Konrad Dybcio wrote:
On 2/22/24 10:04, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 10:56, Konrad Dybcio wrote:
On 2/22/24 00:41, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 01:19, Bjorn Andersson wrote
On 2/22/24 10:04, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 10:56, Konrad Dybcio wrote:
On 2/22/24 00:41, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 01:19, Bjorn Andersson wrote:
The max frequency listed in the DPU opp-table is 506MHz, this is not
sufficient to drive a 4k@60
On 2/22/24 00:19, Bjorn Andersson wrote:
The RB3gen2 has a USB redriver on APPS_I2C, enable the bus and introduce
the redriver. The plumbing with other components is kept separate for
clarity.
Signed-off-by: Bjorn Andersson
---
Any chance you could add an alias for this I2C bus?
Or all
On 2/22/24 00:41, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 01:19, Bjorn Andersson wrote:
The max frequency listed in the DPU opp-table is 506MHz, this is not
sufficient to drive a 4k@60 display, resulting in constant underrun.
Add the missing MDP_CLK turbo frequency of 608MHz to the
Andersson
---
Reviewed-by: Konrad Dybcio
Konrad
-mode.
Switch the compatible of the mdss_edp instance and make it eDP for the
SC7280 qcard.
Signed-off-by: Bjorn Andersson
---
Reviewed-by: Konrad Dybcio
Konrad
On 20.02.2024 18:31, Dmitry Baryshkov wrote:
> The patch adding Type-C support for sm6115 was misapplied. All the
> orientation switch configuration ended up at the UFS PHY node instead of
> the USB PHY node. Move the data bits to the correct place.
>
> Fixes: a06a2f12f9e2 ("arm64: dts: qcom:
On 19.02.2024 15:49, Dmitry Baryshkov wrote:
> On Mon, 19 Feb 2024 at 15:36, Konrad Dybcio wrote:
>>
>> Enable the A702 GPU (also marketed as "3D accelerator by qcom [1], lol).
>
> Is it not?
Sure, every electronic device is also a heater, I suppose.. I found
this word
On 19.02.2024 15:53, Dmitry Baryshkov wrote:
> On Mon, 19 Feb 2024 at 15:36, Konrad Dybcio wrote:
>>
>> Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL")
>> introduced an entry to the alpha offsets array, but diving into QCM2290
>> downstream
On 19.02.2024 15:54, Andrew Halaney wrote:
> On Mon, Feb 19, 2024 at 02:35:48PM +0100, Konrad Dybcio wrote:
>> Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL")
>> introduced an entry to the alpha offsets array, but diving into QCM2290
>> downstream an
Enable the A702 GPU (also marketed as "3D accelerator by qcom [1], lol).
[1]
https://docs.qualcomm.com/bundle/publicresource/87-61720-1_REV_A_QUALCOMM_ROBOTICS_RB1_PLATFORM__QUALCOMM_QRB2210__PRODUCT_BRIEF.pdf
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/qrb2210-rb1.dt
Add some defines required for A702. Can be substituted with a header
sync after merging mesa!27665 [1].
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27665
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 18 ++
1 file changed, 18
Describe the GPU hardware on the QCM2290.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 154 ++
1 file changed, 154 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index
support for it, tested with QCM2290 / RB1.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 92 +++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 18 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 16 +-
3 files changed, 117 insertions
different hardware.
Introduce another set of offsets and a new configure function for the
Huayra PLL found on QCM2290. This is required e.g. for the consumers
of GPUCC_PLL0 to properly start.
Signed-off-by: Konrad Dybcio
---
drivers/clk/qcom/clk-alpha-
Add a driver for the GPU clock controller block found on the QCM2290 SoC.
Signed-off-by: Konrad Dybcio
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/gpucc-qcm2290.c | 423 +++
3 files changed, 433
The GPU SMMU on QCM2290 nicely fits into the description we already have
for SM61[12]5. Add it.
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu
Add device tree bindings for graphics clock controller for Qualcomm
Technology Inc's QCM2290 SoCs.
Signed-off-by: Konrad Dybcio
---
.../bindings/clock/qcom,qcm2290-gpucc.yaml | 76 ++
include/dt-bindings/clock/qcom,qcm2290-gpucc.h | 32 +
2 files changed
/mesa/-/merge_requests/27665
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (8):
dt-bindings: arm-smmu: Add QCM2290 GPU SMMU
dt-bindings: clock: Add Qcom QCM2290 GPUCC
clk: qcom: clk-alpha-pll: Add HUAYRA_2290 support
clk: qcom: Add QCM2290 GPU clock controller driver
.mbn).
>
> Add this as machine = "qcom,sm7150", because speed-bin values are
> different from atoll (sc7180/sm7125).
>
> Signed-off-by: Danila Tikhonov
> ---
Sorry for the mess on the previous thread!
Reviewed-by: Konrad Dybcio
Konrad
the adreno_is_a750() macro and
> the ADRENO_7XX_GEN3 family id.
>
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 12.02.2024 15:45, Neil Armstrong wrote:
> On 12/02/2024 11:46, Konrad Dybcio wrote:
>> On 12.02.2024 11:37, Neil Armstrong wrote:
>>> Add support for the A750 GPU found on the SM8650 platform
>>>
>>> Unlike the the very close A740 GPU on the SM8550 SoC, th
On 12.02.2024 11:37, Neil Armstrong wrote:
> Add path of the GPU firmware for the SM8650-QRD board
>
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 12.02.2024 11:37, Neil Armstrong wrote:
> Add GPU nodes for the SM8650 platform.
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 169
> +++
> 1 file changed, 169 insertions(+)
>
> diff --git
On 12.02.2024 11:37, Neil Armstrong wrote:
> Add support for the A750 GPU found on the SM8650 platform
>
> Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU
> doesn't have an HWCFG block but a separate register set.
>
> The missing registers are added in the a6xx.xml.h file that
On 12.02.2024 11:37, Neil Armstrong wrote:
> Document the Adreno 750 GMU found on the SM8650 platform.
>
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 21.01.2024 20:41, Adam Skladowski wrote:
> Add node describing wireless connectivity subsystem.
>
> Signed-off-by: Adam Skladowski
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 96 +++
> 1 file changed, 96 insertions(+)
>
> diff --git
On 21.01.2024 20:41, Adam Skladowski wrote:
> Add Adreno GPU node.
>
> Signed-off-by: Adam Skladowski
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 66 +++
> 1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi
>
On 21.01.2024 20:41, Adam Skladowski wrote:
> Add MDSS nodes to support displays on MSM8976 SoC.
>
> Signed-off-by: Adam Skladowski
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 268 +-
> 1 file changed, 264 insertions(+), 4 deletions(-)
>
> diff --git
On 21.01.2024 20:40, Adam Skladowski wrote:
> Add the nodes describing the apps and gpu iommu and its context banks
> that are found on msm8976 SoCs.
>
> Signed-off-by: Adam Skladowski
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 80 +++
> 1 file changed, 80
uninteresting churn, but there are a couple spots in a7xx
paths which update REG_A6XX_foo to REG_A7XX_foo for registers which are
a7xx specific.
Cc: Connor Abbott
Signed-off-by: Rob Clark
---
Acked-by: Konrad Dybcio
Konrad
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