Allow a SMMU device to opt into allocating a TTBR1 pagetable.
The size of the TTBR1 region will be the same as
the TTBR0 size with the sign extension bit set on the highest
bit in the region unless the upstream size is 49 bits and then
the sign-extension bit will be set on the 49th bit.
The
From: Jeremy Gebben
Add support to return the value of the TTBR0 register in response
to a request via DOMAIN_ATTR_TTBR0.
Signed-off-by: Jeremy Gebben
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 13
Instead of checking for a5xx_gpu->gpmu_iova during destroy we
accidently check a5xx_gpu->gpmu_bo.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Pursuant to the arm-smmu-v3 SVM support:
https://lists.linuxfoundation.org/pipermail/iommu/2017-February/020599.html
I felt it would be helpful if I would demonstrate how Qualcomm implements
per-process pagetables for several generations of SoCs and GPUs focusing on the
Adreno A540 GPU and an
Implement support for dynamic domain switching. This feature is
only enabled when the qcom,dynamic device tree attribute for an smmu
instance.
In order to use dynamic domains, a non-dynamic domain must first
be created and attached. The non-dynamic domain must remain
attached while the device is
Add an API to create a dynamic domain from an existing domain.
A dynamic domain is a special IOMMU domain that is attached to
the same device as the parent domain but is backed by separate
pagetables. Devices such as GPUs that support asynchronous
methods for switching pagetables can create
Add a new domain attribute to enable the TTBR1 pagetable for drivers
and devices that support it. This will enabled using a TTBR1 (otherwise
known as a "global" or "system" pagetable for devices that support a split
pagetable scheme for switching pagetables quickly and safely.
Signed-off-by:
From: Jeremy Gebben
In the ARM SMMU architecture, pagetable programming is controlled
by the TTBR0 register. The layout of this
registers varies depending on the pagetable format in use.
In particular, the ASID (address space ID) field is found in
CONTEXTIDR when using
We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c. Plus it is better symmetry to have
the attach and detach at the same code level.
Signed-off-by: Jordan
In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.
This forces a few changes in the gem object however: instead
of using a simple
Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be
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