On Mon, Dec 03, 2018 at 07:02:07PM -0800, Jeykumar Sankaran wrote:
> On 2018-12-03 06:47, Sean Paul wrote:
> > On Tue, Nov 27, 2018 at 02:28:30PM -0800, Jeykumar Sankaran wrote:
> > > Add display port support in DPU by creating hooks
> > > for DP encoder enumeration and encoder mode
> > >
Quoting Matthias Kaehlcke (2018-11-30 16:52:47)
> Allow the PHY drivers to get the ref clock from the DT.
>
> Signed-off-by: Matthias Kaehlcke
> ---
Reviewed-by: Stephen Boyd
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Quoting Matthias Kaehlcke (2018-11-30 16:52:53)
> Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
> hardcoded in the PLL 'driver' for the 10nm PHY.
>
> Signed-off-by: Matthias Kaehlcke
> Reviewed-by: Douglas Anderson
> ---
Reviewed-by: Stephen Boyd
Quoting Matthias Kaehlcke (2018-11-30 16:52:54)
> Add 'xo_board' as ref clock for the DSI PHY, it was previously
> hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Why is driver in quotes?
>
> Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
When trying to get the display up on my sdm845 board I noticed that
the display wouldn't probe if I had the dsi1 node marked as "disabled"
even though my board doesn't use dsi1. It looks like the msm code
adds all nodes to its list of components even if they are disabled. I
believe this doesn't
Hi,
On Fri, Nov 30, 2018 at 4:53 PM Matthias Kaehlcke wrote:
>
> Allow the PHY drivers to get the ref clock from the DT.
>
> Signed-off-by: Matthias Kaehlcke
> ---
> Changes in V3:
> - added note that the ref clock is only required for new DTS
> files/entries
>
> Changes in v2:
> - add the
On Tue, Dec 04, 2018 at 08:48:22AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-30 16:52:54)
> > Add 'xo_board' as ref clock for the DSI PHY, it was previously
> > hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
>
> Why is driver in quotes?
It's not really a full fledged
Hi,
On Mon, Dec 3, 2018 at 6:41 PM Jeykumar Sankaran wrote:
> >> + dsi1: dsi@ae96000 {
> >> + compatible = "qcom,mdss-dsi-ctrl";
> >> + reg = <0xae96000 0x400>;
> >> + reg-names =
Quoting Matthias Kaehlcke (2018-12-04 09:35:49)
> On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
> > Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> > > +
> > > /* custom byte clock divider */
> > > struct clk_bytediv *bytediv;
> > >
> > > @@ -125,7 +127,10 @@
On Tue, Dec 04, 2018 at 08:03:53AM +0100, Andrzej Hajda wrote:
> On 03.12.2018 22:48, Ville Syrjälä wrote:
> > On Thu, Nov 29, 2018 at 09:46:16AM +0100, Andrzej Hajda wrote:
> >> Quite late, hopefully not too late.
> >>
> >>
> >> On 21.11.2018 12:51, Ville Syrjälä wrote:
> >>> On Wed, Nov 21, 2018
On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate. Use default values if the ref
> > clock is not specified.
> >
> > Signed-off-by:
On Mon, Dec 03, 2018 at 03:47:13PM -0700, Jordan Crouse wrote:
> This is a rebase of
>
> https://patchwork.freedesktop.org/series/51214/
>
> On top of
>
> https://gitlab.freedesktop.org/seanpaul/dpu-staging/tags/for_jcrouse
Thanks for the resend, I've pushed it to dpu-staging/for-next
Sean
On Fri, Nov 16, 2018 at 01:42:10PM -0500, Sean Paul wrote:
> From: Sean Paul
>
> This was originally 3 patchsets, but none have gotten full review, so I
> figured I'd package the v2's all up into one set so it's easier to track.
>
> Set 1-
>
On Mon, Dec 3, 2018 at 2:56 PM Sean Paul wrote:
>
> From: Sean Paul
>
> Since dpu_crtc subclasses crtc_state, we need a custom .reset hook in
> order to allocate the right amount of memory to accommodate the
> additional struct members in dpu_crtc_state. So bring it [partially]
> back.
>
>
On Tue, Dec 04, 2018 at 10:51:42AM -0500, Bruce Wang wrote:
> On Mon, Dec 3, 2018 at 2:56 PM Sean Paul wrote:
> >
> > From: Sean Paul
> >
> > Since dpu_crtc subclasses crtc_state, we need a custom .reset hook in
> > order to allocate the right amount of memory to accommodate the
> > additional
Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate. Use default values if the ref
> clock is not specified.
>
> Signed-off-by: Matthias Kaehlcke
> ---
> Changes in v3:
> - use default name and rate if the
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
Reviewed-by: Chris Wilson
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/msm/msm_gem_submit.c
This adds the gpu nodes for the adreno 200 GPU on iMX51 and iMX53, now
supported by the freedreno driver.
The compatible for the iMX51 uses a patchid of 1, which is used by drm/msm
driver to identify the smaller 128KiB GMEM size.
Signed-off-by: Jonathan Marek
---
v4:
added commit message
Quoting Matthias Kaehlcke (2018-11-30 16:52:49)
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> index 26e3a01a99c2b..4a84c69ca0b2b 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> +++
Quoting Matthias Kaehlcke (2018-11-30 16:52:52)
> Add 'xo_board' as ref clock for the DSI PHYs, it was previously
> hardcoded in the PLL 'driver' for the 28nm PHY.
>
> Signed-off-by: Matthias Kaehlcke
> Reviewed-by: Douglas Anderson
> ---
Reviewed-by: Stephen Boyd
On Sat, Dec 01, 2018 at 10:19:11PM -0500, Yangtao Li wrote:
> We already have the DEFINE_SHOW_ATTRIBUTE.There is no need to define
> such a macro separately,so remove DEFINE_DPU_DEBUGFS_SEQ_FOPS.
> Also use DEFINE_SHOW_ATTRIBUTE to simplify some code.
>
> Signed-off-by: Yangtao Li
> ---
>
This allows controlling which of the 8 lanes are used for 6 bit color.
Signed-off-by: Jonathan Marek
---
v3: removed empty line and added documentation
.../devicetree/bindings/display/msm/mdp4.txt | 2 ++
.../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 21 ---
2 files
Document the new amd,imageon compatible, used for non-qcom hardware that
uses the drm/msm driver (iMX5).
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
A2XX has its own very simple MMU.
Added a msm_use_mmu() function because we can't rely on iommu_present to
decide to use MMU or not.
Signed-off-by: Jonathan Marek
---
v3: rebased on msm-next-staging and moved is_a2xx initialization earlier
drivers/gpu/drm/msm/Makefile | 3 +-
On Tue, Dec 4, 2018 at 11:56 AM Robert Foss wrote:
>
> If dma_fence_wait fails to wait for a supplied in-fence in
> msm_ioctl_gem_submit, make sure we release that in-fence.
>
> Also remove this dma_fence_put() from the 'out' label.
>
> Signed-off-by: Robert Foss
> Reviewed-by: Chris Wilson
>
On Tue, Dec 04, 2018 at 08:46:53AM +0100, Andrzej Hajda wrote:
> On 03.12.2018 22:38, Ville Syrjälä wrote:
> > On Thu, Nov 29, 2018 at 10:08:07AM +0100, Andrzej Hajda wrote:
> >> On 21.11.2018 19:19, Laurent Pinchart wrote:
> >>> Hi Ville,
> >>>
> >>> Thank you for the patch.
> >>>
> >>> On
Hi,
On Tue, Dec 4, 2018 at 3:54 PM Jeykumar Sankaran wrote:
>
> DPU is short for the Display Processing Unit. It is the display
> controller on Qualcomm SDM845 chips.
>
> This change adds MDSS and DSI nodes to enable display on the
> target device.
>
> Changes in v2:
> - Beefed up
On 2018-12-03 06:47, Sean Paul wrote:
On Tue, Nov 27, 2018 at 02:28:30PM -0800, Jeykumar Sankaran wrote:
Add display port support in DPU by creating hooks
for DP encoder enumeration and encoder mode
initialization.
This change is based on the SDM845 Display port
driver changes[1].
changes in
DPU is short for the Display Processing Unit. It is the display
controller on Qualcomm SDM845 chips.
This change adds MDSS and DSI nodes to enable display on the
target device.
Changes in v2:
- Beefed up commit message
- Use SoC specific compatibles for mdss and dpu (Rob H)
Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes in v3:
- patch added to the series
---
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
Chnages in v4:
- added "Reviewed-by" tags from Stephen and Doug
Changes in v3:
- added note that the ref clock is only required for new DTS
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v4:
- none
Changes in v3:
- fixed check for
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes in v3:
- added
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate() and
dsi_pll_28nm_clk_recalc_rate()
- pass name of VCO ref clock to pll_28nm_register() instead
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
-
The MSM DSI PHY drivers currently hardcode the name and the rate of
the PHY ref clock. Get the ref clock from the device tree instead.
Note: testing of this series was limited to SDM845 and the 10nm PHY
Major changes in v4:
- always use parent rate for 28nm and 28nm 8960 PHYs
Major changes in
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v4:
- none
Changes in v3:
- fixed check for
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
On Tue, Dec 4, 2018 at 1:04 PM Douglas Anderson wrote:
>
> When trying to get the display up on my sdm845 board I noticed that
> the display wouldn't probe if I had the dsi1 node marked as "disabled"
> even though my board doesn't use dsi1. It looks like the msm code
> adds all nodes to its list
On Sat, Dec 1, 2018 at 10:54 AM Rob Clark wrote:
>
> This solves a problem we see with drm/msm, caused by getting
> iommu_dma_ops while we attach our own domain and manage it directly at
> the iommu API level:
>
> [0038] user address but active_mm is swapper
> Internal error:
Hi Ville,
On Tuesday, 4 December 2018 21:13:20 EET Ville Syrjälä wrote:
> On Tue, Dec 04, 2018 at 08:46:53AM +0100, Andrzej Hajda wrote:
> > On 03.12.2018 22:38, Ville Syrjälä wrote:
> >> On Thu, Nov 29, 2018 at 10:08:07AM +0100, Andrzej Hajda wrote:
> >>> On 21.11.2018 19:19, Laurent Pinchart
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