Re: [Freedreno] [PATCH 03/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

2017-02-06 Thread Rob Clark 
On Mon, Feb 6, 2017 at 2:20 PM, Emil Velikov  wrote:
> Hi Jordan,
>
> On 6 February 2017 at 17:39, Jordan Crouse  wrote:
>> Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
>> user sets 'hint' to non-zero it means that they want a IOVA for the
>> GEM object instead of a mmap() offset. Return the iova in the 'offset'
>> member.
>>
>> Signed-off-by: Jordan Crouse 
>> ---
>>  drivers/gpu/drm/msm/msm_drv.c | 29 +
>>  include/uapi/drm/msm_drm.h|  4 ++--
>>  2 files changed, 27 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
>> index e29bb66..1e4e022 100644
>> --- a/drivers/gpu/drm/msm/msm_drv.c
>> +++ b/drivers/gpu/drm/msm/msm_drv.c
>> @@ -677,6 +677,17 @@ static int msm_ioctl_gem_cpu_fini(struct drm_device 
>> *dev, void *data,
>> return ret;
>>  }
>>
>> +static int msm_ioctl_gem_info_iova(struct drm_device *dev,
>> +   struct drm_gem_object *obj, uint64_t *iova)
>> +{
>> +   struct msm_drm_private *priv = dev->dev_private;
>> +
>> +   if (!priv->gpu)
>> +   return -EINVAL;
>> +
> Not too familiar with msm so perhaps a silly question: how can we trigger 
> this ?

if gpu has not loaded (for example, missing firmware, or kernel does
not have iommu, etc)

>> +   return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
>> +}
>> +
>>  static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
>> struct drm_file *file)
>>  {
>> @@ -684,14 +695,24 @@ static int msm_ioctl_gem_info(struct drm_device *dev, 
>> void *data,
>> struct drm_gem_object *obj;
>> int ret = 0;
>>
>> -   if (args->pad)
>> -   return -EINVAL;
>> -
> Please keep the input validation before doing any work (the lookup below).

+1 for making this args->flags and checking against
GEM_INFO_VALID_FLAGS up front.  We may want to use some of those other
bits some day

>> obj = drm_gem_object_lookup(file, args->handle);
>> if (!obj)
>> return -ENOENT;
>>
>> -   args->offset = msm_gem_mmap_offset(obj);
>> +   /*
>> +* If the hint variable is set, it means that the user wants a IOVA 
>> for
>> +* this buffer.  Return the address from the GPU because that is
>> +* probably what it is looking for
>> +*/
>> +   if (args->hint) {
> One could also rename hint to flags. Regardless of the name you can
> use hint/flags as a bitmask.
>
>> +   uint64_t iova;
>> +
>> +   ret = msm_ioctl_gem_info_iova(dev, obj, );
>> +   if (!ret)
>> +   args->offset = iova;
>> +   } else {
>> +   args->offset = msm_gem_mmap_offset(obj);
>> +   }
>>
>> drm_gem_object_unreference_unlocked(obj);
>>
>> diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
>> index 4d5d6a2..045ad20 100644
>> --- a/include/uapi/drm/msm_drm.h
>> +++ b/include/uapi/drm/msm_drm.h
>> @@ -105,8 +105,8 @@ struct drm_msm_gem_new {
>>
>>  struct drm_msm_gem_info {
>> __u32 handle; /* in */
>> -   __u32 pad;
>> -   __u64 offset; /* out, offset to pass to mmap() */
>> +   __u32 hint;   /* in */
> Please add explicit #define for the currently valid hints/flags.
>
>> +   __u64 offset; /* out, mmap() offset if hint is 0, iova if 1 
>> */
> Other drivers have used anonymous unions to improve the naming, in
> such situations.
>
> struct drm_msm_gem_info {
> __u32 handle;   /* in */
> __u32 hint; /* in */
> union { /* out */
>   __u64 offset; /* offset if hint is FOO */
>   __u64 iova;   /* iova if hint is BAR */
> };
> };

is anon union legit for uabi?  I was under the impression that for
some reason it was not.  But I could be wrong.

BR,
-R

>
> Thanks
> Emil
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Re: [Freedreno] [PATCH 03/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

2017-02-06 Thread Emil Velikov 
Hi Jordan,

On 6 February 2017 at 17:39, Jordan Crouse  wrote:
> Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
> user sets 'hint' to non-zero it means that they want a IOVA for the
> GEM object instead of a mmap() offset. Return the iova in the 'offset'
> member.
>
> Signed-off-by: Jordan Crouse 
> ---
>  drivers/gpu/drm/msm/msm_drv.c | 29 +
>  include/uapi/drm/msm_drm.h|  4 ++--
>  2 files changed, 27 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index e29bb66..1e4e022 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -677,6 +677,17 @@ static int msm_ioctl_gem_cpu_fini(struct drm_device 
> *dev, void *data,
> return ret;
>  }
>
> +static int msm_ioctl_gem_info_iova(struct drm_device *dev,
> +   struct drm_gem_object *obj, uint64_t *iova)
> +{
> +   struct msm_drm_private *priv = dev->dev_private;
> +
> +   if (!priv->gpu)
> +   return -EINVAL;
> +
Not too familiar with msm so perhaps a silly question: how can we trigger this ?

> +   return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
> +}
> +
>  static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
> struct drm_file *file)
>  {
> @@ -684,14 +695,24 @@ static int msm_ioctl_gem_info(struct drm_device *dev, 
> void *data,
> struct drm_gem_object *obj;
> int ret = 0;
>
> -   if (args->pad)
> -   return -EINVAL;
> -
Please keep the input validation before doing any work (the lookup below).

> obj = drm_gem_object_lookup(file, args->handle);
> if (!obj)
> return -ENOENT;
>
> -   args->offset = msm_gem_mmap_offset(obj);
> +   /*
> +* If the hint variable is set, it means that the user wants a IOVA 
> for
> +* this buffer.  Return the address from the GPU because that is
> +* probably what it is looking for
> +*/
> +   if (args->hint) {
One could also rename hint to flags. Regardless of the name you can
use hint/flags as a bitmask.

> +   uint64_t iova;
> +
> +   ret = msm_ioctl_gem_info_iova(dev, obj, );
> +   if (!ret)
> +   args->offset = iova;
> +   } else {
> +   args->offset = msm_gem_mmap_offset(obj);
> +   }
>
> drm_gem_object_unreference_unlocked(obj);
>
> diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
> index 4d5d6a2..045ad20 100644
> --- a/include/uapi/drm/msm_drm.h
> +++ b/include/uapi/drm/msm_drm.h
> @@ -105,8 +105,8 @@ struct drm_msm_gem_new {
>
>  struct drm_msm_gem_info {
> __u32 handle; /* in */
> -   __u32 pad;
> -   __u64 offset; /* out, offset to pass to mmap() */
> +   __u32 hint;   /* in */
Please add explicit #define for the currently valid hints/flags.

> +   __u64 offset; /* out, mmap() offset if hint is 0, iova if 1 */
Other drivers have used anonymous unions to improve the naming, in
such situations.

struct drm_msm_gem_info {
__u32 handle;   /* in */
__u32 hint; /* in */
union { /* out */
  __u64 offset; /* offset if hint is FOO */
  __u64 iova;   /* iova if hint is BAR */
};
};


Thanks
Emil
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Re: [Freedreno] [PATCH 00/11] drm/msm: A5XX preemption

2017-02-06 Thread Alex Deucher 
On Mon, Feb 6, 2017 at 12:59 PM, Daniel Vetter  wrote:
> On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote:
>> This series of patches implements multiple ringbuffers and preemption for 
>> Adreno
>> A5XX targets. Preemption allows a command to be interrupted at specific
>> preemption points and execution switched to a different ringbuffer.
>>
>> The software alogrithm uses preemption to enforce quality of service for
>> priority levels - commands to a certain ring preempt the rings of lower
>> priority. Note that priority is a software construct; the driver chooses a 
>> ring
>> to switch to and the hardware executes. This is important because it shows 
>> that
>> preemption can be used for things other than priority (timeslices for 
>> quality of
>> service for example).
>>
>> This initial series implements 4 ringbuffers to give sufficient coverage for 
>> the
>> range of priority levels requested by the GLES and compute extensions. The
>> targeted ringbuffer is specified in the command submission flags. The default
>> ring is 0 (lowest priority).
>
> Link to userspace part that implements these extensions? Also which
> gles/compute extensions are you talking about? Asking not just because of
> the open source userspace requirement, but also because we want to
> upstream a scheduler on the i915 side. Getting alignment on that across
> drm drivers would be sweet.

FWIW, we have had a GPU scheduler in amdgpu for several years now.  We
purposely tried to keep it largely separate from our driver so others
could leverage it if they wanted to.  See
drivers/gpu/drm/amd/scheduler in the kernel.

Alex

>
> Adding intel-gfx, I'll poke the folks working on this too.
> -Daniel
>
>>
>> Jordan
>>
>> Jordan Crouse (11):
>>   drm/msm: Make sure to detach the MMU during GPU cleanup
>>   drm/msm: Improve the zap shader
>>   drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA
>>   drm/msm: Remove idle function hook
>>   drm/msm: get an iova from the address space instead of an id
>>   drm/msm: Add a struct to pass configuration to msm_gpu_init()
>>   drm/msm: Remove memptrs->wptr
>>   drm/msm: Support multiple ringbuffers
>>   drm/msm: Shadow current pointer in the ring until command is complete
>>   drm/msm: Make the value of RB_CNTL (almost) generic
>>   drm/msm: Implement preemption for A5XX targets
>>
>>  drivers/gpu/drm/msm/Makefile  |   1 +
>>  drivers/gpu/drm/msm/adreno/a3xx_gpu.c |  13 +-
>>  drivers/gpu/drm/msm/adreno/a4xx_gpu.c |  13 +-
>>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 278 +-
>>  drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 106 +
>>  drivers/gpu/drm/msm/adreno/a5xx_power.c   |  11 +-
>>  drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 367 
>> ++
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 215 +++--
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  42 ++--
>>  drivers/gpu/drm/msm/dsi/dsi_host.c|  15 +-
>>  drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c  |   8 +-
>>  drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  18 +-
>>  drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |   3 -
>>  drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c |  13 +-
>>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c  |   5 +-
>>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  11 +-
>>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |   4 -
>>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  13 +-
>>  drivers/gpu/drm/msm/msm_drv.c |  43 ++--
>>  drivers/gpu/drm/msm/msm_drv.h |  27 ++-
>>  drivers/gpu/drm/msm/msm_fb.c  |  15 +-
>>  drivers/gpu/drm/msm/msm_fbdev.c   |  10 +-
>>  drivers/gpu/drm/msm/msm_fence.c   |  85 +--
>>  drivers/gpu/drm/msm/msm_fence.h   |  13 +-
>>  drivers/gpu/drm/msm/msm_gem.c | 124 +++---
>>  drivers/gpu/drm/msm/msm_gem.h |   5 +-
>>  drivers/gpu/drm/msm/msm_gem_submit.c  |  14 +-
>>  drivers/gpu/drm/msm/msm_gpu.c | 140 +++-
>>  drivers/gpu/drm/msm/msm_gpu.h |  54 -
>>  drivers/gpu/drm/msm/msm_kms.h |   3 +
>>  drivers/gpu/drm/msm/msm_ringbuffer.c  |  14 +-
>>  drivers/gpu/drm/msm/msm_ringbuffer.h  |  21 +-
>>  include/uapi/drm/msm_drm.h|   9 +-
>>  33 files changed, 1324 insertions(+), 389 deletions(-)
>>  create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_preempt.c
>>
>> --
>> 1.9.1
>>
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>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [Freedreno] [Intel-gfx] [PATCH 00/11] drm/msm: A5XX preemption

2017-02-06 Thread Rob Clark 
On Mon, Feb 6, 2017 at 1:23 PM, Daniel Stone  wrote:
> Hi,
>
> On 6 February 2017 at 17:59, Daniel Vetter  wrote:
>> On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote:
>>> This initial series implements 4 ringbuffers to give sufficient coverage 
>>> for the
>>> range of priority levels requested by the GLES and compute extensions. The
>>> targeted ringbuffer is specified in the command submission flags. The 
>>> default
>>> ring is 0 (lowest priority).
>>
>> Link to userspace part that implements these extensions? Also which
>> gles/compute extensions are you talking about? Asking not just because of
>> the open source userspace requirement, but also because we want to
>> upstream a scheduler on the i915 side. Getting alignment on that across
>> drm drivers would be sweet.
>
> Assuming he meant EGL rather than GLES, this is the usual one:
> https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt
>

There was an RFC for this from Chris.. not sure if it landed yet, but
that is what I was planning to use from the userspace side.

Probably first step would be to enable this without preemption points.
Although I think I have a reasonable idea how the preemption points
work..

BR,
-R
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Re: [Freedreno] [PATCH 00/11] drm/msm: A5XX preemption

2017-02-06 Thread Daniel Stone 
Hi,

On 6 February 2017 at 17:59, Daniel Vetter  wrote:
> On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote:
>> This initial series implements 4 ringbuffers to give sufficient coverage for 
>> the
>> range of priority levels requested by the GLES and compute extensions. The
>> targeted ringbuffer is specified in the command submission flags. The default
>> ring is 0 (lowest priority).
>
> Link to userspace part that implements these extensions? Also which
> gles/compute extensions are you talking about? Asking not just because of
> the open source userspace requirement, but also because we want to
> upstream a scheduler on the i915 side. Getting alignment on that across
> drm drivers would be sweet.

Assuming he meant EGL rather than GLES, this is the usual one:
https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt

Cheers,
Daniel
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[Freedreno] [pull] drm/msm: msm-next for 4.11

2017-02-06 Thread Rob Clark 
Hi Dave,

The big things this time around are:
1) support for hw cursor on newer mdp5 devices (snapdragon 820+,
tested on db820c)
2) dsi encoder cleanup
3) gpu dt bindings cleanup so we can get the gpu nodes merged upstream

The following changes since commit 99743ae4c5f52f8f8ceb17783056fcc9b4f8b64c:

  Merge branch 'drm-etnaviv-next' of
https://git.pengutronix.de/git/lst/linux into drm-next (2017-02-03
05:41:58 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~robclark/linux msm-next

for you to fetch changes up to 21c42da18ef128ca8fb4cc4ead888f5c61e3916a:

  drm/msm: return -EFAULT if copy_from_user() fails (2017-02-06 11:28:45 -0500)


Archit Taneja (22):
  drm/msm/mdp5: cfg: Add pipe_cursor block
  drm/msm/mdp5: Update generated headers
  drm/msm/dsi: Update generated headers
  drm/msm/dsi: Set msm_dsi->encoders before initializing bridge
  drm/msm: Construct only one encoder for DSI
  drm/msm: Set encoder's mode of operation using a kms func
  drm/msm/mdp5: Prepare for merging video and command encoders
  drm/msm/mdp5: Create single encoder per interface (INTF)
  drm/msm/mdp5: cfg: Change count to unsigned int
  drm/msm/mdp5: Create only as many CRTCs as we need
  drm/msm/mdp5: Prepare CRTC/LM for empty stages
  drm/msm/mdp5: Use plane helpers to configure src/dst rectangles
  drm/msm/mdp5: Configure COLOR3_OUT propagation
  drm/msm/mdp5: Misc cursor plane bits
  drm/msm/mdp5: Add cursor planes
  drm/msm/mdp5: Refactor mdp5_plane_atomic_check
  drm/msm/mdp5: Add support for legacy cursor updates
  drm/msm/dsi: Don't error if a DSI host doesn't have a device connected
  drm/msm/dsi: Add 8x96 info in dsi_cfg
  drm/msm/dsi: Add a PHY op that initializes version specific stuff
  drm/msm/dsi: Reset both PHYs before clock operation for dual DSI
  drm/msm/dsi: Add PHY/PLL for 8x96

Dan Carpenter (1):
  drm/msm: return -EFAULT if copy_from_user() fails

Hai Li (4):
  drm/msm/dsi: Return more timings from PHY to host
  drm/msm/dsi: Pass down use case to PHY
  drm/msm/dsi: Move PHY operations out of host
  drm/msm/dsi: Add new method to calculate 14nm PHY timings

Rob Clark (5):
  drm/msm: remove qcom,gpu-pwrlevels bindings
  drm/msm: drop qcom,chipid
  drm/msm: drop quirks binding
  drm/msm: drop _clk suffix from clk names
  drm/msm: let gpu wire up it's own fault handler

 .../devicetree/bindings/display/msm/gpu.txt|   38 +-
 drivers/gpu/drm/msm/Kconfig|7 +
 drivers/gpu/drm/msm/Makefile   |2 +
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c  |   21 +-
 drivers/gpu/drm/msm/adreno/adreno_device.c |   62 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c|1 -
 drivers/gpu/drm/msm/adreno/adreno_gpu.h|4 +-
 drivers/gpu/drm/msm/dsi/dsi.c  |   18 +-
 drivers/gpu/drm/msm/dsi/dsi.h  |   51 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h  |  269 -
 drivers/gpu/drm/msm/dsi/dsi_cfg.c  |   25 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.h  |1 +
 drivers/gpu/drm/msm/dsi/dsi_host.c |   97 +-
 drivers/gpu/drm/msm/dsi/dsi_manager.c  |  254 +++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c  |  239 -
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h  |   20 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c |  169 +++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c |5 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c |6 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c|5 +-
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c  |   12 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h  |   11 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 1104 
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c|   28 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h|   48 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c|   10 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h|3 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c|  135 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c   |   73 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c|   14 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h|4 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c|   77 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c|  123 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h|   45 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c   |8 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c  |  181 +++-
 drivers/gpu/drm/msm/mdp/mdp_kms.h  |1 +
 drivers/gpu/drm/msm/msm_atomic.c   |   26 +-
 drivers/gpu/drm/msm/msm_drv.c  |   20 +

[Freedreno] [PATCH 03/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

2017-02-06 Thread Jordan Crouse 
Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_drv.c | 29 +
 include/uapi/drm/msm_drm.h|  4 ++--
 2 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index e29bb66..1e4e022 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -677,6 +677,17 @@ static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, 
void *data,
return ret;
 }
 
+static int msm_ioctl_gem_info_iova(struct drm_device *dev,
+   struct drm_gem_object *obj, uint64_t *iova)
+{
+   struct msm_drm_private *priv = dev->dev_private;
+
+   if (!priv->gpu)
+   return -EINVAL;
+
+   return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
+}
+
 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
struct drm_file *file)
 {
@@ -684,14 +695,24 @@ static int msm_ioctl_gem_info(struct drm_device *dev, 
void *data,
struct drm_gem_object *obj;
int ret = 0;
 
-   if (args->pad)
-   return -EINVAL;
-
obj = drm_gem_object_lookup(file, args->handle);
if (!obj)
return -ENOENT;
 
-   args->offset = msm_gem_mmap_offset(obj);
+   /*
+* If the hint variable is set, it means that the user wants a IOVA for
+* this buffer.  Return the address from the GPU because that is
+* probably what it is looking for
+*/
+   if (args->hint) {
+   uint64_t iova;
+
+   ret = msm_ioctl_gem_info_iova(dev, obj, );
+   if (!ret)
+   args->offset = iova;
+   } else {
+   args->offset = msm_gem_mmap_offset(obj);
+   }
 
drm_gem_object_unreference_unlocked(obj);
 
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 4d5d6a2..045ad20 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -105,8 +105,8 @@ struct drm_msm_gem_new {
 
 struct drm_msm_gem_info {
__u32 handle; /* in */
-   __u32 pad;
-   __u64 offset; /* out, offset to pass to mmap() */
+   __u32 hint;   /* in */
+   __u64 offset; /* out, mmap() offset if hint is 0, iova if 1 */
 };
 
 #define MSM_PREP_READ0x01
-- 
1.9.1

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[Freedreno] [PATCH 04/11] drm/msm: Remove idle function hook

2017-02-06 Thread Jordan Crouse 
There isn't any generic code that uses ->idle so remove it.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 4 ++--
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c   | 4 ++--
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c   | 9 -
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h   | 1 +
 drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
 drivers/gpu/drm/msm/msm_gpu.h   | 1 -
 6 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index b999349..fc4fd2d 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -40,6 +40,7 @@
 extern bool hang_debug;
 
 static void a3xx_dump(struct msm_gpu *gpu);
+static bool a3xx_idle(struct msm_gpu *gpu);
 
 static bool a3xx_me_init(struct msm_gpu *gpu)
 {
@@ -65,7 +66,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
 
gpu->funcs->flush(gpu);
-   return gpu->funcs->idle(gpu);
+   return a3xx_idle(gpu);
 }
 
 static int a3xx_hw_init(struct msm_gpu *gpu)
@@ -448,7 +449,6 @@ static void a3xx_dump(struct msm_gpu *gpu)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
-   .idle = a3xx_idle,
.irq = a3xx_irq,
.destroy = a3xx_destroy,
 #ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 511bc85..6bc948b 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -31,6 +31,7 @@
 
 extern bool hang_debug;
 static void a4xx_dump(struct msm_gpu *gpu);
+static bool a4xx_idle(struct msm_gpu *gpu);
 
 /*
  * a4xx_enable_hwcg() - Program the clock control registers
@@ -137,7 +138,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
 
gpu->funcs->flush(gpu);
-   return gpu->funcs->idle(gpu);
+   return a4xx_idle(gpu);
 }
 
 static int a4xx_hw_init(struct msm_gpu *gpu)
@@ -538,7 +539,6 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t 
*value)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
-   .idle = a4xx_idle,
.irq = a4xx_irq,
.destroy = a4xx_destroy,
 #ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 23eeed2..2074f64 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -391,7 +391,7 @@ static int a5xx_me_init(struct msm_gpu *gpu)
 
gpu->funcs->flush(gpu);
 
-   return gpu->funcs->idle(gpu) ? 0 : -EINVAL;
+   return a5xx_idle(gpu) ? 0 : -EINVAL;
 }
 
 static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu,
@@ -699,7 +699,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
OUT_RING(gpu->rb, 0x0F);
 
gpu->funcs->flush(gpu);
-   if (!gpu->funcs->idle(gpu))
+   if (!a5xx_idle(gpu))
return -EINVAL;
}
 
@@ -716,7 +716,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
OUT_RING(gpu->rb, 0x);
 
gpu->funcs->flush(gpu);
-   if (!gpu->funcs->idle(gpu))
+   if (!a5xx_idle(gpu))
return -EINVAL;
} else {
/* Print a warning so if we die, we know why */
@@ -790,7 +790,7 @@ static inline bool _a5xx_check_idle(struct msm_gpu *gpu)
A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT);
 }
 
-static bool a5xx_idle(struct msm_gpu *gpu)
+bool a5xx_idle(struct msm_gpu *gpu)
 {
/* wait for CP to drain ringbuffer: */
if (!adreno_idle(gpu))
@@ -1091,7 +1091,6 @@ static void a5xx_show(struct msm_gpu *gpu, struct 
seq_file *m)
.last_fence = adreno_last_fence,
.submit = a5xx_submit,
.flush = adreno_flush,
-   .idle = a5xx_idle,
.irq = a5xx_irq,
.destroy = a5xx_destroy,
.show = a5xx_show,
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
index 1590f84..6b20f28 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
@@ -56,5 +56,6 @@ static inline int spin_usecs(struct msm_gpu *gpu, uint32_t 
usecs,
return -ETIMEDOUT;
 }
 
+bool a5xx_idle(struct msm_gpu *gpu);
 
 #endif /* __A5XX_GPU_H__ */
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c 
b/drivers/gpu/drm/msm/adreno/a5xx_power.c
index 72d52c7..ed0802e 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
@@ -194,7 +194,7 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu)
 
gpu->funcs->flush(gpu);
 
-   if (!gpu->funcs->idle(gpu)) {
+

[Freedreno] [PATCH 01/11] drm/msm: Make sure to detach the MMU during GPU cleanup

2017-02-06 Thread Jordan Crouse 
We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c.  Plus it is better symmetry to have
the attach and detach at the same code level.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 29 +++--
 drivers/gpu/drm/msm/msm_gpu.c   |  3 ---
 2 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index bc2224b..acb685a 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -421,18 +421,27 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
return 0;
 }
 
-void adreno_gpu_cleanup(struct adreno_gpu *gpu)
+void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
 {
-   if (gpu->memptrs_bo) {
-   if (gpu->memptrs)
-   msm_gem_put_vaddr(gpu->memptrs_bo);
+   struct msm_gpu *gpu = _gpu->base;
+
+   if (adreno_gpu->memptrs_bo) {
+   if (adreno_gpu->memptrs)
+   msm_gem_put_vaddr(adreno_gpu->memptrs_bo);
+
+   if (adreno_gpu->memptrs_iova)
+   msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->id);
+
+   drm_gem_object_unreference_unlocked(adreno_gpu->memptrs_bo);
+   }
+   release_firmware(adreno_gpu->pm4);
+   release_firmware(adreno_gpu->pfp);
 
-   if (gpu->memptrs_iova)
-   msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
+   msm_gpu_cleanup(gpu);
 
-   drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
+   if (gpu->aspace) {
+   gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
+   iommu_ports, ARRAY_SIZE(iommu_ports));
+   msm_gem_address_space_destroy(gpu->aspace);
}
-   release_firmware(gpu->pm4);
-   release_firmware(gpu->pfp);
-   msm_gpu_cleanup(>base);
 }
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index d8420be..403cca1 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -711,9 +711,6 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
msm_ringbuffer_destroy(gpu->rb);
}
 
-   if (gpu->aspace)
-   msm_gem_address_space_destroy(gpu->aspace);
-
if (gpu->fctx)
msm_fence_context_free(gpu->fctx);
 }
-- 
1.9.1

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[Freedreno] [PATCH 05/11] drm/msm: get an iova from the address space instead of an id

2017-02-06 Thread Jordan Crouse 
In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.

This forces a few changes in the gem object however: instead
of using a simple index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c |   8 +-
 drivers/gpu/drm/msm/adreno/a5xx_power.c   |   5 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   |   6 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c|  15 +++-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c  |   8 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  18 ++---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |   3 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c |  13 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c  |   5 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  11 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |   4 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  13 ++--
 drivers/gpu/drm/msm/msm_drv.c |  14 
 drivers/gpu/drm/msm/msm_drv.h |  25 +++---
 drivers/gpu/drm/msm/msm_fb.c  |  15 ++--
 drivers/gpu/drm/msm/msm_fbdev.c   |  10 ++-
 drivers/gpu/drm/msm/msm_gem.c | 124 +-
 drivers/gpu/drm/msm/msm_gem.h |   4 +-
 drivers/gpu/drm/msm/msm_gem_submit.c  |   4 +-
 drivers/gpu/drm/msm/msm_gpu.c |   8 +-
 drivers/gpu/drm/msm/msm_gpu.h |   1 -
 drivers/gpu/drm/msm/msm_kms.h |   3 +
 22 files changed, 184 insertions(+), 133 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 2074f64..546280c 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -415,7 +415,7 @@ static struct drm_gem_object *a5xx_ucode_load_bo(struct 
msm_gpu *gpu,
}
 
if (iova) {
-   int ret = msm_gem_get_iova(bo, gpu->id, iova);
+   int ret = msm_gem_get_iova(bo, gpu->aspace, iova);
 
if (ret) {
drm_gem_object_unreference_unlocked(bo);
@@ -757,19 +757,19 @@ static void a5xx_destroy(struct msm_gpu *gpu)
 
if (a5xx_gpu->pm4_bo) {
if (a5xx_gpu->pm4_iova)
-   msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->aspace);
drm_gem_object_unreference_unlocked(a5xx_gpu->pm4_bo);
}
 
if (a5xx_gpu->pfp_bo) {
if (a5xx_gpu->pfp_iova)
-   msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->aspace);
drm_gem_object_unreference_unlocked(a5xx_gpu->pfp_bo);
}
 
if (a5xx_gpu->gpmu_bo) {
if (a5xx_gpu->gpmu_bo)
-   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
}
 
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c 
b/drivers/gpu/drm/msm/adreno/a5xx_power.c
index ed0802e..2fdee44 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
@@ -301,7 +301,8 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
if (IS_ERR(a5xx_gpu->gpmu_bo))
goto err;
 
-   if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->id, _gpu->gpmu_iova))
+   if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->aspace,
+   _gpu->gpmu_iova))
goto err;
 
ptr = msm_gem_get_vaddr(a5xx_gpu->gpmu_bo);
@@ -330,7 +331,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
 
 err:
if (a5xx_gpu->gpmu_iova)
-   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
if (a5xx_gpu->gpmu_bo)
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
 
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index acb685a..247f017 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -61,7 +61,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
 
DBG("%s", gpu->name);
 
-   ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, >rb_iova);
+   ret = msm_gem_get_iova(gpu->rb->bo, gpu->aspace, >rb_iova);
if (ret) {
gpu->rb_iova = 0;
dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
@@ -411,7 +411,7 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
return -ENOMEM;
}
 
-   ret =

[Freedreno] [PATCH 07/11] drm/msm: Remove memptrs->wptr

2017-02-06 Thread Jordan Crouse 
memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
 2 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 53f9dea..4c3e9b3 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -123,7 +123,6 @@ void adreno_recover(struct msm_gpu *gpu)
/* reset completed fence seqno: */
adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
adreno_gpu->memptrs->rptr  = 0;
-   adreno_gpu->memptrs->wptr  = 0;
 
gpu->funcs->pm_resume(gpu);
 
@@ -256,7 +255,6 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
seq_printf(m, "fence:%d/%d\n", adreno_gpu->memptrs->fence,
gpu->fctx->last_fence);
seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
-   seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
 
gpu->funcs->pm_resume(gpu);
@@ -296,7 +294,6 @@ void adreno_dump_info(struct msm_gpu *gpu)
printk("fence:%d/%d\n", adreno_gpu->memptrs->fence,
gpu->fctx->last_fence);
printk("rptr: %d\n", get_rptr(adreno_gpu));
-   printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
printk("rb wptr:  %d\n", get_wptr(gpu->rb));
 }
 
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index e8d55b0..fdf4ef3 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -85,7 +85,6 @@ struct adreno_info {
 
 struct adreno_rbmemptrs {
volatile uint32_t rptr;
-   volatile uint32_t wptr;
volatile uint32_t fence;
 };
 
-- 
1.9.1

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[Freedreno] [PATCH 06/11] drm/msm: Add a struct to pass configuration to msm_gpu_init()

2017-02-06 Thread Jordan Crouse 
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 ++--
 drivers/gpu/drm/msm/msm_gpu.c   | 13 ++---
 drivers/gpu/drm/msm/msm_gpu.h   | 11 ++-
 3 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 247f017..53f9dea 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -344,6 +344,7 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs 
*funcs)
 {
struct adreno_platform_config *config = pdev->dev.platform_data;
+   struct msm_gpu_config adreno_gpu_config  = { 0 };
struct msm_gpu *gpu = _gpu->base;
int ret;
 
@@ -364,9 +365,16 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
 
+   adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
+   adreno_gpu_config.irqname = "kgsl_3d0_irq";
+
+   adreno_gpu_config.va_start = SZ_16M;
+   adreno_gpu_config.va_end = 0x;
+
+   adreno_gpu_config.ringsz = RB_SIZE;
+
ret = msm_gpu_init(drm, pdev, _gpu->base, >base,
-   adreno_gpu->info->name, "kgsl_3d0_reg_memory", 
"kgsl_3d0_irq",
-   RB_SIZE);
+   adreno_gpu->info->name, _gpu_config);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index d336c24..bc75425 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -570,7 +570,7 @@ static irqreturn_t irq_handler(int irq, void *data)
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-   const char *name, const char *ioname, const char *irqname, int 
ringsz)
+   const char *name, struct msm_gpu_config *config)
 {
struct iommu_domain *iommu;
int i, ret;
@@ -606,14 +606,14 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
 
/* Map registers: */
-   gpu->mmio = msm_ioremap(pdev, ioname, name);
+   gpu->mmio = msm_ioremap(pdev, config->ioname, name);
if (IS_ERR(gpu->mmio)) {
ret = PTR_ERR(gpu->mmio);
goto fail;
}
 
/* Get Interrupt: */
-   gpu->irq = platform_get_irq_byname(pdev, irqname);
+   gpu->irq = platform_get_irq_byname(pdev, config->irqname);
if (gpu->irq < 0) {
ret = gpu->irq;
dev_err(drm->dev, "failed to get irq: %d\n", ret);
@@ -657,9 +657,8 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
 */
iommu = iommu_domain_alloc(_bus_type);
if (iommu) {
-   /* TODO 32b vs 64b address space.. */
-   iommu->geometry.aperture_start = SZ_16M;
-   iommu->geometry.aperture_end = 0x;
+   iommu->geometry.aperture_start = config->va_start;
+   iommu->geometry.aperture_end = config->va_end;
 
dev_info(drm->dev, "%s: using IOMMU\n", name);
gpu->aspace = msm_gem_address_space_create(>dev,
@@ -678,7 +677,7 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
 
/* Create ringbuffer: */
mutex_lock(>struct_mutex);
-   gpu->rb = msm_ringbuffer_new(gpu, ringsz);
+   gpu->rb = msm_ringbuffer_new(gpu, config->ringsz);
mutex_unlock(>struct_mutex);
if (IS_ERR(gpu->rb)) {
ret = PTR_ERR(gpu->rb);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index ad6d13a..cc6530f 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -28,6 +28,14 @@
 struct msm_gem_submit;
 struct msm_gpu_perfcntr;
 
+struct msm_gpu_config {
+   const char *ioname;
+   const char *irqname;
+   uint64_t va_start;
+   uint64_t va_end;
+   unsigned int ringsz;
+};
+
 /* So far, with hardware that I've seen to date, we can have:
  *  + zero, one, or two z180 2d cores
  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
@@ -205,7 +213,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-   const char

[Freedreno] [PATCH 10/11] drm/msm: Make the value of RB_CNTL (almost) generic

2017-02-06 Thread Jordan Crouse 
We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.

The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++-
 drivers/gpu/drm/msm/msm_gpu.h   |  5 +
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 44a95ea..aca1fc3 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -21,7 +21,6 @@
 #include "msm_gem.h"
 #include "msm_mmu.h"
 
-#define RB_BLKSIZE 32
 
 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
 {
@@ -71,11 +70,14 @@ int adreno_hw_init(struct msm_gpu *gpu)
}
}
 
-   /* Setup REG_CP_RB_CNTL: */
+   /*
+* Setup REG_CP_RB_CNTL.  The same value is used across targets (with
+* the excpetion of A430 that disables the RPTR shadow) - the cacluation
+* for the ringbuffer size and block size is moved to msm_gpu.h for the
+* pre-processor to deal with and the A430 variant is ORed in here
+*/
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
-   /* size is log2(quad-words): */
-   AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) |
-   AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
+   MSM_GPU_RB_CNTL_DEFAULT |
(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
 
/* Setup ringbuffer address - use ringbuffer[0] for GPU init */
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 38d826a..50fef27 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -135,6 +135,11 @@ struct msm_gpu {
 
 /* It turns out that all targets use the same ringbuffer size */
 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
+#define MSM_GPU_RINGBUFFER_BLKSIZE 32
+
+#define MSM_GPU_RB_CNTL_DEFAULT \
+   (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
+   AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
 
 static inline struct msm_ringbuffer *__get_ring(struct msm_gpu *gpu, int index)
 {
-- 
1.9.1

___
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[Freedreno] [PATCH 02/11] drm/msm: Improve the zap shader

2017-02-06 Thread Jordan Crouse 
Simply the code, use snprintf correctly and make sure that we memset
the rest of the segment if the memory size in the ELF file is larger
than the file size.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 60 +--
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 5f8b368..23eeed2 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -31,11 +31,11 @@ static inline bool _check_segment(const struct elf32_phdr 
*phdr)
phdr->p_memsz);
 }
 
-static int __pil_tz_load_image(struct platform_device *pdev,
+static int zap_load_segments(struct platform_device *pdev,
const struct firmware *mdt, const char *fwname,
void *fwptr, size_t fw_size, unsigned long fw_min_addr)
 {
-   char str[64] = { 0 };
+   char filename[64];
const struct elf32_hdr *ehdr = (struct elf32_hdr *) mdt->data;
const struct elf32_phdr *phdrs = (struct elf32_phdr *) (ehdr + 1);
const struct firmware *fw;
@@ -53,16 +53,18 @@ static int __pil_tz_load_image(struct platform_device *pdev,
offset = (phdr->p_paddr - fw_min_addr);
 
/* Request the file containing the segment */
-   snprintf(str, sizeof(str) - 1, "%s.b%02d", fwname, i);
+   snprintf(filename, sizeof(filename), "%s.b%02d", fwname, i);
 
-   ret = request_firmware(, str, >dev);
+   ret = request_firmware(, filename, >dev);
if (ret) {
-   dev_err(>dev, "Failed to load segment %s\n", str);
+   dev_err(>dev, "Failed to load segment %s\n",
+   filename);
break;
}
 
if (offset + fw->size > fw_size) {
-   dev_err(>dev, "Segment %s is too big\n", str);
+   dev_err(>dev, "Segment %s is too big\n",
+   filename);
ret = -EINVAL;
release_firmware(fw);
break;
@@ -70,15 +72,19 @@ static int __pil_tz_load_image(struct platform_device *pdev,
 
/* Copy the segment into place */
memcpy(fwptr + offset, fw->data, fw->size);
+
+   if (phdr->p_memsz > phdr->p_filesz)
+   memset(fwptr + fw->size, 0,
+   phdr->p_memsz - phdr->p_filesz);
release_firmware(fw);
}
 
return ret;
 }
 
-static int _pil_tz_load_image(struct platform_device *pdev)
+static int zap_load_mdt(struct platform_device *pdev)
 {
-   char str[64] = { 0 };
+   char filename[64];
const char *fwname;
const struct elf32_hdr *ehdr;
const struct elf32_phdr *phdrs;
@@ -86,7 +92,6 @@ static int _pil_tz_load_image(struct platform_device *pdev)
phys_addr_t fw_min_addr, fw_max_addr;
dma_addr_t fw_phys;
size_t fw_size;
-   u32 pas_id;
void *ptr;
int i, ret;
 
@@ -95,11 +100,10 @@ static int _pil_tz_load_image(struct platform_device *pdev)
 
if (!qcom_scm_is_available()) {
dev_err(>dev, "SCM is not available\n");
-   return -EINVAL;
+   return -EPROBE_DEFER;
}
 
ret = of_reserved_mem_device_init(>dev);
-
if (ret) {
dev_err(>dev, "Unable to set up the reserved memory\n");
return ret;
@@ -112,17 +116,12 @@ static int _pil_tz_load_image(struct platform_device 
*pdev)
return -EINVAL;
}
 
-   if (of_property_read_u32(pdev->dev.of_node, "qcom,pas-id", _id)) {
-   dev_err(>dev, "Could not read the pas ID\n");
-   return -EINVAL;
-   }
-
-   snprintf(str, sizeof(str) - 1, "%s.mdt", fwname);
+   snprintf(filename, sizeof(filename), "%s.mdt", fwname);
 
/* Request the MDT file for the firmware */
-   ret = request_firmware(, str, >dev);
+   ret = request_firmware(, filename, >dev);
if (ret) {
-   dev_err(>dev, "Unable to load %s\n", str);
+   dev_err(>dev, "Unable to load %s\n", filename);
return ret;
}
 
@@ -151,7 +150,7 @@ static int _pil_tz_load_image(struct platform_device *pdev)
fw_size = (size_t) (fw_max_addr - fw_min_addr);
 
/* Verify the MDT header */
-   ret = qcom_scm_pas_init_image(pas_id, mdt->data, mdt->size);
+   ret = qcom_scm_pas_init_image(13, mdt->data, mdt->size);
if (ret) {
dev_err(>dev, "Invalid firmware metadata\n");
goto out;
@@ -163,18 +162,19 @@ static int _pil_tz_load_image(struct platform_device 
*pdev)
goto out;
 
/* Set up the newly allocated memory region */
-   ret