[Freedreno] [PATCH] drm/msm: fix leak in failed get_pages

leanup. Signed-off-by: Prakash Kamliya <pkaml...@codeaurora.org> Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/m

[Freedreno] [PATCH] drm/msm: Memory leak bug fix

This patch fixes a possible memory leak in get_pages() Prakash Kamliya (1): drm/msm: fix leak in failed get_pages drivers/gpu/drm/msm/msm_gem.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) -- 1.9.1 ___ Freedreno mailing

[Freedreno] [PATCH] drm/msm: fix leak in failed get_pages

leanup. Signed-off-by: Prakash Kamliya <pkaml...@codeaurora.org> Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/m

Re: [Freedreno] [PATCH 04/10] drm/msm/gpu: Convert the GPU show function to use the GPU state

On 4/18/2018 4:14 AM, Jordan Crouse wrote: Convert the existing GPU show function to use the GPU state to dump the information rather than reading it directly from the hardware. This will require an additional step to capture the state before dumping it for the existing nodes but it will

Re: [Freedreno] [PATCH 06/10] drm/msm/gpu: Capture the GPU state on a GPU hang

On 4/18/2018 4:14 AM, Jordan Crouse wrote: Capture the GPU state on a GPU hang and store it for later playback via the devcoredump facility. Only one crash state is stored at a time on the assumption that the first hang is usually the most interesting. The existing crash state can be cleared

Re: [Freedreno] [PATCH 06/10] drm/msm/gpu: Capture the GPU state on a GPU hang

On 5/23/2018 4:50 PM, Sharat Masetty wrote: On 4/18/2018 4:14 AM, Jordan Crouse wrote: Capture the GPU state on a GPU hang and store it for later playback via the devcoredump facility. Only one crash state is stored at a time on the assumption that the first hang is usually the most

[Freedreno] [PATCH 0/3] drm/msm: re-factor devfreq common code

This series re-factors the devfreq code a bit in preparation for the upcoming A6x related devfreq changes. The code applies cleanly on 4.17 and has been verified on DB820C. Sharat Masetty (3): drm/msm: suspend devfreq on init drm/msm: move suspend/resume devfreq to their own functions drm

[Freedreno] [PATCH 3/3] drm/msm: re-factor devfreq code

dependent. Additionally on targets where the clocks are completely controlled by the on chip microcontroller, fetching and setting the current GPU frequency will be different. This patch aims to embrace these differences by re-factoring the devfreq code a bit. Signed-off-by: Sharat Masetty <sm

[Freedreno] [PATCH 1/3] drm/msm: suspend devfreq on init

GPU is powered on. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 1c09acf..d7586f2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c

[Freedreno] [PATCH 2/3] drm/msm: move suspend/resume devfreq to their own functions

This is needed for hardware revisions which do not rely on the generic suspend, resume handlers for power management. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.c | 26 ++ drivers/gpu/drm/msm/msm_gpu.h | 2 ++ 2 files c

[Freedreno] [PATCH v4 1/3] drm/msm: suspend devfreq on init

GPU is powered on. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 1c09acf..d7586f2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm

[Freedreno] [PATCH v4 0/3] re-factor devfreq common code

move suspend/resume devfreq to their own functions"(for now) Sharat Masetty (3): drm/msm: suspend devfreq on init drm/msm: re-factor devfreq code drm/msm: unregister devfreq upon clean up drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 16 drivers/gpu/drm/msm/msm_gpu.c

[Freedreno] [PATCH v4 3/3] drm/msm: unregister devfreq upon clean up

Call the devfreq_remove_device() API to remove the GPU devfreq instance during GPU driver cleanup. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index ffa5b77

[Freedreno] [PATCH v2] drm/msm: Add OUT_RING64() helper macro

This patch adds a simple helper function to help write 64 bit payloads to the ringbuffer. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 drivers/gpu/drm/msm/adreno/a5xx_power.c | 3 +-- drivers/gpu/drm/msm/msm_ringbuffer.h| 6 ++ 3 files

[Freedreno] [PATCH v2 2/3] drm/msm: move suspend/resume devfreq to their own functions

This is needed for hardware revisions which do not rely on the generic suspend, resume handlers for power management. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 23 +++ drivers/gpu/drm/msm/msm_gpu.h | 2 ++ 2 files changed, 17 insertions(+), 8

[Freedreno] [PATCH v2 0/3] drm/msm: re-factor devfreq common code

This series re-factors the devfreq code a bit in preparation for the upcoming A6x related devfreq changes. The code applies cleanly on 4.17 and has been verified on DB820C. V2: Addressed code review comments from Jordan Crouse. Sharat Masetty (3): drm/msm: suspend devfreq on init drm/msm

[Freedreno] [PATCH v2 3/3] drm/msm: re-factor devfreq code

dependent. Additionally on targets where the clocks are completely controlled by the on chip microcontroller, fetching and setting the current GPU frequency will be different. This patch aims to embrace these differences by re-factoring the devfreq code a bit. Signed-off-by: Sharat Masetty

[Freedreno] [PATCH v2 1/3] drm/msm: suspend devfreq on init

GPU is powered on. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 1c09acf..d7586f2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm

[Freedreno] [PATCH] drm/msm: Add OUT_RING64() helper macro

This patch adds a simple helper function to help write 64 bit payloads to the ringbuffer. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 drivers/gpu/drm/msm/adreno/a5xx_power.c | 3 +-- drivers/gpu/drm/msm/msm_ringbuffer.h| 6 ++ 3 files

[Freedreno] [PATCH v3 0/4] re-factor devfreq common code

This series re-factors the devfreq code a bit in preparation for the upcoming A6x related devfreq changes. The code applies cleanly on 4.17 and has been verified on DB820C. V2: Addressed code review comments from Jordan Crouse. V3: Added a new patch for devfreq cleanup. Sharat Masetty (4): drm

[Freedreno] [PATCH v3 4/4] drm/msm: unregister devfreq upon clean up

Call the devfreq_remove_device() API to remove the GPU devfreq instance during GPU driver cleanup. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 43e36d7

[Freedreno] [PATCH 1/4] drm/msm: Add submitqueue setup and close

This patch adds a bit of infrastructure to give the different Adreno targets the flexibility to setup the submitqueues per their needs. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.h | 7 +++ drivers/gpu/drm/msm/msm_submitqueue.

[Freedreno] [PATCH 0/4] Preemption support for A6xx targets

vels, each with different granularities and different switch-out--switch-in times. While this patch only enables the first preemption level i.e. preemption at the ringbuffer level, support for more finer grained preemption levels will follow after more testing. Sharat Masetty (4): drm/msm: Add submitq

[Freedreno] [PATCH 4/4] drm/msm/A6xx: Enable preemption for A6xx targets

This patch simply increases the number of available ringbuffers, therefore enabling preemption. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/

[Freedreno] [PATCH 2/4] drm/msm: Add new PM4 type7 opcodes

-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index fb605a3..f0fd80e 100644 --- a/drivers/gpu/d

Re: [Freedreno] [PATCH 5/5] drm/msm/A6x: Add devfreq support in A6x

On 8/23/2018 9:30 PM, Jordan Crouse wrote: On Thu, Aug 23, 2018 at 02:48:31PM +0530, Sharat Masetty wrote: Implement routines to estimate GPU busy time and fetching the current frequency for the polling interval. This is required by the devfreq framework which recommends a frequency change

Re: [Freedreno] [PATCH 3/5] drm/msm/adreno: Load the firmware before bringing up the hardware

On 8/6/2018 11:03 PM, Jordan Crouse wrote: Failure to load firmware is the primary reason to fail adreno_load_gpu(). Try to load it first before going into the hardware initialization code and unwinding it. This is important for a6xx because the GMU gets loaded from the runtime power code and

[Freedreno] [PATCH v2 4/5] drm/msm: re-factor devfreq code

will be target dependent. Additionally on targets where the clocks are completely controlled by the on chip microcontroller, fetching and setting the current GPU frequency will be different. This patch aims to embrace these differences by re-factoring the devfreq code a bit. Signed-off-by: Sharat Masetty

[Freedreno] [PATCH v2 0/5] msm/drm: A6xx DCVS series

This patch series starts off with a few bug fixes in devfreq code, followed by refactoring the devfreq code needed for supporting different chipsets, and ends with adding devfreq support for A6xx. Sharat Masetty (5): drm/msm: suspend devfreq on init drm/msm: unregister devfreq upon clean up

[Freedreno] [PATCH v2 2/5] drm/msm: unregister devfreq upon clean up

Call the devfreq_remove_device() API to remove the GPU devfreq instance during GPU driver cleanup. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 04f9604

[Freedreno] [PATCH v2 5/5] drm/msm/A6xx: Add devfreq support for A6xx

to the GMU. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 39 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ 4 files

[Freedreno] [PATCH v2 3/5] drm/msm/A6xx: Add gmu_read64() register read op

Add a simple function to read 64 registers in the GMU domain Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index a08ee8f

[Freedreno] [PATCH v2 1/5] drm/msm: suspend devfreq on init

GPU is powered on. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 5281a32..04f9604 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm

[Freedreno] [PATCH 1/5] drm/msm: suspend devfreq on init

GPU is powered on. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 5281a32..04f9604 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm

[Freedreno] [PATCH 5/5] drm/msm/A6x: Add devfreq support in A6x

. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 46 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ 4 files changed, 72

[Freedreno] [PATCH 4/5] drm/msm: re-factor devfreq code

dependent. Additionally on targets where the clocks are completely controlled by the on chip microcontroller, fetching and setting the current GPU frequency will be different. This patch aims to embrace these differences by re-factoring the devfreq code a bit. Signed-off-by: Sharat Masetty

[Freedreno] [PATCH 3/5] drm/msm/A6x: Add gmu_read64() register read op

Add a simple function to read 64 registers in the GMU domain Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index a08ee8f

[Freedreno] [PATCH 2/5] drm/msm: unregister devfreq upon clean up

Call the devfreq_remove_device() API to remove the GPU devfreq instance during GPU driver cleanup. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 04f9604

[Freedreno] [PATCH 0/5] msm/drm: A6x DCVS series

This patch series starts off with a few bug fixes in devfreq code, followed by refactoring the devfreq code needed for supporting different chipsets, and ends with adding devfreq support for A6x. Sharat Masetty (5): drm/msm: suspend devfreq on init drm/msm: unregister devfreq upon clean up

[Freedreno] [PATCH v3 3/4] drm/msm: re-factor devfreq code

will be target dependent. Additionally on targets where the clocks are completely controlled by the on chip microcontroller, fetching and setting the current GPU frequency will be different. This patch aims to embrace these differences by re-factoring the devfreq code a bit. Signed-off-by: Sharat Masetty

[Freedreno] [PATCH v3 2/4] drm/msm/A6xx: Add gmu_read64() register read op

Add a simple function to read 64 registers in the GMU domain Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index a08ee8f

[Freedreno] [PATCH v3 4/4] drm/msm/A6xx: Add devfreq support for A6xx

to the GMU. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 39 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ 4 files

[Freedreno] [PATCH 0/6] Preemption support for A6xx targets

evels each with different granularities and different switch-out-switch-in times. This series starts off by adding basic preemption support for A6xx targets, leading up to the tip of the stack which enables L1 level preemption. This is a more fine grained version and faster than the default leve

[Freedreno] [PATCH 6/6] drm/msm/A6xx: Enable L1 preemption level

This patch enables L1 level which is a finer grained preemption at either a draw call or a bin boundary. The worst case switching latency is higher in this case but that is a trade off we make for enabling faster preemption. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drive

[Freedreno] [PATCH 3/6] drm/msm/A6xx: Implement preemption for A6XX targets

-call level or a bin boundary level preemption. This patch enables the basic preemption level, with more fine grained preemption support to follow. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx

[Freedreno] [PATCH 4/6] drm/msm/A6xx: Enable preemption for A6xx targets

This patch simply increases the number of available ringbuffers, therefore enabling preemption. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/

[Freedreno] [PATCH 5/6] drm/msm/Adreno: Refactor some preemption code

The preemption state machine related code is same across Adreno targets, so move the common code to a common header file to avoid code duplication. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 26 --- drivers/gpu/d

[Freedreno] [PATCH 1/6] drm/msm: Add submitqueue setup and close

This patch adds a bit of infrastructure to give the different Adreno targets the flexibility to setup the submitqueues per their needs. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.h | 7 +++ drivers/gpu/drm/msm/msm_submitqueue.

[Freedreno] [PATCH 2/6] drm/msm: Add new PM4 type7 opcodes

-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index fb605a3..f0fd80e 100644 --- a/drivers/gpu/d

Re: [Freedreno] [PATCH 2/5] arm64:dts:sdm845: Add support for GPU LLCC

On 4/4/2018 2:52 AM, Jordan Crouse wrote: On Fri, Mar 23, 2018 at 12:49:48PM +0530, Sharat Masetty wrote: Add client side bindings required for the GPU to use the last level system cache. Also add a register range in the GPU CX domain. Reviewed-by: Jordan Crouse <jcro...@codeaurora.

[Freedreno] [PATCH 1/5] drm/msm: rearrange the gpu_rmw() function

The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/msm_drv

[Freedreno] [PATCH 4/5] drm/msm: Pass mmu features to generic layers

supports. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/

[Freedreno] [PATCH 5/5] drm/msm/A6xx: Add support for using system cache(llc)

h from it. Similarly DOMAIN_ATTR_USE_UPSTREAM_HINT is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/m

[Freedreno] [PATCH 2/5] arm64:dts:sdm845: Add support for GPU LLCC

Add client side bindings required for the GPU to use the last level system cache. Also add a register range in the GPU CX domain. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-)

[Freedreno] [PATCH 3/5] drm/msm/adreno: Add registers in the GPU CX domain

Add the registers needed for configuring the system cache slice info and other parameters in the GPU. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xm

[Freedreno] [PATCH] rnndb/adreno: Add more PM4 opcodes

Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx hardware features. Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- rnndb/adreno/adreno_pm4.xml | 5 + 1 file changed, 5 insertions(+) diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml

Re: [Freedreno] [v2 4/7] drm/msm/adreno: Add registers in the GPU CX domain

On 10/5/2018 8:31 PM, Jordan Crouse wrote: On Fri, Oct 05, 2018 at 06:38:32PM +0530, Sharat Masetty wrote: Add the registers needed for configuring the system cache slice info and other parameters in the GPU. This would conflict with msm-next or at least with the latest update from

Re: [Freedreno] [v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC)

On 10/5/2018 8:37 PM, Jordan Crouse wrote: On Fri, Oct 05, 2018 at 06:38:35PM +0530, Sharat Masetty wrote: The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used

[Freedreno] [PATCH] rnndb: Add additional a6xx registers in gpu CX

Add a few additional registers in the CX domain needed to implement system cache support for a6xx. --- rnndb/adreno/a6xx.xml | 5 + 1 file changed, 5 insertions(+) diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml index b2bd64b..78ba1ce 100644 --- a/rnndb/adreno/a6xx.xml +++

[Freedreno] [PATCH 2/3] drm/msm: Check if target supports crash dump capture

This patch simply checks first to see if the target can support crash dump capture before proceeding. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index

[Freedreno] [PATCH 0/3] drm/msm: Fix gpu recovery path

A few fixes for issues that I have seen in recovery path. The fix in lib/string is probably not needed anymore with the fixes in drm/msm, but I added it here nonetheless as it is good to have. Sharat Masetty (3): lib/string: Pass the input gfp flags to kmalloc drm/msm: Check if target

[Freedreno] [PATCH 1/3] lib/string: Pass the input gfp flags to kmalloc

Pass the user sent gfp flags to kmalloc() calls. This helps calling the functions in user desired contexts. Signed-off-by: Sharat Masetty --- lib/string_helpers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/string_helpers.c b/lib/string_helpers.c index 29c490e

[Freedreno] [PATCH 3/3] drm/msm: Fix task dump in gpu recovery

immediately, this way the task stays afloat until we need it and we also get to use the desired gfp flags. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm

Re: [Freedreno] [PATCH 08/13] drm/msm/gpu: Rearrange the code that collects the task during a hang

On 8/4/2018 10:47 PM, Rob Clark wrote: On Thu, Jul 12, 2018 at 3:48 PM Chris Wilson wrote: Quoting Jordan Crouse (2018-07-12 19:59:25) Do a bit of cleanup to prepare for upcoming changes to pass the hanging task comm and cmdline to the crash dump function. Signed-off-by: Jordan Crouse

[Freedreno] [PATCH 3/3] drm/msm: Use Hardware counters for perf profiling

This patch attempts to make use of the hardware counters for GPU busy % estimation when possible and skip using the software counters as it also accounts for software side delays. This should help give more accurate representation of the GPU workload. Signed-off-by: Sharat Masetty --- drivers

[Freedreno] [PATCH 0/3] drm/msm: Revive GPU workload profiling

could have piggybacked on the devfreq samples and accumulated the busytimes, but I chose not to, since it puts a dependency on the gpu devfreq which in itself is an optional feature. There is one pending issue with GPU recovery + sampling use case, which I plan to address soon. Sharat Masetty (3

[Freedreno] [PATCH 2/3] drm/msm/a6xx: Move power counter selectable to resume()

this to get sane perf values in all cases. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c0cd3ac

[Freedreno] [RFC PATCH] drm/scheduler: Add drm_sched_job_cleanup

the fence_put(finished_fence) from the scheduler to the drivers handler of free_job(). The drivers get to use this new API. This is done so that the layer creating the sched object is the one freeing up the resources as well. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

[Freedreno] [PATCH v2] drm/scheduler: Add drm_sched_job_cleanup

moving the dma_fence_put(finished_fence) to the drivers ops free handler routines. Signed-off-by: Sharat Masetty --- Changes from v1: Addressed review comments from Christian Koenig drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 ++ drivers

[Freedreno] [PATCH] drm/msm: Optimize GPU crashstate capture read path

ter with the dev_coredump once the encoding of the buffers is complete. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 35 +++-- drivers/gpu/drm/msm/msm_gpu.c | 93 +++-- drivers/gpu/drm/msm/msm_gpu.h | 1 + 3 fi

[Freedreno] [PATCH] drm/msm: Optimize adreno_show_object()

depends on the size of the data captured by the driver. This is certainly not desirable and does not scale well with large captures. This patch encodes the buffer only once in the read path. With this there is an immediate >10X speed improvement in crashstate save time. Signed-off-by: Sharat Mase

Re: [Freedreno] [PATCH 07/11] drm/msm/a6xx: Add a6xx gpu state

On 10/17/2018 9:58 PM, Jordan Crouse wrote: Add support for gathering and dumping the a6xx GPU state including registers, GMU registers, indexed registers, shader blocks, context clusters and debugbus. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Makefile|1 +

Re: [Freedreno] [PATCH 2/2] drm/scheduler: Add a start_timeout_notify() backend function

On 11/2/2018 7:07 PM, Koenig, Christian wrote: Am 02.11.18 um 14:25 schrieb Sharat Masetty: On 11/2/2018 4:09 PM, Koenig, Christian wrote: Am 02.11.18 um 11:31 schrieb Sharat Masetty: Add an optional backend function op which will let the scheduler clients know when the timeout got

[Freedreno] [PATCH 2/2] drm/scheduler: Add a start_timeout_notify() backend function

-off-by: Sharat Masetty --- Here is an example of how I plan to use this new function callback. [1] https://patchwork.freedesktop.org/patch/254227/ drivers/gpu/drm/scheduler/sched_main.c | 7 ++- include/drm/gpu_scheduler.h| 6 ++ 2 files changed, 12 insertions(+), 1 deletion

Re: [Freedreno] [PATCH] drm/msm: Optimize GPU crashstate capture read path

Thanks for the comments Jordan - On 11/1/2018 8:34 PM, Jordan Crouse wrote: On Thu, Nov 01, 2018 at 02:05:41PM +0530, Sharat Masetty wrote: When the userspace tries to read the crashstate dump, the read side implementation in the driver currently ascii85 encodes all the binary buffers

Re: [Freedreno] [PATCH 2/2] drm/scheduler: Add a start_timeout_notify() backend function

On 11/2/2018 4:09 PM, Koenig, Christian wrote: Am 02.11.18 um 11:31 schrieb Sharat Masetty: Add an optional backend function op which will let the scheduler clients know when the timeout got scheduled on the scheduler instance. This will help drivers with multiple schedulers(one per ring

[Freedreno] [PATCH] drm/scheduler: Add drm_sched_job_cleanup

moving the dma_fence_put(finished_fence) to the drivers ops free handler routines. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 ++ drivers/gpu/drm/etnaviv/etnaviv_sched.c | 3 +++ drivers/gpu/drm/scheduler

[Freedreno] [PATCH] drm/scheduler: Add drm_sched_suspend/resume timeout functions

in the right direction, I will put this through my testing drill and polish it. IMO I think I prefer the callback approach as it appears to be simple, less error prone for both the scheduler and the drivers. [1] https://patchwork.freedesktop.org/patch/259914/ Signed-off-by: Sharat Masetty --- drivers/gpu

[Freedreno] [PATCH 2/3] include/linux/ascii85: Add ascii85_encode_to_buf()

-by: Sharat Masetty --- include/linux/ascii85.h | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/include/linux/ascii85.h b/include/linux/ascii85.h index 4cc4020..3665899 100644 --- a/include/linux/ascii85.h +++ b/include/linux/ascii85.h @@ -23,8 +23,12

[Freedreno] [PATCH 3/3] drm/msm: Optimize adreno_show_object()

depends on the size of the data captured by the driver. This is certainly not desirable and does not scale well with large captures. This patch encodes the buffer only once in the read path. With this there is an immediate >10X speed improvement in crashstate save time. Signed-off-by: Sharat Mase

[Freedreno] [PATCH 1/3] drm/msm: use kvmalloc for ring data in gpu crashstate

The ringbuffer data to capture at crashtime can end up being large sometimes, and the size can vary from being less than a page to the full size of 32KB. So use the kvmalloc variant that perfectly fits the bill. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4

[Freedreno] [PATCH 1/2] drm/msm/a6xx: Build a6xx_gpu_state under the right conditionals

Build a6xx_gpu_state.c only if either of CONFIG_DEBUG_FS, CONFIG_DEV_COREDUMP is defined. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/Makefile | 5 - drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu

[Freedreno] [PATCH 2/2] drm/msm/a6xx: Fix a typo in a6xx gpu crash state

This patch simply fixes a typo for the name of an indexed register. CP_MEMPOOOL -> CP_MEMPOOL. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/driv

Re: [Freedreno] [PATCH] drm/scheduler: Add drm_sched_suspend/resume timeout functions

On 11/15/2018 12:33 AM, Koenig, Christian wrote: Am 14.11.18 um 18:29 schrieb Sharat Masetty: On 11/8/2018 8:11 PM, Koenig, Christian wrote: Am 08.11.18 um 14:42 schrieb Sharat Masetty: Hi Christian, Can you please review this patch? It is a continuation of the discussion at [1

Re: [Freedreno] [PATCH] drm/scheduler: Add drm_sched_suspend/resume timeout functions

On 11/8/2018 8:11 PM, Koenig, Christian wrote: Am 08.11.18 um 14:42 schrieb Sharat Masetty: Hi Christian, Can you please review this patch? It is a continuation of the discussion at [1]. At first I was thinking of using a cancel for suspend instead of a mod(to an arbitrarily large value

Re: [Freedreno] [PATCH 09/13] drm/msm: Use the DRM common Scheduler

Thanks for the review comments Jordan. I tried to answer a few queries.. please check. On 10/2/2018 12:32 AM, Jordan Crouse wrote: On Mon, Oct 01, 2018 at 06:01:41PM +0530, Sharat Masetty wrote: This patch hooks up the DRM gpu scheduler to the msm DRM driver. The most noticeable changes

Re: [Freedreno] [PATCH 06/13] drm/msm: Use kzalloc for submit struct allocation

On 10/1/2018 11:43 PM, Jordan Crouse wrote: On Mon, Oct 01, 2018 at 06:01:38PM +0530, Sharat Masetty wrote: This patch changes to kzalloc and avoids setting individual submit struct fields to zero manually. I don't think this one is worth it. There are so many members in submit and so few

Re: [Freedreno] [PATCH 7/9] OPP: Add dev_pm_opp_get_interconnect_bw()

On 8/27/2018 8:41 PM, Jordan Crouse wrote: Add dev_pm_opp_get_interconnect_bw() to read the interconnect bandwidth values for a given OPP. Signed-off-by: Jordan Crouse --- drivers/opp/of.c | 36 include/linux/pm_opp.h | 7 +++ 2 files

[Freedreno] [v2 6/7] drm/msm: Pass mmu features to generic layers

supports. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +++- drivers

[Freedreno] [v2 0/7] drm/msm/a6xx: System Cache Support

driver. Minor tweaks and adjustments here and there. Testing: Nothing breaks, but need to profile DDR traffic to see the impact the cache blocks are really making. Please review... Jordan Crouse (1): soc: qcom: llcc-slice: Add error checks for API functions Sharat Masetty (5): drm/msm

[Freedreno] [v2 1/7] soc: qcom: llcc-slice: Add error checks for API functions

From: Jordan Crouse llcc_slice_getd can return a ERR_PTR code on failure. Add a IS_ERR_OR_NULL check to subsequent API calls that use struct llcc_slice_desc to guard against faults and to let the leaf drivers get away with safely using a ERR_PTR() encoded "pointer" in the aftermath of a

[Freedreno] [v2 2/7] iommu/arm-smmu: Add support to use Last level cache

From: Vivek Gautam Qualcomm SoCs have an additional level of cache called as System cache or Last level cache[1]. This cache sits right before the DDR, and is tightly coupled with the memory controller. The cache is available to all the clients present in the SoC system. The clients request

[Freedreno] [v2 3/7] drm/msm: rearrange the gpu_rmw() function

The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 8

[Freedreno] [v2 4/7] drm/msm/adreno: Add registers in the GPU CX domain

Add the registers needed for configuring the system cache slice info and other parameters in the GPU. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm

[Freedreno] [v2 5/7] arm64:dts:sdm845: Add register range for gpu CX

This patch adds a register range in the gpu CX domain. This is needed to support the last level system cache(LLC). Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi

[Freedreno] [PATCH 09/13] drm/msm: Use the DRM common Scheduler

putting the job on the ringbuffer. This should enable us with increased parallelism in the driver which should translate to better performance overall hopefully. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/Makefile | 3 +- drivers

[Freedreno] [PATCH 13/13] drm/msm: Implement better timeout detection

The base scheduler patch has barebones timeout implementation, it does not account for issues like starvation on lower priority rings. This patch enables more accurate measurement on time spent on each ringbuffer, thereby helping us with better timeout detection mechanism. Signed-off-by: Sharat

[Freedreno] [PATCH 11/13] drm/scheduler: Add a timeout_start_notify function op

-by: Sharat Masetty --- drivers/gpu/drm/scheduler/gpu_scheduler.c | 16 +--- include/drm/gpu_scheduler.h | 6 ++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c b/drivers/gpu/drm/scheduler/gpu_scheduler.c index

[Freedreno] [PATCH 12/13] jiffies: add utility function to calculate delta in ms

From: Matteo Croce add jiffies_delta_to_msecs() helper func to calculate the delta between two times and eventually 0 if negative. Suggested-by: Eric Dumazet Signed-off-by: Matteo Croce Reviewed-by: Eric Dumazet Acked-by: Simon Horman Signed-off-by: Pablo Neira Ayuso ---

[Freedreno] [PATCH 08/13] drm/scheduler: set sched->thread to NULL in failure

In cases where the scheduler instance is used a base object of another vendor driver object, it's not clear if the driver can call sched cleanup on the fail path. Set the sched->thread to NULL, so that the vendor driver can safely call drm_sched_fini() during cleanup. Signed-off-by: Sha

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