Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
On 4/11/24 23:46, Dmitry Baryshkov wrote:
On Fri, 12 Apr 2024 at 00:35, Konrad Dybcio wrote:
On 4/10/24 21:26, Dmitry Baryshkov wrote:
On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
On 4/6/24 05:23, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.
Add support for SMEM-based speed binning, which includes getting
"feature code" and "product code" from said source and parsing them
to form something that lets us match OPPs against.
Signed-off-by: Konrad Dybcio
---
[...]
+ }
+
+ ret = qcom_smem_get_product_code();
+ if (ret) {
+ dev_err(dev, "Couldn't get product code from SMEM!\n");
+ return ret;
+ }
+
+ /* Don't consider fcode for external feature codes */
+ if (fcode <= SOCINFO_FC_EXT_RESERVE)
+ fcode = SOCINFO_FC_UNKNOWN;
+
+ *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
+ FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
What about just asking the qcom_smem for the 'gpu_bin' and hiding gory
details there? It almost feels that handling raw PCODE / FCODE here is
too low-level and a subject to change depending on the socinfo format.
No, the FCODE & PCODE can be interpreted differently across consumers.
That's why I wrote about asking for 'gpu_bin'.
I'd rather keep the magic GPU LUTs inside the adreno driver, especially
since not all Snapdragons feature Adreno, but all Adrenos are on
Snapdragons (modulo a2xx but I refuse to make design decisions treating
these equally to e.g. a6xx)
LUTs - yes. I wanted to push (FC << a) | (PC << b) and all the RESERVE
/ UNKNOWN magic there.
Ohh this specifically.. yeah I considered pushing that there as well,
but I realized this is specific to the GPU. The socinfo APIs should
only return a valid/unknown code for both P and F and let the consumer
figure out how to interpret these.
+
+ return ret;
}
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
@@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct
platform_device *pdev,
devm_pm_opp_set_clkname(dev, "core");
}
- if (adreno_read_speedbin(dev, ) || !speedbin)
+ if (adreno_read_speedbin(adreno_gpu, dev, ) || !speedbin)
speedbin = 0x;
- adreno_gpu->speedbin = (uint16_t) (0x & speedbin);
the &= 0x should probably go to the adreno_read_speedbin / nvmem
case. WDYT?
Ok, I can keep it, though realistically if this ever does anything
useful, it likely means the dt is wrong
Yes, but if DT is wrong, we should probably fail in a sensible way. I
just wanted to point out that previously we had this &0x, while your
patch silently removes it.
Right, but I don't believe it actually matters.. If that AND ever did
anything, this was a silent failure with garbage data passed in anyway.
If you really insist, I can remove it separately.
I'd say, up to Rob or up to your consideration.
Konrad
Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
On Fri, 12 Apr 2024 at 00:35, Konrad Dybcio wrote:
>
>
>
> On 4/10/24 21:26, Dmitry Baryshkov wrote:
> > On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 4/6/24 05:23, Dmitry Baryshkov wrote:
> >>> On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> abstracted through SMEM, instead of being directly available in a fuse.
>
> Add support for SMEM-based speed binning, which includes getting
> "feature code" and "product code" from said source and parsing them
> to form something that lets us match OPPs against.
>
> Signed-off-by: Konrad Dybcio
> ---
> >>
> >> [...]
> >>
> >>>
> + }
> +
> + ret = qcom_smem_get_product_code();
> + if (ret) {
> + dev_err(dev, "Couldn't get product code from SMEM!\n");
> + return ret;
> + }
> +
> + /* Don't consider fcode for external feature codes */
> + if (fcode <= SOCINFO_FC_EXT_RESERVE)
> + fcode = SOCINFO_FC_UNKNOWN;
> +
> + *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
> + FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
> >>>
> >>> What about just asking the qcom_smem for the 'gpu_bin' and hiding gory
> >>> details there? It almost feels that handling raw PCODE / FCODE here is
> >>> too low-level and a subject to change depending on the socinfo format.
> >>
> >> No, the FCODE & PCODE can be interpreted differently across consumers.
> >
> > That's why I wrote about asking for 'gpu_bin'.
>
> I'd rather keep the magic GPU LUTs inside the adreno driver, especially
> since not all Snapdragons feature Adreno, but all Adrenos are on
> Snapdragons (modulo a2xx but I refuse to make design decisions treating
> these equally to e.g. a6xx)
LUTs - yes. I wanted to push (FC << a) | (PC << b) and all the RESERVE
/ UNKNOWN magic there.
>
> >
> >>
> >>>
> +
> + return ret;
> }
> int adreno_gpu_init(struct drm_device *drm, struct platform_device
> *pdev,
> @@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct
> platform_device *pdev,
> devm_pm_opp_set_clkname(dev, "core");
> }
> - if (adreno_read_speedbin(dev, ) || !speedbin)
> + if (adreno_read_speedbin(adreno_gpu, dev, ) || !speedbin)
> speedbin = 0x;
> - adreno_gpu->speedbin = (uint16_t) (0x & speedbin);
> >>>
> >>> the &= 0x should probably go to the adreno_read_speedbin / nvmem
> >>> case. WDYT?
> >>
> >> Ok, I can keep it, though realistically if this ever does anything
> >> useful, it likely means the dt is wrong
> >
> > Yes, but if DT is wrong, we should probably fail in a sensible way. I
> > just wanted to point out that previously we had this &0x, while your
> > patch silently removes it.
>
> Right, but I don't believe it actually matters.. If that AND ever did
> anything, this was a silent failure with garbage data passed in anyway.
>
> If you really insist, I can remove it separately.
I'd say, up to Rob or up to your consideration.
--
With best wishes
Dmitry
Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
On 4/10/24 21:26, Dmitry Baryshkov wrote:
On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
On 4/6/24 05:23, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.
Add support for SMEM-based speed binning, which includes getting
"feature code" and "product code" from said source and parsing them
to form something that lets us match OPPs against.
Signed-off-by: Konrad Dybcio
---
[...]
+ }
+
+ ret = qcom_smem_get_product_code();
+ if (ret) {
+ dev_err(dev, "Couldn't get product code from SMEM!\n");
+ return ret;
+ }
+
+ /* Don't consider fcode for external feature codes */
+ if (fcode <= SOCINFO_FC_EXT_RESERVE)
+ fcode = SOCINFO_FC_UNKNOWN;
+
+ *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
+ FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
What about just asking the qcom_smem for the 'gpu_bin' and hiding gory
details there? It almost feels that handling raw PCODE / FCODE here is
too low-level and a subject to change depending on the socinfo format.
No, the FCODE & PCODE can be interpreted differently across consumers.
That's why I wrote about asking for 'gpu_bin'.
I'd rather keep the magic GPU LUTs inside the adreno driver, especially
since not all Snapdragons feature Adreno, but all Adrenos are on
Snapdragons (modulo a2xx but I refuse to make design decisions treating
these equally to e.g. a6xx)
+
+ return ret;
}
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
@@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct
platform_device *pdev,
devm_pm_opp_set_clkname(dev, "core");
}
- if (adreno_read_speedbin(dev, ) || !speedbin)
+ if (adreno_read_speedbin(adreno_gpu, dev, ) || !speedbin)
speedbin = 0x;
- adreno_gpu->speedbin = (uint16_t) (0x & speedbin);
the &= 0x should probably go to the adreno_read_speedbin / nvmem
case. WDYT?
Ok, I can keep it, though realistically if this ever does anything
useful, it likely means the dt is wrong
Yes, but if DT is wrong, we should probably fail in a sensible way. I
just wanted to point out that previously we had this &0x, while your
patch silently removes it.
Right, but I don't believe it actually matters.. If that AND ever did
anything, this was a silent failure with garbage data passed in anyway.
If you really insist, I can remove it separately.
Konrad
Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:
>
>
> On 4/6/24 05:23, Dmitry Baryshkov wrote:
> > On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
> > > On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> > > abstracted through SMEM, instead of being directly available in a fuse.
> > >
> > > Add support for SMEM-based speed binning, which includes getting
> > > "feature code" and "product code" from said source and parsing them
> > > to form something that lets us match OPPs against.
> > >
> > > Signed-off-by: Konrad Dybcio
> > > ---
>
> [...]
>
> >
> > > + }
> > > +
> > > + ret = qcom_smem_get_product_code();
> > > + if (ret) {
> > > + dev_err(dev, "Couldn't get product code from SMEM!\n");
> > > + return ret;
> > > + }
> > > +
> > > + /* Don't consider fcode for external feature codes */
> > > + if (fcode <= SOCINFO_FC_EXT_RESERVE)
> > > + fcode = SOCINFO_FC_UNKNOWN;
> > > +
> > > + *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
> > > + FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
> >
> > What about just asking the qcom_smem for the 'gpu_bin' and hiding gory
> > details there? It almost feels that handling raw PCODE / FCODE here is
> > too low-level and a subject to change depending on the socinfo format.
>
> No, the FCODE & PCODE can be interpreted differently across consumers.
That's why I wrote about asking for 'gpu_bin'.
>
> >
> > > +
> > > + return ret;
> > > }
> > > int adreno_gpu_init(struct drm_device *drm, struct platform_device
> > > *pdev,
> > > @@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct
> > > platform_device *pdev,
> > > devm_pm_opp_set_clkname(dev, "core");
> > > }
> > > - if (adreno_read_speedbin(dev, ) || !speedbin)
> > > + if (adreno_read_speedbin(adreno_gpu, dev, ) || !speedbin)
> > > speedbin = 0x;
> > > - adreno_gpu->speedbin = (uint16_t) (0x & speedbin);
> >
> > the &= 0x should probably go to the adreno_read_speedbin / nvmem
> > case. WDYT?
>
> Ok, I can keep it, though realistically if this ever does anything
> useful, it likely means the dt is wrong
Yes, but if DT is wrong, we should probably fail in a sensible way. I
just wanted to point out that previously we had this &0x, while your
patch silently removes it.
--
With best wishes
Dmitry
Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
On 4/6/24 05:23, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.
Add support for SMEM-based speed binning, which includes getting
"feature code" and "product code" from said source and parsing them
to form something that lets us match OPPs against.
Signed-off-by: Konrad Dybcio
---
[...]
- return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+ u32 fcode, pcode;
+ int ret;
+
+ /* Try reading the speedbin via a nvmem cell first */
+ ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+ if (!ret && ret != -EINVAL)
This is always false.
Right, a better condition would be (!ret || ret != EINVAL)..
+ return ret;
+
+ ret = qcom_smem_get_feature_code();
+ if (ret) {
+ dev_err(dev, "Couldn't get feature code from SMEM!\n");
+ return ret;
This brings in QCOM_SMEM dependency (which is not mentioned in the
Kconfig). Please keep iMX5 hardware in mind, so the dependency should be
optional. Respective functions should be stubbed in the header.
OK, I had this in mind early on, but forgot to actually impl it.
+ }
+
+ ret = qcom_smem_get_product_code();
+ if (ret) {
+ dev_err(dev, "Couldn't get product code from SMEM!\n");
+ return ret;
+ }
+
+ /* Don't consider fcode for external feature codes */
+ if (fcode <= SOCINFO_FC_EXT_RESERVE)
+ fcode = SOCINFO_FC_UNKNOWN;
+
+ *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
+ FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
What about just asking the qcom_smem for the 'gpu_bin' and hiding gory
details there? It almost feels that handling raw PCODE / FCODE here is
too low-level and a subject to change depending on the socinfo format.
No, the FCODE & PCODE can be interpreted differently across consumers.
+
+ return ret;
}
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
@@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct
platform_device *pdev,
devm_pm_opp_set_clkname(dev, "core");
}
- if (adreno_read_speedbin(dev, ) || !speedbin)
+ if (adreno_read_speedbin(adreno_gpu, dev, ) || !speedbin)
speedbin = 0x;
- adreno_gpu->speedbin = (uint16_t) (0x & speedbin);
the &= 0x should probably go to the adreno_read_speedbin / nvmem
case. WDYT?
Ok, I can keep it, though realistically if this ever does anything
useful, it likely means the dt is wrong
Konrad
Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
Hi Konrad,
kernel test robot noticed the following build errors:
[auto build test ERROR on 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd]
url:
https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/soc-qcom-Move-some-socinfo-defines-to-the-header-expand-them/20240405-164231
base: 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd
patch link:
https://lore.kernel.org/r/20240405-topic-smem_speedbin-v1-4-ce2b864251b1%40linaro.org
patch subject: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
config: i386-buildonly-randconfig-003-20240406
(https://download.01.org/0day-ci/archive/20240406/202404061841.njuovdv7-...@intel.com/config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20240406/202404061841.njuovdv7-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202404061841.njuovdv7-...@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/msm/adreno/adreno_gpu.c: In function 'adreno_read_speedbin':
>> drivers/gpu/drm/msm/adreno/adreno_gpu.c:1090:14: error: implicit declaration
>> of function 'FIELD_PREP'; did you mean 'NEED_PGE'?
>> [-Werror=implicit-function-declaration]
*speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
^~
NEED_PGE
cc1: some warnings being treated as errors
vim +1090 drivers/gpu/drm/msm/adreno/adreno_gpu.c
1062
1063 int adreno_read_speedbin(struct adreno_gpu *adreno_gpu,
1064 struct device *dev, u32 *speedbin)
1065 {
1066 u32 fcode, pcode;
1067 int ret;
1068
1069 /* Try reading the speedbin via a nvmem cell first */
1070 ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin",
speedbin);
1071 if (!ret && ret != -EINVAL)
1072 return ret;
1073
1074 ret = qcom_smem_get_feature_code();
1075 if (ret) {
1076 dev_err(dev, "Couldn't get feature code from SMEM!\n");
1077 return ret;
1078 }
1079
1080 ret = qcom_smem_get_product_code();
1081 if (ret) {
1082 dev_err(dev, "Couldn't get product code from SMEM!\n");
1083 return ret;
1084 }
1085
1086 /* Don't consider fcode for external feature codes */
1087 if (fcode <= SOCINFO_FC_EXT_RESERVE)
1088 fcode = SOCINFO_FC_UNKNOWN;
1089
> 1090 *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
1091 FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
1092
1093 return ret;
1094 }
1095
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
Hi Konrad,
kernel test robot noticed the following build errors:
[auto build test ERROR on 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd]
url:
https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/soc-qcom-Move-some-socinfo-defines-to-the-header-expand-them/20240405-164231
base: 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd
patch link:
https://lore.kernel.org/r/20240405-topic-smem_speedbin-v1-4-ce2b864251b1%40linaro.org
patch subject: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
config: i386-buildonly-randconfig-001-20240406
(https://download.01.org/0day-ci/archive/20240406/202404061839.0wagfxwj-...@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project
6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20240406/202404061839.0wagfxwj-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202404061839.0wagfxwj-...@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/msm/adreno/adreno_gpu.c:1090:14: error: call to undeclared
>> function 'FIELD_PREP'; ISO C99 and later do not support implicit function
>> declarations [-Wimplicit-function-declaration]
1090 | *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
| ^
1 error generated.
vim +/FIELD_PREP +1090 drivers/gpu/drm/msm/adreno/adreno_gpu.c
1062
1063 int adreno_read_speedbin(struct adreno_gpu *adreno_gpu,
1064 struct device *dev, u32 *speedbin)
1065 {
1066 u32 fcode, pcode;
1067 int ret;
1068
1069 /* Try reading the speedbin via a nvmem cell first */
1070 ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin",
speedbin);
1071 if (!ret && ret != -EINVAL)
1072 return ret;
1073
1074 ret = qcom_smem_get_feature_code();
1075 if (ret) {
1076 dev_err(dev, "Couldn't get feature code from SMEM!\n");
1077 return ret;
1078 }
1079
1080 ret = qcom_smem_get_product_code();
1081 if (ret) {
1082 dev_err(dev, "Couldn't get product code from SMEM!\n");
1083 return ret;
1084 }
1085
1086 /* Don't consider fcode for external feature codes */
1087 if (fcode <= SOCINFO_FC_EXT_RESERVE)
1088 fcode = SOCINFO_FC_UNKNOWN;
1089
> 1090 *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
1091 FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
1092
1093 return ret;
1094 }
1095
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> abstracted through SMEM, instead of being directly available in a fuse.
>
> Add support for SMEM-based speed binning, which includes getting
> "feature code" and "product code" from said source and parsing them
> to form something that lets us match OPPs against.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++
> drivers/gpu/drm/msm/adreno/adreno_gpu.c| 39
> +++---
> drivers/gpu/drm/msm/adreno/adreno_gpu.h| 12 ++---
> 4 files changed, 51 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 4cbdfabbcee5..6776fd80f7a6 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2890,13 +2890,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info
> *info, u32 fuse)
> return UINT_MAX;
> }
>
> -static int a6xx_set_supported_hw(struct device *dev, const struct
> adreno_info *info)
> +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu,
> + struct device *dev,
> + const struct adreno_info *info)
> {
> u32 supp_hw;
> u32 speedbin;
> int ret;
>
> - ret = adreno_read_speedbin(dev, );
> + ret = adreno_read_speedbin(adreno_gpu, dev, );
> /*
>* -ENOENT means that the platform doesn't support speedbin which is
>* fine
> @@ -3056,7 +3058,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>
> a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
>
> - ret = a6xx_set_supported_hw(>dev, config->info);
> + ret = a6xx_set_supported_hw(adreno_gpu, >dev, config->info);
> if (ret) {
> a6xx_destroy(&(a6xx_gpu->base.base));
> return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
> b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index c3703a51287b..901ef767e491 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -6,6 +6,8 @@
> * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
> */
>
> +#include
> +
> #include "adreno_gpu.h"
>
> bool hang_debug = false;
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 074fb498706f..0e4ff532ac3c 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -21,6 +21,9 @@
> #include "msm_gem.h"
> #include "msm_mmu.h"
>
> +#include
> +#include
> +
> static u64 address_space_size = 0;
> MODULE_PARM_DESC(address_space_size, "Override for size of processes private
> GPU address space");
> module_param(address_space_size, ullong, 0600);
> @@ -1057,9 +1060,37 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem
> *adreno_ocmem)
> adreno_ocmem->hdl);
> }
>
> -int adreno_read_speedbin(struct device *dev, u32 *speedbin)
> +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu,
> + struct device *dev, u32 *speedbin)
> {
> - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
> + u32 fcode, pcode;
> + int ret;
> +
> + /* Try reading the speedbin via a nvmem cell first */
> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
> + if (!ret && ret != -EINVAL)
This is always false.
> + return ret;
> +
> + ret = qcom_smem_get_feature_code();
> + if (ret) {
> + dev_err(dev, "Couldn't get feature code from SMEM!\n");
> + return ret;
This brings in QCOM_SMEM dependency (which is not mentioned in the
Kconfig). Please keep iMX5 hardware in mind, so the dependency should be
optional. Respective functions should be stubbed in the header.
> + }
> +
> + ret = qcom_smem_get_product_code();
> + if (ret) {
> + dev_err(dev, "Couldn't get product code from SMEM!\n");
> + return ret;
> + }
> +
> + /* Don't consider fcode for external feature codes */
> + if (fcode <= SOCINFO_FC_EXT_RESERVE)
> + fcode = SOCINFO_FC_UNKNOWN;
> +
> + *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
> + FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);
What about just asking the qcom_smem for the 'gpu_bin' and hiding gory
details there? It almost feels that handling raw PCODE / FCODE here is
too low-level and a subject to change depending on the socinfo format.
> +
> + return ret;
> }
>
> int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> @@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct
> platform_device *pdev,
>
