Re: RFC: C++ PATCH to adjust empty class parameter passing ABI

On Thu, Apr 14, 2016 at 12:25 PM, Jakub Jelinek <ja...@redhat.com> wrote: > On Thu, Apr 14, 2016 at 12:19:26PM +0100, Ramana Radhakrishnan wrote: >> Is this a valid example for what you have in mind ? >> >> struct baz >> { >> char a[1024]; >> };

Re: How to check if two symbols are from same source unit during WPA ?

> > What happens in practice? GCC doesn't put functions in random > partitions. > The data goes into a separate partition AFAIU - it means that all data accesses are as though they are extern references which means there's not necessarily any CSE'ing ability that's available with section

Re: RFC: C++ PATCH to adjust empty class parameter passing ABI

On Thu, Apr 14, 2016 at 11:36 AM, Jakub Jelinek <ja...@redhat.com> wrote: > On Thu, Apr 14, 2016 at 11:25:07AM +0100, Ramana Radhakrishnan wrote: >> > I see the test failing on aarch64-none-linux-gnu (native) >> > with no output, just: >> > spawn [open ...] &

Re: RFC: C++ PATCH to adjust empty class parameter passing ABI

On Thu, Apr 14, 2016 at 10:41 AM, Kyrill Tkachov wrote: > > On 14/04/16 09:02, Christophe Lyon wrote: >> >> On 13 April 2016 at 22:12, Jason Merrill wrote: >>> >>> On 04/13/2016 03:18 PM, Jakub Jelinek wrote: On Wed, Apr 13, 2016 at

Re: [PATCH, testsuite/ARM] Skip pr70496.c for cortex-m devices

On Wed, Apr 6, 2016 at 12:03 PM, Thomas Preudhomme wrote: > Hi, > > Testcase in gcc.target/arm/pr70496.c uses an .arm directive so assumes the > target has an ARM execution state. This patch adds a dg-skip-if directive to > skip that test on Cortex-M targets since

[Patch ARM] Fix PR target/53440 - handle generic thunks better for TARGET_32BIT.

with no regressions. Queued for stage1 now as it isn't technically a regression. regards Ramana Ramana Radhakrishnan <ramana.radhakrish...@arm.com> PR target/53440 * config/arm/arm.c (arm32_output_mi_thunk): New. (arm_output_mi_thunk): Rename to arm_thumb1_mi_thunk.

[Patch ARM] Fix PR 70496 (unified assembler rewrite fall-out)

. regards Ramana 2016-04-01 Ramana Radhakrishnan <ramana.radhakrish...@arm.com> PR target/70496 * config/arm/arm.h (ASM_APP_OFF): Handle TARGET_ARM and TARGET_THUMB. 2016-04-01 Ramana Radhakrishnan <ramana.radhakrish...@arm.com> PR

Re: [Patch ARM] Delete ASM_OUTPUT_DEF and fall back to default .set directive

On 31/03/16 16:41, James Greenhalgh wrote: > > Hi, > > gcc.dg/torture/pr69951.c has been failing for arm*-*-linux* targets, as > we put out "b = a" as a way of defining a symbol alias, which trips an > assembler warning if the left hand side is an instruction name (such as 'b' > for branch, see

[Patch AArch64] Fix PR target/63874

e41d4bd6abbee99628909d4af612504844dee640 Author: Ramana Radhakrishnan <ramana.radhakrish...@arm.com> Date: Thu Mar 31 13:47:33 2016 +0100 fix PR63874 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index cf1239d..6782316 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/

Re: [PATCH] Fix PR31096

On 31/03/16 09:55, Hurugalawadi, Naveen wrote: > +/* { dg-final { scan-assembler-not "addl" } } */ addl is not the mnemonic for add on all architectures Ramana

Re: [PATCH ARM v2] PR69770 -mlong-calls does not affect calls to __gnu_mcount_nc generated by -pg

And some more formatting issues. On 30/03/16 10:33, Ramana Radhakrishnan wrote: > > > On 24/03/16 21:02, Charles Baylis wrote: >> When compiling with -mlong-calls and -pg, calls to the __gnu_mcount_nc >> function are not generated as long calls. >> >>

Re: [PATCH ARM v2] PR69770 -mlong-calls does not affect calls to __gnu_mcount_nc generated by -pg

On 24/03/16 21:02, Charles Baylis wrote: > When compiling with -mlong-calls and -pg, calls to the __gnu_mcount_nc > function are not generated as long calls. > > This is the sequel to this patch > https://gcc.gnu.org/ml/gcc-patches/2016-02/msg00881.html > > This patch fixes the following

Re: [PATCH][ARM][RFC] PR target/65578 Fix gcc.dg/torture/stackalign/builtin-apply-4.c for single-precision fpus

On Tue, Feb 9, 2016 at 5:21 PM, Kyrill Tkachov wrote: > Hi all, > > In this wrong-code PR the builtin-apply-4.c test fails with -flto but only > when targeting an fpu > with only single-precision capabilities. > > bar is a function returing a double. For non-LTO

Re: [PATCH][ARM] Split out armv7ve effective target check

On 23/03/16 11:09, Kyrill Tkachov wrote: > > On 23/03/16 10:33, Kyrill Tkachov wrote: >> >> On 16/03/16 15:54, Ramana Radhakrishnan wrote: >>> On Wed, Mar 2, 2016 at 1:32 PM, Kyrill Tkachov >>> <kyrylo.tkac...@foss.arm.com> wrote: >>>> Hi all,

Re: [PATCH][ARM] Reduce size of arm1020e automaton

On Mon, Feb 29, 2016 at 4:08 PM, Kyrill Tkachov wrote: > Hi all, > > I've had this one sitting in my tree for some time. > The arm1020e automaton has no business being as large as it is (3185 > states). > Most of the bloat is due to overly large reservation durations

Re: [PATCH][ARM] PR driver/70132: Avoid double fclose in driver-arm.c

On Fri, Mar 11, 2016 at 3:32 PM, Kyrill Tkachov wrote: > Hi all, > > As reported in the PR we can end up calling fclose twice on a file, causing > an error. > This patch fixes that by reorganising the logic a bit to ensure we return > after closing > the file the

Re: [GCC][ARM] Skip tests that assume target supports arm mode, when testing M profiles

On Thu, Mar 17, 2016 at 4:39 PM, Andre Vieira (lists) wrote: > Hello, > > This patch skips four tests that assume a target supports ARM mode when > testing M-profiles. > Tested it by running the four tests for A-profiles and M-profiles. > > Is this ok? OK. Ramana

Re: [PATCH][ARM] Split out armv7ve effective target check

On Wed, Mar 2, 2016 at 1:32 PM, Kyrill Tkachov wrote: > Hi all, > > I'm seeing the fails: > FAIL: gcc.target/arm/atomic_loaddi_2.c scan-assembler-times ldrd\tr[0-9]+, > r[0-9]+, \\[r[0-9]+\\] 1 > FAIL: gcc.target/arm/atomic_loaddi_5.c scan-assembler-times

Re: [PATCH][ARM][testsuite][committed] Do not override -mcpu in no-volatile-in-it.c

On Fri, Mar 18, 2016 at 10:31 AM, Andre Vieira (lists) wrote: > On 16/07/15 16:31, Kyrill Tkachov wrote: >> Hi all, >> >> This scan-assembler test was failing for me when testing with an >> explicit /-march=armv7-a variant because >> it clashed with the

Re: [PATCH][ARM][4.9 Backport] PR target/69875 Fix atomic_loaddi expansion

On Wed, Feb 24, 2016 at 11:23 AM, Kyrill Tkachov wrote: > Hi all, > > This is the GCC 4.9 backport of > https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01338.html. > The differences are that TARGET_HAVE_LPAE has to be defined in arm.h in a > different way because > the

Re: [PATCH][ARM][5 Backport] PR target/69875 Fix atomic_loaddi expansion

On Wed, Feb 24, 2016 at 11:23 AM, Kyrill Tkachov wrote: > Hi all, > > This is the GCC 5 backport of > https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01338.html. > The differences are that TARGET_HAVE_LPAE has to be defined in arm.h in a > different way because > the

Re: [RFC PR43721] Optimize a/b and a%b to single divmod call

Hi Prathamesh, Could you split out the ARM specific portions into a separate patch please in a patch series? >@deftypefn {Target Hook} void TARGET_EXPAND_DIVMOD_LIBFUNC (bool >@var{unsignedp}, machine_mode @var{mode}, @var{rtx}, @var{rtx}, rtx >*@var{quot}, rtx *@var{rem}) >Expand divmod

Re: [patch, testsuite, ARM] don't try to execute simd.exp tests on targets without NEON

On Wed, Mar 2, 2016 at 1:33 PM, Andre Vieira (lists) wrote: > On 21/05/15 10:01, Kyrill Tkachov wrote: >> Hi Sandra, >> >> On 21/05/15 06:43, Sandra Loosemore wrote: >>> This is another patch aimed at fixing bugs relating to trying to execute >>> NEON code on a

Re: [PATCH][ARM] Error out of arm_neon.h if compiling for soft-float ABI

On Mon, Feb 29, 2016 at 5:48 PM, Kyrill Tkachov wrote: > Hi all, > > Now that we've moved to pragmas guarding the various intrinsics in > arm_neon.h I think we should still > throw a #error if someone tries to include the header while compiling for > -mfloat-abi=soft.

Re: [AArch64] Disable pcrelative_literal_loads with fix-cortex-a53-843419

On Tue, Jan 26, 2016 at 2:42 PM, Christophe Lyon wrote: > Hi, > > This is a followup to PR63304. > > As discussed in bugzilla, this patch disables pcrelative_literal_loads > when -mfix-cortex-a53-843419 (or its default configure option) is > used. > > I copied the

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

y 2016 at 12:32, Kyrill Tkachov >>> <kyrylo.tkac...@foss.arm.com> wrote: >>>> >>>> On 04/02/16 08:58, Ramana Radhakrishnan wrote: >>>>> >>>>> On Tue, Jun 30, 2015 at 2:15 AM, Jim Wilson <jim.wil...@linaro.org> >>>>> wro

Re: [PATCH][ARM] PR target/70008

On Mon, Mar 7, 2016 at 3:51 AM, Michael Collison wrote: > New patch that adds the predicate "reg_or_arm_rhs_operand" as suggested by > Richard. Tested on all arm and thumb targets as before. > > Okay for trunk? Missing comment on the predicate. Ok, please queue this

Re: [PATCH, ARM] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0

On Thu, Mar 3, 2016 at 9:40 AM, Thomas Preudhomme <thomas.preudho...@foss.arm.com> wrote: > On Friday 15 January 2016 12:45:04 Ramana Radhakrishnan wrote: >> On Wed, Dec 16, 2015 at 9:11 AM, Thomas Preud'homme >> >> <thomas.preudho...@foss.arm.com> wrote: >

Re: [PATCH][ARM] PR rtl-optimization/69904: Disallow copying/duplicating of load-exclusive operations

On 03/03/16 09:35, Kyrill Tkachov wrote: > Hi all, > > In this PR shrink-wrapping ends up duplicating the load-exclusive part of a > load-exclusive/store-exclusive loop > used to implement an atomic compare exchange operation. Look in bugzilla for > the kind of sequences generated. > The

Re: [PATCH] Fix PR69951

On 01/03/16 09:54, Richard Biener wrote: > On Tue, 1 Mar 2016, James Greenhalgh wrote: > >> On Tue, Mar 01, 2016 at 10:21:27AM +0100, Richard Biener wrote: >>> On Mon, 29 Feb 2016, James Greenhalgh wrote: >>> On Fri, Feb 26, 2016 at 09:32:53AM +0100, Richard Biener wrote: > > The

Re: [PATCH][ARM] Tests for arm_restrict_it patterns in thumb2.md

On Fri, Feb 5, 2016 at 10:00 AM, Kyrill Tkachov wrote: > Hi all, > > I've been auditing the patterns in the arm backend that were added/modified > for -mrestrict-it > and I've come up with a few runtime tests that end up generating those > patterns. > This patch

Re: [PATCH][ARM] PR target/69875 Fix atomic_loaddi expansion

On 19/02/16 15:24, Kyrill Tkachov wrote: > Hi all, > > The atomic_loaddi expander on arm has some issues and can benefit from a > rewrite to properly > perform double-word atomic loads on various architecture levels. > > Consider the code: > -- > #include > >

Re: [PATCH, PR69532]: Simple changes to effective target in two tests from *_ok -> *_hw

On Tue, Feb 16, 2016 at 11:47 AM, David Sherwood wrote: > Hi, > > I have a fix for bugzilla defect 69532, which is a simple change to > a couple of arm tests to check for effective target arm_v8_neon_hw > instead of arm_v8_neon_ok. > > Tested: > arm-none-eabi: No

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Mon, Feb 15, 2016 at 11:32 AM, Kyrill Tkachov <kyrylo.tkac...@foss.arm.com> wrote: > > On 04/02/16 08:58, Ramana Radhakrishnan wrote: >> >> On Tue, Jun 30, 2015 at 2:15 AM, Jim Wilson <jim.wil...@linaro.org> wrote: >>> >>> This is my sug

Re: [ARM] implement division using vrecpe/vrecps with -funsafe-math-optimizations

On Sun, Jan 17, 2016 at 9:06 AM, Prathamesh Kulkarni <prathamesh.kulka...@linaro.org> wrote: > On 31 July 2015 at 15:04, Ramana Radhakrishnan > <ramana.radhakrish...@foss.arm.com> wrote: >> >> >> On 29/07/15 11:09, Prathamesh Kulkarni wrote: >>> H

Re: [PATCH][ARM] Remove neon_reinterpret, use casts

On 04/02/16 11:04, Ramana Radhakrishnan wrote: > On Mon, Jan 18, 2016 at 12:14 PM, Alan Lawrence <alan.lawre...@arm.com> wrote: >> This cleans up the neon_reinterpret code on ARM in a similar way to AArch64. >> Rather than a builtin backing onto an expander that emits a mov

Re: [PATCH][ARM] Remove neon_reinterpret, use casts

On Mon, Jan 18, 2016 at 12:14 PM, Alan Lawrence wrote: > This cleans up the neon_reinterpret code on ARM in a similar way to AArch64. > Rather than a builtin backing onto an expander that emits a mov insn, we can > just use a cast, because GCC defines casts of vector types

Re: [PATCH][ARM] Enable fusion of AES instructions

On Tue, Dec 15, 2015 at 10:59 AM, Wilco Dijkstra wrote: > ping > >> -Original Message- >> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com] >> Sent: 19 November 2015 18:12 >> To: gcc-patches@gcc.gnu.org >> Subject: [PATCH][ARM] Enable fusion of AES instructions

Re: [PATCH][ARM][0/4] Fixing PR target/65932

On Fri, Jan 22, 2016 at 9:52 AM, Kyrill Tkachov wrote: > Hi all, > > PR target/65932 is a wrong-code bug affecting arm and has manifested itself > when compiling the Linux kernel, so it's something that we really > ought to fix. The problem stems from the fact that

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jun 30, 2015 at 2:15 AM, Jim Wilson wrote: > This is my suggested fix for PR 65932, which is a linux kernel > miscompile with gcc-5.1. > > The problem here is caused by a chain of events. The first is that > the relatively new eipa_sra pass creates fake parameters

Re: [PATCH][ARM][2/4] Fix operand costing logic for SMUL[TB][TB]

On Fri, Jan 22, 2016 at 9:52 AM, Kyrill Tkachov wrote: > Hi all, > > As part of investigating the codegen effects of a fix for PR 65932 I found > we assign > too high a cost for the sign-extending multiply instruction SMULBB. > This is because we add the cost of a

Re: [PATCH][ARM] Fix PR target/69403: Bug in thumb2_ior_scc_strict_it pattern

On Fri, Jan 22, 2016 at 9:32 AM, Kyrill Tkachov wrote: > Hi Han, > > On 21/01/16 22:57, Han Shen wrote: >> >> Hi Kyrill, the patched gcc generates correct asm for me for the test >> case. (I'll then build the whole system to see if other it-block >> related bugs are

Re: [PATCH][GCC][ARM] testcase memset-inline-10.c uses -mfloat-abi=hard but does not check whether target supports it

On Thu, Nov 12, 2015 at 3:16 PM, Andre Vieira wrote: > On 12/11/15 15:08, Andre Vieira wrote: >> >> Hi, >> >>This patch changes the memset-inline-10.c testcase to make sure that >> it is only compiled for ARM targets that support -mfloat-abi=hard using >> the

Re: [PATCH][ARM] PR target/69135: Mark ARMv8 vcvt instructions as unconditional

On Fri, Jan 15, 2016 at 3:05 PM, Kyrill Tkachov wrote: > Hi all, > > In this PR the ARMv8 vcvt instructions end up being conditionalised when > they don't have a conditional form. > setting the predicable attribute to "no" is not enough. We need to set the > "conds"

Re: [PATCH, ARM] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0

On Wed, Dec 16, 2015 at 9:11 AM, Thomas Preud'homme wrote: > During reorg pass, thumb1_reorg () is tasked with rewriting mov rd, rn to > subs rd, rn, 0 to avoid a comparison against 0 instruction before doing a > conditional branch based on it. The actual

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

>> >> I couldn't find 0/7 but in addition here you need to update the output >> for TAG_FP_SIMD_Arch to be 4. >> >> regards >> Ramana > > After discussing this offline, it turns out that the relevant attribute > (Tag_Advanced_SIMD_arch) is set by the assembler. Yep - sorry about the noise.

Re: [PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

On Tue, Dec 15, 2015 at 4:03 PM, Matthew Wahab <matthew.wa...@foss.arm.com> wrote: > On 10/12/15 10:45, Ramana Radhakrishnan wrote: >> >> On Tue, Dec 8, 2015 at 7:45 AM, Christian Bruel <christian.br...@st.com> >> wrote: >>> >>> Hi Matthew, &g

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

On Tue, Dec 15, 2015 at 4:07 PM, Matthew Wahab <matthew.wa...@foss.arm.com> wrote: > On 10/12/15 10:49, Ramana Radhakrishnan wrote: >> >> On Mon, Dec 7, 2015 at 4:10 PM, Matthew Wahab <matthew.wa...@foss.arm.com> >> wrote: >>> >>> On 27/11/15 17:1

Re: [PATCH 3/7][ARM] Add patterns for new instructions

On Mon, Dec 7, 2015 at 4:06 PM, Matthew Wahab wrote: > Ping. Updated patch attached. > Matthew > > > On 26/11/15 16:00, Matthew Wahab wrote: >> >> Hello, >> >> This patch adds patterns for the instructions, vqrdmlah and vqrdmlsh, >> introduced in the ARMv8.1

Re: [PATCH 2/7][ARM] Multilib support for ARMv8.1.

On Mon, Dec 7, 2015 at 4:05 PM, Matthew Wahab wrote: > Ping. Updated patch attached. > Matthew > > > On 26/11/15 15:58, Matthew Wahab wrote: >> >> This patch sets up multilib support for ARMv8.1, treating it as a >> synonym for ARMv8. Since ARMv8.1 integer, FP or SIMD

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

On Mon, Dec 7, 2015 at 4:04 PM, Matthew Wahab wrote: > Ping. Updated patch attached. > Matthew > > > On 26/11/15 15:55, Matthew Wahab wrote: >> >> Hello, >> >> >> ARMv8.1 includes an extension to ARM which adds two Adv.SIMD >> instructions, vqrdmlah and vqrdmlsh. This

Re: [PATCH 5/7][Testsuite] Support ARMv8.1 ARM tests.

On Mon, Dec 7, 2015 at 4:10 PM, Matthew Wahab wrote: > On 27/11/15 17:11, Matthew Wahab wrote: >> >> On 27/11/15 13:44, Christophe Lyon wrote: On 26/11/15 16:02, Matthew Wahab wrote: >> >> > This patch adds ARMv8.1 support to GCC Dejagnu, to allow ARM

Re: [PATCH 6/7][ARM] Add ACLE intrinsics vqrdmlah and vqrdmlsh

On Mon, Dec 7, 2015 at 4:12 PM, Matthew Wahab wrote: > Ping. Updated patch attached. > Matthew > > > On 26/11/15 16:04, Matthew Wahab wrote: >> >> Hello, >> >> This patch adds the ACLE intrinsics for the instructions introduced in >> ARMv8.1. It adds the vqrmdlah and

Re: [PATCH 4/7][ARM] Add ACLE feature macro for ARMv8.1 instructions.

On Tue, Dec 8, 2015 at 7:45 AM, Christian Bruel wrote: > Hi Matthew, > > > On 12/07/2015 05:07 PM, Matthew Wahab wrote: >> >> Ping. Updated patch attached. >> Matthew >> >> >> On 26/11/15 16:01, Matthew Wahab wrote: >>> >>> Hello, >>> >>> This patch adds the feature macro

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

On Thu, Dec 10, 2015 at 10:43 AM, Ramana Radhakrishnan <ramana@googlemail.com> wrote: > On Mon, Dec 7, 2015 at 4:04 PM, Matthew Wahab > <matthew.wa...@foss.arm.com> wrote: >> Ping. Updated patch attached. >> Matthew >> >> >> On 26

Re: [PATCH 7/7][ARM] Add ACLE intrinsics vqrdmlah_lane and vqrdmlsh_lane

On Thu, Nov 26, 2015 at 4:04 PM, Matthew Wahab wrote: > Hello, > > This patch adds the ACLE intrinsics for the instructions introduced in > ARMv8.1. It adds the vqrmdlah_lane and vqrdmlsh_lane forms of the > instrinsics to the arm_neon.h header, together with the ARM

Re: [PATCH, ARM] PR68674 Fix LTO support for neon builtins and error catching

On Tue, Dec 8, 2015 at 12:53 PM, Christian Bruel wrote: > Hi, > > The order of the NEON builtins construction has led to complications since > the attribute target support. This was not a problem when driven from the > command line, but was causing various issues when the

Re: [PATCH, ARM] PR68674 Fix LTO support for neon builtins and error catching

On Tue, Dec 8, 2015 at 1:29 PM, Christian Bruel <christian.br...@st.com> wrote: > Hello Ramana, > > On 12/08/2015 02:01 PM, Ramana Radhakrishnan wrote: >> >> On Tue, Dec 8, 2015 at 12:53 PM, Christian Bruel <christian.br...@st.com> >> wrote: >>>

Re: [PATCH, ARM] PR68674 Fix LTO support for neon builtins and error catching

On 08/12/15 13:53, Christian Bruel wrote: > >> >> The __builtin_neon* aren't published anywhere and people really >> shouldn't be using that directly in source code and only use the >> interface in arm_neon.h which implements pretty much all the Neon >> intrinsics in the ACLE document. >> > >

Re: [PATCH][ARM] PR target/68214: Delete IP-reg-clobbering call-through-mem patterns

On Fri, Dec 4, 2015 at 9:27 AM, Kyrill Tkachov wrote: > Hi all, > > The wrong-code in this PR occurs for pre-ARMv5 architectures with Thumb > interworking when trying > to use a static chain. Our output_call_mem function that outputs the > assembly for the call explicitly

Re: [PATCH][1/2] Fix PR68553

On 04/12/15 16:04, Richard Biener wrote: > On December 4, 2015 4:32:33 PM GMT+01:00, Alan Lawrence > wrote: >> On 27/11/15 08:30, Richard Biener wrote: >>> >>> This is part 1 of a fix for PR68533 which shows that some targets >>> cannot can_vec_perm_p on an identity

Re: Instruction scheduler rewriting instructions?

On Thu, Dec 3, 2015 at 7:01 PM, Steve Ellcey wrote: > Can the instruction scheduler actually rewrite instructions? I didn't > think so but when I compile some code on MIPS with: > > -O2 -fno-ivopts -fno-peephole2 -fno-schedule-insns2 > > I get: > > $L4: > lbu

[Patch AArch64] Fix typo in aarch64_builtin_reciprocal.

The patch to restructure builtin_reciprocals missed out an obvious ')'. Adjusted thusly and applied as obvious to trunk. regards Ramana 2015-12-01 Ramana Radhakrishnan <ramana.radhakrish...@arm.com> * config/aarch64/aarch64.c (aarch64_builtin_reciprocal): Fix typo.

Re: [Patch AArch64] Fix typo in aarch64_builtin_reciprocal.

On 01/12/15 09:04, Jakub Jelinek wrote: > On Tue, Dec 01, 2015 at 08:58:53AM +0000, Ramana Radhakrishnan wrote: >> The patch to restructure builtin_reciprocals missed out an obvious ')'. >> Adjusted thusly and applied as obvious to trunk. > > Sorry for that. Could y

Re: [PR67383][ARM][4.9]Backport of "Allow any register for DImode values in Thumb2"

On 27/11/15 09:40, Renlin Li wrote: > Hi Ramana, > > On 16/10/15 14:54, Renlin Li wrote: >> >> >>> The command line implies we remove r7 (frame pointer in Thumb2 - historical >>> accident, fno-omit-frame-pointer), r9 (ffixed-r9), r10 (-mpic-register) >>> which >>> leaves us with: >>> >>> *

Re: [PING] Re: [PATCH] c++/67913, 67917 - fix new expression with wrong number of elements

> Cookies on ARM are 8-bytes [1], but sizeof ((size_t) n) is only 4-bytes, > so this check will fail (We'll ask for 500 bytes, the test here will only > be looking for 496). > > Would it undermine the test for other architectures if I were to swap out > the != for a >= ? I think that is in line

Re: [PATCH][ARM] Do not expand movmisalign pattern if not in 32-bit mode

On 11/11/15 16:10, Kyrill Tkachov wrote: > Hi all, > > The attached testcase ICEs when compiled with -march=armv6k -mthumb -Os or > any march > for which -mthumb gives Thumb1: > error: unrecognizable insn: > } > ^ > (insn 13 12 14 5 (set (reg:SI 116 [ x ]) > (unspec:SI [ >

Re: [PATCH][ARM] PR 68149 Fix ICE in unaligned_loaddi split

On 10/11/15 17:32, Kyrill Tkachov wrote: > Hi all, > > This ICE in this PR occurs when we're trying to split unaligned_loaddi into > two SImode unaligned loads. > The problem is in the addressing mode. When reload was picking the > addressing mode we accepted an offset of > -256 because the

Re: Incorrect code due to indirect tail call of varargs function with hard float ABI

On 18/11/15 00:32, Kugan wrote: >> > Hi Ramana, >> > >> > Thanks for the review. I have opened a gcc bug-report for this. I tested >> > the attached patch for arm-none-linux-gnueabihf and >> > arm-none-linux-gnueabi with no new regressions. Is this OK? >> > >> > >> > Thanks, >> > Kugan >> >

Re: [PATCH][ARM] PR 68143 Properly update memory offsets when expanding setmem

On 06/11/15 10:46, Kyrill Tkachov wrote: > Hi all, > > In this wrong-code PR the vector setmem expansion and > arm_block_set_aligned_vect in particular > use the wrong offset when calling adjust_automodify_address. In the attached > testcase during the > initial zeroing out we get two V16QI

Re: [Patch ARM] Add support for Cortex-A35

On Mon, Nov 16, 2015 at 2:42 PM, James Greenhalgh wrote: > > Hi, > > This patch adds support to the ARM back-end for the Cortex-A35 > processor, as recently announced by ARM. The ARM Cortex-A35 provides > full support for the ARMv8-A architecture, including the CRC

Re: Incorrect code due to indirect tail call of varargs function with hard float ABI

Hi Kugan, It does look like an issue. Please open a bug report. > > > On 17/11/15 12:00, Charles Baylis wrote: >> On 16 November 2015 at 22:24, Kugan >> wrote: >> >>> Please note that we have a sibcall from "broken" to "indirect". >>> >>> "direct" is

Re: [PATCH] [ARM] neon-testgen.ml typo

> Hmm. I hadn't noticed that the crypto intrinsics tests where generated by > neon-testgen.ml, I thought they were hand-written. > The tests I added do not cover the crypto intrinsics, so I'm going > to revert r230274 and restore all the tests generated by neon-testgen.ml > until we have better

Re: [mask-vec_cond, patch 1/2] Support vectorization of VEC_COND_EXPR with no embedded comparison

On Thu, Oct 8, 2015 at 4:50 PM, Ilya Enkovich wrote: > Hi, > > This patch allows COND_EXPR with no embedded comparison to be vectorized. > It's applied on top of vectorized comparison support series. New optab > vcond_mask_optab > is introduced for such statements.

Re: [Patch ARM] Switch ARM to unified asm.

On Thu, Nov 12, 2015 at 9:21 AM, Christian Bruel <christian.br...@st.com> wrote: > Hi Ramana, > > On 11/10/2015 12:48 PM, Ramana Radhakrishnan wrote: >> >> [Resending as I managed to muck this up with my mail client] >> >> Hi, >> >> I held off

Re: [PATCH 04/N] Fix big memory leak in ix86_valid_target_attribute_p

On 12/11/15 15:52, Martin Liška wrote: > On 11/12/2015 12:29 PM, Richard Biener wrote: >> On Thu, Nov 12, 2015 at 11:03 AM, Martin Liška wrote: >>> Hello. >>> >>> Following patch was a bit negotiated with Jakub and can save a huge amount >>> of memory in cases >>> where target

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

On Wed, Nov 11, 2015 at 6:34 PM, Jim Wilson wrote: > This adds an option for the Qualcomm server parts, qdf24xx, just > optimizing like a cortex-a57 for now, same as how the initial Samsung > exynos-m1 support worked. > > This was tested with armv8 and aarch64 bootstraps

Re: [PATCH] PR67305, tighten neon_vector_mem_operand on eliminable registers

On 04/11/15 09:45, Jiong Wang wrote: > As discussed at the bugzilla > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67305 > > neon_vector_mem_operand is broken. As the comments says > "/* Reject eliminable registers. */", the code block at the head > of this function which checks

Re: [Patch AArch64] Switch constant pools to separate rodata sections.

On Tue, Nov 10, 2015 at 4:39 PM, Alan Lawrence <alan.lawre...@arm.com> wrote: > On 04/11/15 14:26, Ramana Radhakrishnan wrote: >> >> >> True and I've just been reading more of the backend - We could now start >> using blocks for constant pools as well. So let's

Re: [PATCH 3a/4][AArch64] Add attribute for compatibility with ARM pipeline models

On Tue, Nov 10, 2015 at 6:01 PM, Ramana Radhakrishnan <ramana@googlemail.com> wrote: > On Tue, Nov 10, 2015 at 5:50 PM, Evandro Menezes <e.mene...@samsung.com> > wrote: >>2015-11-10 Evandro Menezes <e.mene...@samsung.com> >> >>gcc/ >> &

Re: [PATCH 3a/4][AArch64] Add attribute for compatibility with ARM pipeline models

On Tue, Nov 10, 2015 at 5:50 PM, Evandro Menezes wrote: >2015-11-10 Evandro Menezes > >gcc/ > >* config/aarch64/aarch64.md (predicated): Copy attribute from >"arm.md". > > This patch duplicates an attribute from arm.md so

[Patch ARM] Switch ARM to unified asm.

Ramana gcc/ChangeLog: 2015-11-06 Ramana Radhakrishnan <ramana.radhakrish...@arm.com> * config/arm/arm-ldmstm.ml: Rewrite to generate unified asm templates. * config/arm/arm.c (arm_asm_trampoline_template): Make unified asm safe. (arm_output_multireg_pop): Li

Re: [PATCH][ARM][cleanup] Remove uses of CONST_DOUBLE_HIGH/LOW

On Thu, Nov 5, 2015 at 9:32 AM, Kyrill Tkachov wrote: > Hi all, > > This cleanup patch removes handling of CONST_DOUBLE rtxes that carry large > integers. > These should never be passed down from the midend and the arm backend > doesn't create them. > The code has been

Re: [PATCH][ARM] Fix costing of vmul+vcvt combine pattern

On Tue, Oct 27, 2015 at 1:55 PM, Kyrill Tkachov wrote: > Hi all, > > This patch allows us to handle the *combine_vcvtf2i pattern in rtx costs by > properly identifying it > as a toint coversion. Before this I saw a pattern like: > (set (reg/i:SI 0 r0) > (fix:SI (fix:SF

Re: [PATCH 4b/4] [ARM] PR63870 Remove error for invalid lane numbers

On 08/11/15 00:26, charles.bay...@linaro.org wrote: > From: Charles Baylis > > Charles Baylis > > * config/arm/neon.md (neon_vld1_lane): Remove error for invalid > lane number. > (neon_vst1_lane): Likewise. >

Re: [Patch AArch64] Switch constant pools to separate rodata sections.

On 08/11/15 11:42, Andreas Schwab wrote: > This is causing a bootstrap comparison failure in gcc/go/gogo.o. I'm looking into this - this is now PR68256. regards Ramana > > Andreas. >

Re: [Patch AArch64] Switch constant pools to separate rodata sections.

On 08/11/15 11:42, Andreas Schwab wrote: > This is causing a bootstrap comparison failure in gcc/go/gogo.o. > > Andreas. > I've had a look at this for sometime this afternoon and the trigger is the aarch64_use_constant_blocks_p change which appears to be causing a bootstrap comparison

Re: [PATCH 2/4] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier

On 08/11/15 00:26, charles.bay...@linaro.org wrote: > From: Charles Baylis > > gcc/ChangeLog: > > Charles Baylis > > PR target/63870 > * config/arm/arm-builtins.c: (arm_load1_qualifiers) Use >

Re: [PATCH 1/4] [ARM] PR63870 Add qualifiers for NEON builtins

On 08/11/15 00:26, charles.bay...@linaro.org wrote: > From: Charles Baylis > > gcc/ChangeLog: > > Charles Baylis > > PR target/63870 > * config/arm/arm-builtins.c (enum arm_type_qualifiers): New enumerator >

Re: regrename: don't overflow insn_rr_info

On 06/11/15 11:08, Bernd Schmidt wrote: > This one is a fix for something that could currently only affect c6x, but I > have code that exposes it on i386. > > When optionally gathering operand info in regrename, we can overflow the > array in certain situations. This can occur when we have a

Re: [PATCH][ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check

On 29/10/15 14:14, Kyrill Tkachov wrote: > > On 29/10/15 14:00, Marcus Shawcroft wrote: >> On 29 October 2015 at 13:50, Kyrill Tkachov wrote: >> > Ok for trunk? rtl.h exposes reg_or_subregno() already doesn't that do what we need here? >>> >>> reg_or_subregno

Re: regrename: don't overflow insn_rr_info

On 06/11/15 11:31, Bernd Schmidt wrote: > On 11/06/2015 12:17 PM, Ramana Radhakrishnan wrote: >> On 06/11/15 11:08, Bernd Schmidt wrote: >>> This one is a fix for something that could currently only affect c6x, but I >>> have code that exposes it on i386. >&g

Re: [PATCH][ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check

> Hi! > > I faced the same issue but I had somewhat different RTL for the consumer: > > (insn 20 15 21 2 (set (reg/i:SI 0 r0) > (minus:SI (subreg:SI (reg:DI 117) 4) > (mult:SI (reg:SI 123) > (reg:SI 114 gasman.c:4 48 {*mulsi3subsi}) > >

Re: How do we write unused arguments?

On Thu, Nov 5, 2015 at 9:32 AM, Bernd Schmidt wrote: > When reviewing patches I'm never quite sure which of the following we should > be using: > > some_target_hook (tree decl, machine_mode mode ATTRIBUTE_UNUSED) > > some_target_hook (tree decl, machine_mode ARG_UNUSED

Re: [ARM][PATCH, PR 68223] arm_[su]min_cmp pattern fails

dditional branches and that means the original pattern is probably more efficient. > > 2015-11-06 Michael Collison <michael.colli...@linaro.org > Ramana Radhakrishnan <ramana.radhakrish...@linaro.org> > > PR target/68223 Instead just say .. (watchin

Re: [Patch AArch64] Switch constant pools to separate rodata sections.

On 03/11/15 17:09, James Greenhalgh wrote: > On Tue, Nov 03, 2015 at 04:36:45PM +0000, Ramana Radhakrishnan wrote: >> Hi, >> >> Now that PR63304 is fixed and we have an option to address >> any part of the memory using adrp / add or adrp / ldr instructions >

Re: [PATCH] [ARM] neon-testgen.ml typo

On Fri, Oct 30, 2015 at 2:42 PM, Christophe Lyon <christophe.l...@linaro.org> wrote: > On 30 October 2015 at 15:33, Ramana Radhakrishnan > <ramana.radhakrish...@foss.arm.com> wrote: >> >> >> On 29/10/15 17:23, Jim Wilson wrote: >>> I noticed a comme

Re: [PATCH] [ARM] PR61551 RFC: Improve costs for NEON addressing modes

Hi Charles, Sorry I missed this completely in my inbox. On 31/10/15 03:34, Charles Baylis wrote: > Hi Ramana, > > [revisiting https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01593.html] > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61551 > > This patch is an initial attempt to rework the ARM

Re: [PATCH] Add support for ARM embedded multilibs

On 04/11/15 08:43, Jasmin J. wrote: > Hello Ramana! > >> Thank you for your patch - In this case before you make any more >> changes to this patch - comparing your patch and Terry's patch here >> https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00729.html shows no real >> differences > As I wrote

Re: [PATCH] Add support for ARM embedded multilibs

On Wed, Nov 4, 2015 at 12:29 AM, Jasmin J. wrote: > Thank you for your patch - In this case before you make any more changes to this patch - comparing your patch and Terry's patch here https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00729.html shows no real differences, I would

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