Hello,
The patch below fixes ICE reported in PR51794.
It avoids creating DDG edges for register uses of class DF_REF_ARTIFICIAL
as
the latter does not have real instructions for them and thus calling
BLOCK_FOR_INSN fails.
Tested and bootstrap on ppc64-redhat-linux, enabling SMS on loops with
Hello,
On Mon, Jan 2, 2012 at 3:30 PM, Richard Sandiford
rdsandif...@googlemail.com wrote:
Ayal Zaks ayal.z...@gmail.com writes:
+ for (i = 0; i ira_pressure_classes_num; i++)
+ {
+ enum reg_class pressure_class;
+
+ pressure_class = ira_pressure_classes[i];
+
+
Hello Richard,
This patch adjusts the dump output from
modulo-sched.c:get_schdedule_window.
Dump output is very much down to personal preference, so please feel free
just to reject the change.
The output format looks great to me although I cannot approve it.
Thanks,
Revital
Hi,
Thanks for the review!
Changelog:
(sms_schedule_by_order): Update call to get_sched_window.
all set_must_precede_follow.
^^^
call
Done.
+/* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and
MUST_PRECEDE
+ respectively only if cycle C falls
Hello Richard,
I ask because in the final range:
start = early_start;
end = MIN (end, early_start + ii);
/* Schedule the node close to it's predecessors. */
step = 1;
END is an exclusive bound. It seems like we might be double-counting
here,
and effectively
Hi Roman,
While building a data dependency graph for loop a ddg edge for some pair
of instructions with inter-loop dependency should be created only if
there is no edge for intra-loop dependency between these instructions.
Creating both of edges leads sometimes to the fact that function
It
Hello Roman,
This patch should be applied only after pending patches by Revital. This
patch
significantly enhances the existing implementation of the SMS. Patch
adds
support of scheduling loops without doloop pattern. The loop should meet
the
following requirements.
Thanks for the patch!
I
Hello,
(sorry for multiple copies of this email)
This small fix was inserted to skip DEBUG_INSNs while
recognizing doloop pattern in loop-doloop.c file. It's a fix
for the already approved do-loop patch (not in mainline yet,
http://gcc.gnu.org/ml/gcc-patches/2011-01/msg01718.html) in
Hello Alexandre
I think this will restore proper functioning to SMS in the presence of
debug insns. A while ago, we'd never generate deps of non-debug insns
on debug insns. I introduced them to enable sched to adjust (reset)
debug insns when non-debug insns were moved before them. I
Hello,
The attached patch includes enhancements for SMS to support targets
that their doloop part is not decoupled from the rest of the loop's
instructions, as SMS currently requires. (ARM is an example for such
target, where the loop's instructions might use CC which is used in the
doloop part)
Hello,
@@ -162,6 +175,7 @@ doloop_condition_get (rtx doloop_pat)
return 0;
if ((XEXP (condition, 0) == reg)
+ || (REGNO (XEXP (condition, 0)) == CC_REGNUM)
|| (GET_CODE (XEXP (condition, 0)) == PLUS
XEXP (XEXP (condition, 0), 0) == reg))
You can't
slowdown, which have appeared
because of do-loop conversion.
The questions are:
How to properly fix the ICE described?
Do you think this approach (after the fixes) can make its way into trunk?
Happy holidays!
--
Roman Zhuykov
[attachment sms-doloop-any-reg.diff deleted by Revital1 Eres/Haifa/IBM]Index
Hello Bingfeng,
Thanks for your reply! I would be very interested to try your patch.
Revital
From: Bingfeng Mei b...@broadcom.com
To: Revital1 Eres/Haifa/i...@ibmil, gcc@gcc.gnu.org
gcc@gcc.gnu.org
Date: 13/12/2010 12:20 PM
Subject:RE: A question about using
Hello,
I have the loop below and I want to pass to gcc that src1 and src2 never
alias with dst; so I used the restrict keyword as below; however I still
see that there are dependence edges between dst and src1 and src2 in
the DDG created by SMS and I wonder how can I resolve this.
(I used GCC
Hello,
When trying to compile the following loop with GCC -r164298 with modulo
scheduling pass enabled on PowerPC I get that the inter loop edges
between the memory instructions are created in the DDG although the
following check in ddg.c exists:
static void
add_inter_loop_mem_dep (ddg_ptr g,
Hello,
Doloop optimization fails to be applied on the following inner loop
when compiling for PowerPC (GCC -r162294) due to:
Doloop: number of iterations too costly to compute.
I do not understand why as the number of iterations is max_cols and I
appreciate an explanation.
Thanks,
Revital
Hello,
I'm compiling the following test with GCC 4.6.0 and I do not see that
MAX_EXPR is generated for (num)0)?0:(num).
With GCC 4.3.2 it is generated OK in original dump (both compilation were
made with -O3). Is there a flag I should use to generate MAX_EXPR
with GCC 4.6.0?
Thanks,
Revital
Hello,
Doloop optimization fails to be applied on the following kernel from
tescase sms-4.c with mainline (-r 162294) due to 'Possible infinite
iteration
case' message; taken from the loop2_doloop dump. (please see below).
With an older version of gcc (-r 146278) doloop succeeded to be applied
Hello,
In the new target I'm working on there are branch regs and gprs.
The loads and store instructions are only to/from the gprs, so if a
branch reg needs to be spilled it first needs to be moved to a gpr and
then stored to memory. I've implemented mov pattern in the machine
description file
Hello,
I have a question regarding code generation for a new target I'm working
on.
I am using GCC 4.6.
In reload pass the following first instruction is replaced with the
second one after spilling reg 182 to the stack. The problem is that
the generated new instruction does not have a valid
Hello,
I want to limit the size of immediate field of some operation.
I think you can look at SIGNED_INT_FITS_N_BITS definition at
config/crx/crx.c
for such example.
You can write a predicate like the following; and use it when describing
the immediate
operand in the md file.
(define_predicate
Hello,
I am using current mainline to compile a testcase which contains a loop.
The target I'm working on supports cmpsi pattern.
While expanding the loop condition I get that do_compare_rtx_and_jump ()
and
do_jump_by_parts_greater_rtx () call each other repeatedly.
The test I'm compiling
Hello,
Just did so... :-)
and it indeed solves this.
Thanks,
Revital
From: Paolo Bonzini bonz...@gnu.org
To: Revital1 Eres/Haifa/i...@ibmil
Cc: gcc@gcc.gnu.org
Date: 25/05/2010 03:57 PM
Subject:Re: Help with expanding compare
Sent by:Paolo Bonzini
Hello,
I have a question regarding the process of bundling and NOPs insertion for
VLIW architecture
and I appreciate your answer:
I am calling the second scheduler from the machine reorg pass; similar to
what is done for IA64.
I now want to handle the bundling and NOPs insertion for VLIW
Hello,
Is there a way to pass to the unroller the maximum number of iterations
of the loop such that it can decide to avoid unrolling if
the maximum number is small.
To be more specific, I am referring to the following case:
After the vectorizer decides to peel for alignment
it creates three
Hello,
I unroll the following code one times in a gimpile pass.
Can you please post the flags you used and the full test?
I can try to reproduce this.
Thanks,
Revital
Hello,
I get the following error while bootstrap on x86_64:
Thanks,
Revital
/home/revitale/test_mainline_45/build/./prev-gcc/xgcc
-B/home/revitale/test_mainline_45/build/./prev-gcc/
-B/home/revitale/test_mainline_45/build/x86_64-unknown-linux-gnu/bin/
Hello,
I get the following error while compiling gcc -r150679 on ppc
Thanks,
Revital
Hello,
The following snippet is from a f90 program which contains
a loop that does not get vectorized.
SUBROUTINE foo1(nx,ny,nz,arr2)
USE globalvar_mod, ONLY : dyinv, xstart, xstop
k=1
do j=1,ny
do i=1,nx
arr1(i,j,k) = arr2(i,j,k ) *dyinv
end do
end do
END SUBROUTINE foo1
The
Hello,
The testcase is from 459.GemsFDTD, right? dyinv is a regular
global variable. The issue is the global arrays arr1 and arr2 end
up pointing to anything even though the Fortran aliasing rules say
the do not.
Yes, the testcase is from 459.GemsFDTD.
We are working on this issue.
Hello,
I am trying to compile gcc 4.4.0 for the Cell processor for my google
summer of code project (GCC's OpenCL implementation starting point).
I have used OpenMP for some things and now I am trying to compile
everything on the Cell. OpenMP is supported in the ppu-gcc 4.1.0 so
I am
Hello Bingfeng,
I found a true register dependency is always accompanied with a
cross-iteration
anti dependency.
When -fmodulo-sched-allow-regmoves flag is set some anti-deps edges are not
created.
Please see add_cross_iteration_register_deps () function in ddg.c.
HTH,
Revital
This should
be painful.
Revital
-Original Message-
From: Revital1 Eres [mailto:e...@il.ibm.com]
Sent: 23 June 2009 14:40
To: Bingfeng Mei
Cc: Ayal Zaks; gcc@gcc.gnu.org
Subject: Re: Unnecessary regmoves in modulo scheduler?
Hello Bingfeng,
I found a true register dependency is always
Hello,
i386-pc-solaris:
cc1: warnings being treated as errors
/export/home/arth/gnu/gcc.git/gcc/tree-ssa-loop-prefetch.c: In function
'loop_prefetch_arrays':
/export/home/arth/gnu/gcc.git/gcc/tree-ssa-loop-prefetch.c:1589:7: error:
format '%ld' expects type 'long int', but argument 5 has
Hello,
I get the following error while bootstrap trunk -r148275 on ppc.
Thanks,
Revital
/home/eres/mainline_45/build/./prev-gcc/xgcc
-B/home/eres/mainline_45/build/./prev-gcc/
-B/usr/local/powerpc64-unknown-linux-gnu/bin/
-B/usr/local/powerpc64-unknown-linux-gnu/bin/
Hello,
I get the following ICE while building gcc on CELL spu; trunk -r146825.
(it passes OK on ppc)
Thanks,
Revital
gcc -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wcast-qual -Wold-style-definition
-Wc++-compat
Hello,
Not really an ICE!
Right, sorry about that.
Looks like the code is assuming that all backends use at
least one define_register_constraint. (Also, there's a missing '\n' that
probably makes your generated definition of REG_CLASS_FROM_CONSTRAINT
look a
bit odd!) How about
Hello,
Using testsuite/gcc.dg/sms-6.c as an example and compiling it for
PowerPC,
node 18 (see attachment) is in a SCC and cannot be scheduled until
spliting
twice. The MII = 20 and the schedule can only be found at II = 24.
Yes, I see. This example raises a couple of issues:
o The
Hello,
I have a basic-block and I want to get the last jump insn of it.
I use BB_END (bb) for that purpose.
The instruction I get is a NOTE_INSN_PROLOGUE_END which appears right
before the jump insn; and when doing NEXT_INSN for that note I get
the first insn of the next bb (code_label); which
Hello,
I want print additional information for each branch insn which will be
used by the linker (for the SPU software i-cache), for example:
brsl $lr,[EMAIL PROTECTED]
and I wonder what is the best way to implement it in GCC.
I defined a new note (in reg-notes.def) which can be attached to
Hello,
I am currently working on OpenRISC port of GCC-4.0.2, and I have to
insert a custom RTL (which gets translated to an instruction) at fixed
parts of the code. I have created the custom instruction (by modifying
RTL.DEF) and then put the appropritae constraints in my .md file.
[EMAIL PROTECTED] wrote on 17/10/2008 16:36:32:
Hello,
I tried to enable modulo scheduling for our target VLIW. It fails even
for the
simplest loop. I would like to have a look at how GCC produces schedule
for
other targets. I know that modulo scheduling relies on doloop_end pattern
to
Hello,
I want to emit the following SPU insn:
emit_insn (gen_iorti3 (r77, tmp, GEN_INT(0)));
r77 is defined as 'fixed register' which is a register that the register
allocator can not use. (triggers by SPU option -mfixed-range)
r77 is used to pass information to some other routine at run-time
Hello,
The problem is that r77 is not used in it's function after this
instruction
and thus DCE deletes it.
Don't focus on DCE. That's not the problem; the fact that there's no
visible dependence is the problem. Can you make the next instruction
have a use for r77 explicitly
Hello,
Is there a general way to recognize a nop insn in RTL (using attributes?),
or should I add a target hook for that?
For example, I would like to recognize the following spu insn as a nop:?),
(insn 555 210 203 11 (unspec_volatile [
(const_int 0 [0x0])
] 14) 393 {lnop}
Hello,
I am running the attached testcase (inspired from vect/vect-reduc-3.c
testcase) with -O3 -fwrapv on powerpc64-linux with trunk 4.4.
Here is a snippet from the testcase:
...
unsigned short ub[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
unsigned short uc[N] =
Hello Alexander,
We would like to ask people interested in SMS performance on PowerPC and
Cell SPU to conduct tests with this patch. Any feedback is greatly
appreciated.
The patch passed bootstrap with -fmodulo-sched
-fmodulo-sched-allow-regmoves flags on powerpc64-linux.
I am still testing
Hello,
I think you should add the pair of constraints m and I respectively to
the description of the instruction in your md file (and a relevant
case 8 to handle such instruction), i.e.:
(define_insn movqi
- [(set (match_operand:QI 0 nonimmediate_operand =p,q,m,m,p,q,p,q)
-
Hi Alexander,
We would like to ask people interested in SMS performance on PowerPC and
Cell SPU to conduct tests with this patch. Any feedback is greatly
appreciated.
I intend to perform testing with this patch (on ppc and SPU), after
resolving the miscompilation issues mentioned above.
Hello,
I think you should look at the constraint of the instruction in your md
file, for example (taken from altivec.md file under config/rs6000 dir):
(define_insn altivec_stvx
[(parallel
[(set (match_operand:V4SI 0 memory_operand =Z)
(match_operand:V4SI 1 register_operand v))
Hello,
SMS currently works only on single-basic-block loops. This simplifies
the task of software pipelining. PR34263 is an example where outof-ssa
creates a non-empty latch block for a single-basic-block loop and thus
prevents SMS to be applied on it. This issue was raised in the past
When scheduling insn 58, we calculate a window of possible cycles
according
to already scheduled predecessors and successors. This window looks like
a
parallelogram in general rather than a rectangle: in the first cycle
there
may be predecessors (already scheduled in the first cycle, or a
Hello,
While testing a patch related to SMS I encountered a problem which this
patch tries to fix. The problematic case involves write after read to
the same memory location (see attached file sms-4.c). In this case we
have one anti-dep edge with distance 0 from node r (containing the read
Hello,
I get the following ICE running bootstrap with -O2 on ppc,
--with-cpu=default32 r129655:
make[5]: Entering directory
`/home/revitale/mainline_750cl_test/new_build2/powerpc64-unknown-linux-gnu/nof/libjava'
/bin/sh ./libtool --tag=GCJ --mode=compile
Hello,
While testing a patch for the SMS I got an ICE which seems
to be related to the fact we build def-use chains only
and not use-def chains. (removed in the following patch -
http://gcc.gnu.org/ml/gcc-patches/2006-12/msg01682.html)
The problem arises when we delete an insn from the df that
The problem arises when we delete an insn from the df that contains a
use but do not update the def-use chain of it's def as we do not have
the use-def chain to reach it's def, This later causes a problem when
we try to dump the def-use chain of it's def.
I'm sorry but I don't understand
(call (mem:QI (symbol_ref:SI (\check_match.7758\) [flags 0x3]
function_decl
0x404a3e80 check_match) [0 S1 A8])
(const_int 0 [0x0]))
Q: does this instruction call the function check_match.7758 or
check_match ?
I think that when we do function specialization/cloning (for the IPA
Hello,
I get the following error while running make BOOT_CFLAGS='-O2' bootstrap
on ppc64 with --enable-checking on r128689:
libtool: compile: /home/revitale/check_dump_sms/new_build/./gcc/xgcc
-shared-libgcc -B/home/revitale/check_dump_sms/new_build/./gcc -nostdinc++
[EMAIL PROTECTED] wrote on 24/09/2007 09:19:09:
Hi All,
I wanted to install gcc-3.4 on my ppc-linux m/c. I tried cross
compiling, but cought up with error which i'm not familiar with as i'm
new here.
GCC list is about development of GCC so I think you should try the
gcc-help mailing list
Hello,
I want to create a rtx which will fit the description of the following
operand. (taken from selv2sf4 instruction in the rs6000/paired.md machine
description)
(match_operand:SF 4 zero_fp_constant F)
I am not sure how to create such zero const_double rtx and I appreciate
help regarding
Hello,
I get the following error while bootstrapping on ppc64 -r128289:
cc/../include -I../../gcc/gcc/../libcpp/include
-I../../gcc/gcc/../libdecnumber -I../../gcc/gcc/../libdecnumber/dpd
-I../libdecnumber\
-DTARGET_NAME=\powerpc64-unknown-linux-gnu\ \
-c
Hello,
I get the following error running trunk r127993 with
--enable-checking=assert on ppc64:
gcc -c -g -fkeep-inline-functions -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-Wmissing-format-attribute-DHAVE_CONFIG_H -I. -I.
Wow, you mean SPU has more builtins than x86_64? Up the bitfield
width of tree.h tree_function_decl.function_code until it no longer ICEs.
Changing the following indeed solves the problem:
Index: tree.h
===
--- tree.h
[EMAIL PROTECTED] wrote on 28/08/2007 17:31:08:
On 8/28/07, Dave Korn [EMAIL PROTECTED] wrote:
On 28 August 2007 15:10, Richard Guenther wrote:
Or maybe on ppc/spu enum bitfields are signed and the following
DECL_FUNCTION_CODE (decl) = -1;
gcc_assert (DECL_FUNCTION_CODE
Hello,
I get the following error on ppc64 with trunk r127835:
c/gcc/. -I../../gcc/gcc/../include -I../../gcc/gcc/../libcpp/include
-I../../gcc/gcc/../libdecnumber -I../../gcc/gcc/../libdecnumber/dpd
-I../libdecnumber../../gcc/gcc/regclass.c -o regclass.o
../../gcc/gcc/regclass.c: In
[EMAIL PROTECTED] wrote on 18/08/2007 03:19:48:
I noticed that gcc.dg/sms-antideps.c is failing on my IA64 Linux and
HP-UX platforms. The failure is:
x.c: In function 'foo':
x.c:25: internal compiler error: in gen_sub2_insn, at optabs.c:4640
Please submit a full bug report,
with
Hello,
The summary of the BOF regarding floating point arithmetic in GCC from
the summit can be found in the following wiki page:
http://gcc.gnu.org/wiki/FP_BOF
Thanks,
Revital
Hello,
I wanted to update the status of the first patch that
Vladimir had posted to improve modulo-schedualing.
(http://gcc.gnu.org/ml/gcc-patches/2007-01/msg01468.html).
I tested this patch on ppc64 and currently there is one difference in
one of the fortran's testcases (forall_10.f90); this
Hello,
The following ICE is received on r126521 while bootstraping on ppc64.
Revital
/home/eres/test_again/build/./gcc/xgcc -B/home/eres/test_again/build/./gcc/
-B/home/eres/test_again/build/powerpc64-unknown-linux-gnu/bin/
-B/home/eres/test_again/build/powerpc64-unknown-linux-gnu/lib/
The newly built gfortran must be stomping on memory. I've found that
attached patch allows gfortran to still function. Could someone who
sees this problem try bootstrapping gfortran with the patch?
I will try it.
Revital
The newly built gfortran must be stomping on memory. I've found that
attached patch allows gfortran to still function. Could someone who
sees this problem try bootstrapping gfortran with the patch?
gfortran bootstrapped OK with this patch on ppc64 r126353.
Thanks,
Revital
checking whether the GNU Fortran compiler is working... no
configure: error: GNU Fortran is not working; please report a bug in
http://gcc.gnu.org/bugzilla, attaching
/Develop/mainline-dn/build3/powerpc64-unknown-linux-gnu/libgfortran/config.log
make[1]: *** [configure-target-libgfortran]
[EMAIL PROTECTED] wrote on 24/06/2007 01:17:34:
I tested it on powerpc64-linux with the default option
--with-cpu=default32.
Ah, so this is a 32-bit compiler like on sparc64-linux?
--with-cpu=default32 means that the compiler itself and it's produced
code are 32 bits by default.
Revital
Eric Botcazou [EMAIL PROTECTED] wrote on 23/06/2007 21:50:57:
I'm going to try the 64-bit variant.
SPARC/Solaris 64-bit is OK, as well as IA-64/Linux according to:
http://gcc.gnu.org/ml/gcc-testresults/2007-06/msg01044.html
Do you test PowerPC 32-bit or should I try a build on Darwin
[EMAIL PROTECTED] wrote on 21/06/2007 15:44:27:
Hello. i am Alberto
I work with Gcc trees to modify c++ original code and dont find and i
need documentation about trees because the web isnt enought information.
Where are docs about gcc trees and macros to access it?
In GCC wiki you may
Hello,
I get the following bootstrap comparison failure on powerpc64
for Ada (--enable-languages=ada) with BOOT_CFLAGS='-O2'.
Revital
make[2]: Entering directory `/home/revital/mainline_ccp/build'
make[3]: Entering directory `/home/revital/mainline_ccp/build'
rm -f stage_current
make[3]:
Which revision? The Ada compiler bootstraps fine on i586 and x86-64 at
revision 125912:125915M (i.e with structural alias analysis enabled).
revision 125915.
Thanks,
Revital
Which revision? The Ada compiler bootstraps fine on i586 and x86-64 at
revision 125912:125915M (i.e with structural alias analysis enabled).
Note that if cc1-checksum.o differs, it likely means the issue is
unrelated to
Ada.
I am now bootstrapping only c. If that will pass OK I can
Eric Botcazou [EMAIL PROTECTED] wrote on 21/06/2007 21:10:15:
I am now bootstrapping only c. If that will pass OK I can check Ada on
an older revision if you wish.
I'm not sure that would really help in this case. The fact that x86 and
x86-64 are both clean with structural alias
Hello,
While testing a patch on current trunk (r 125640) I've noticed that g++'s
cp_compat_x_tst.o-cp_compat_y_tst testcase fails with unexpected failure
on x86_64 with the vanilla version but passes OK with the patched version
(-O2). On ppc64 and i486 the test passes both with the vanilla and
Hello,
I have one more question regarding the comment in
tree-ssa-ccp.c file -
/* Note that for propagation purposes, we are only interested in
visiting statements that load the exact same memory reference
stored here. Those statements will have the exact same list
Hello,
I have two ssa vars (i0 and i1 in the following example); what is the
sequence to generate a new phi node corresponding to i3 -
if (...)
i0 = exp1
else
i1 = exp2
i3 = PHI(i0 , i1);
Thanks,
Revital
The engine only knew how to propagate cases that always make the same
set of vdef/vuses, so it was safe to only tell it to use the first
vdef.
/* Note that for propagation purposes, we are only interested in
visiting statements that load the exact same memory reference
Hello,
I appreciate your help in figuring what is considered a valid sequence
of operations for creating a new variable in the tree level.
Is the following sequence OK -
tmp_var = create_tmp_var (type, _new_);
add_referenced_tmp_var (tmp_var);
mark_sym_for_renaming (tmp_var);
Or should I
Hello,
I am trying to understand the usage of some functions in tree-affine.c
file and I appreciate your help.
For example; for the two memory accesses
arr[b+8].X and arr[b+9].X, how does their affine combinations
will look like after executing the following sequence of operation?
(taken
Hello,
The following error is received on ppc64.
Thanks,
Revital
symtab.o -MT symtab.o -MMD -MP -MF .deps/symtab.Po
../../gcc/libcpp/symtab.c
/home/eres/mainline_lim/build/./prev-gcc/xgcc
-B/home/eres/mainline_lim/build/./prev-gcc/
I can modify it to catch it pretty easily, just walk back a few vuses
if the current set of vuses is defined by something that does not
actually touch our offset.
This sounds like what I am trying to do in ccp...
I am not sure I understand. The new patch uses the infrastructure of
the
Could someone tell me how to do vector compare in generic way?
AFAICT every target which supports vector operations has it's own
list of built-in function for vector comparison. For example, Altivec
has vec_cmpgt and other built-ins for vector compare instructions.
(see altivec.h file for the
I will greatly appreciate any suggestions regarding the following
problem I have with the ccp propagator. I am testing the new store
ccp patch which propagates constants by walking the virtual use-def
chain (http://gcc.gnu.org/ml/gcc-patches/2007-05/msg00055.html) and I
encountered the
Hello,
I will greatly appreciate any suggestions regarding the following
problem I have with the ccp propagator. I am testing the new store
ccp patch which propagates constants by walking the virtual use-def
chain (http://gcc.gnu.org/ml/gcc-patches/2007-05/msg00055.html) and I
encountered the
[EMAIL PROTECTED] wrote on 28/05/2007 09:05:24:
Can you help to upgrade the gcc to 4.1.1 by providing the steps and
procedure etc
I think you should try the gcc-help mailing list.
Revital
[EMAIL PROTECTED] wrote on 11/05/2007 15:26:16:
Hello all,
I am working on gcc v4.1.1 for a non-gcc target. I want to support
'MAC' instruction
(mac OP1, OP2, OP3 = OP3 += OP1 * OP2).
http://gcc.gnu.org/ml/gcc/2007-05/msg00114.html seems relevant to your
problem.
Revital
Regards,
Hello,
I get the following error while bootstraping mainline with -O2
-funroll-loops -funsafe-math-optimizations options on PPC.
Thanks,
Revital
make[3]: Leaving directory `/home/revitale/mainline_zero_mve/build'
Comparing stages 2 and 3
warning: ./cc1plus-checksum.o differs
warning:
I've been using binutils 2.17 on various distributions of powerpc64-linux
and have had no problem with it.
I used binutils 2.15. I guess this is the problem.
Thanks,
Revital
Janis
Hello,
I get the following error on PPC while bootstrapping mainline.
Re-runing make I get:
collect2: ld terminated with signal 11 [Segmentation fault]
make[8]: *** [libstdc++.la] Error 1
Thanks,
Revital
ranlib .libs/libgfortran.a
creating libgfortran.la
(cd .libs rm -f libgfortran.la ln
I'll find a way to fix that.
Revital, please try this. I've tested it but know better than to check
things in at the end of the day; I'll post it tomorrow.
It fixes the problem.
Thanks,
Revital
Hello,
I get the following error while running
make check-gcc RUNTESTFLAGS=compat.exp
with mainline gcc version 4.3.0 20070312
on PPC.
Revital
=== g++ tests ===
Schedule of variations:
unix
Running target unix
Using /usr/local/share/dejagnu/baseboards/unix.exp as board description
file
[EMAIL PROTECTED] wrote on 12/03/2007 16:56:53:
Hi all,
i have a very little question for you. I have a basic block and by a
statement iterator i can obtain a tree structure in the following
manner:
tree stmt = bsi_stmt (si);
I want to use this tree structure to manipulate the
Hello,
I wonder why this order (non-consecutive, decreasing) of Altivec registers
was chosen when specifying the allocation order in REG_ALLOC_ORDER.
(taken from rs6000.h)
/* AltiVec registers. */\
77, 78,
Hello,
I appreciate it if someone could tell me how I can create a -0 RTX
expression (like CONST0_RTX)?
Thanks,
Revital
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