On 05/27/2015 07:20 AM, Ilya Enkovich wrote:
I looked into assign_stack_local_1 call for this spill. LRA correctly
requests 16 bytes size with 16 bytes alignment. But
assign_stack_local_1 look reduces alignment to 8 because estimated
stack alignment before RA is 8 and requested mode's (DI)
2015-05-27 6:31 GMT+03:00 Jeff Law l...@redhat.com:
On 05/25/2015 09:27 AM, Ilya Enkovich wrote:
2015-05-22 15:01 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-05-22 11:53 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-05-21 22:08 GMT+03:00 Vladimir Makarov vmaka...@redhat.com:
On 05/25/2015 09:27 AM, Ilya Enkovich wrote:
2015-05-22 15:01 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-05-22 11:53 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-05-21 22:08 GMT+03:00 Vladimir Makarov vmaka...@redhat.com:
So, Ilya, to solve the problem you need to avoid
2015-05-22 15:01 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-05-22 11:53 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-05-21 22:08 GMT+03:00 Vladimir Makarov vmaka...@redhat.com:
So, Ilya, to solve the problem you need to avoid sharing subregs for the
correct LRA/reload work.
2015-05-21 22:08 GMT+03:00 Vladimir Makarov vmaka...@redhat.com:
On 05/21/2015 05:54 AM, Ilya Enkovich wrote:
Thanks. For me it looks like an inheritance bug. It is really hard
to fix the bug w/o the source code. Could you send me your patch in
order I can debug RA with it to investigate
2015-05-22 11:53 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-05-21 22:08 GMT+03:00 Vladimir Makarov vmaka...@redhat.com:
So, Ilya, to solve the problem you need to avoid sharing subregs for the
correct LRA/reload work.
Thanks a lot for your help! I'll fix it.
Ilya
I've fixed
On 05/21/2015 01:08 PM, Vladimir Makarov wrote:
On 05/21/2015 05:54 AM, Ilya Enkovich wrote:
Thanks. For me it looks like an inheritance bug. It is really hard
to fix the bug w/o the source code. Could you send me your patch in
order I can debug RA with it to investigate more.
Sure! Here
On Thu, May 21, 2015 at 02:23:47PM -0600, Jeff Law wrote:
On 05/21/2015 01:08 PM, Vladimir Makarov wrote:
On 05/21/2015 05:54 AM, Ilya Enkovich wrote:
Thanks. For me it looks like an inheritance bug. It is really hard
to fix the bug w/o the source code. Could you send me your patch in
On 20 May 23:27, Vladimir Makarov wrote:
On 20/05/15 04:17 AM, Ilya Enkovich wrote:
On 19 May 11:22, Vladimir Makarov wrote:
On 05/18/2015 08:13 AM, Ilya Enkovich wrote:
2015-05-06 17:18 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
Hi Vladimir,
Could you please comment on this?
On 05/21/2015 05:54 AM, Ilya Enkovich wrote:
Thanks. For me it looks like an inheritance bug. It is really hard
to fix the bug w/o the source code. Could you send me your patch in
order I can debug RA with it to investigate more.
Sure! Here is a patch and a testcase. I applied patch to
On 19 May 11:22, Vladimir Makarov wrote:
On 05/18/2015 08:13 AM, Ilya Enkovich wrote:
2015-05-06 17:18 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
Hi Vladimir,
Could you please comment on this?
Ilya, I think that the idea is worth to try but results might be
mixed. It is hard to
On 20/05/15 04:17 AM, Ilya Enkovich wrote:
On 19 May 11:22, Vladimir Makarov wrote:
On 05/18/2015 08:13 AM, Ilya Enkovich wrote:
2015-05-06 17:18 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
Hi Vladimir,
Could you please comment on this?
Ilya, I think that the idea is worth to try but
On 05/18/2015 08:13 AM, Ilya Enkovich wrote:
2015-05-06 17:18 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-04-25 4:32 GMT+03:00 Jan Hubicka hubi...@ucw.cz:
Hi,
I am adding Vladimir and Richard into CC. I tried to solve similar problem
with FP math years ago by having -mfpmath=sse,i387.
2015-05-06 17:18 GMT+03:00 Ilya Enkovich enkovich@gmail.com:
2015-04-25 4:32 GMT+03:00 Jan Hubicka hubi...@ucw.cz:
Hi,
I am adding Vladimir and Richard into CC. I tried to solve similar problem
with FP math years ago by having -mfpmath=sse,i387. The idea was to allow
use of i387 registers
On 05/07/2015 10:59 AM, Uros Bizjak wrote:
If we consider SSE operations as DImode operations, we will loose the
ability to precisely specify which operation (SSE vs. general reg) we
want. I'm afraid that in DImode case, combine will choose FLAG-less
pattern that will mandate moves from
On 05/07/2015 09:24 AM, Richard Henderson wrote:
I was wondering this morning about the possibility of a kind of constraint
that
would allow RA to generate pairs of registers via CONCAT. That is, the two
hard registers within the CONCAT are collectively the double-word allocation,
but need
On Thu, May 7, 2015 at 6:24 PM, Richard Henderson r...@redhat.com wrote:
On 04/24/2015 06:32 PM, Jan Hubicka wrote:
Also I believe it was kind of Richard's design deicsion to avoid use of
(paradoxical) subregs for vector conversions because these have funny
implications.
Yes indeed.
The
On 04/24/2015 06:32 PM, Jan Hubicka wrote:
Also I believe it was kind of Richard's design deicsion to avoid use of
(paradoxical) subregs for vector conversions because these have funny
implications.
Yes indeed.
The code for handling upper parts of paradoxical subregs is controlled by
macros
2015-04-25 4:32 GMT+03:00 Jan Hubicka hubi...@ucw.cz:
Hi,
I am adding Vladimir and Richard into CC. I tried to solve similar problem
with FP math years ago by having -mfpmath=sse,i387. The idea was to allow
use of i387 registers when SSE ones run out and possibly also model the fact
that
On Fri, Apr 24, 2015 at 11:45 AM, Uros Bizjak ubiz...@gmail.com wrote:
On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich enkovich@gmail.com
wrote:
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer instructions
On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich enkovich@gmail.com wrote:
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer instructions in
SSE I have to use vector variants.
Is this approach really better
On Fri, Apr 24, 2015 at 12:14 PM, Uros Bizjak ubiz...@gmail.com wrote:
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer instructions in
SSE I have to use vector variants.
Is this approach really better that
2015-04-24 12:49 GMT+03:00 Uros Bizjak ubiz...@gmail.com:
On Fri, Apr 24, 2015 at 11:45 AM, Uros Bizjak ubiz...@gmail.com wrote:
On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich enkovich@gmail.com
wrote:
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit
On Fri, Apr 24, 2015 at 12:09 PM, Ilya Enkovich enkovich@gmail.com wrote:
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer instructions in
SSE I have to use vector variants.
Is this approach really better
On Fri, 24 Apr 2015, Uros Bizjak wrote:
Please try to generate paradoxical subreg (V2DImode subreg of V1DImode
pseudo). IIRC, there is some functionality in the compiler that is
able to tell if the highpart of the paradoxical register is zeroed.
Those are not currently legal (I tried to
2015-04-24 12:45 GMT+03:00 Uros Bizjak ubiz...@gmail.com:
On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich enkovich@gmail.com
wrote:
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer instructions in
SSE I
2015-04-24 13:27 GMT+03:00 Marc Glisse marc.gli...@inria.fr:
On Fri, 24 Apr 2015, Uros Bizjak wrote:
Please try to generate paradoxical subreg (V2DImode subreg of V1DImode
pseudo). IIRC, there is some functionality in the compiler that is
able to tell if the highpart of the paradoxical
Hi,
I am adding Vladimir and Richard into CC. I tried to solve similar problem
with FP math years ago by having -mfpmath=sse,i387. The idea was to allow
use of i387 registers when SSE ones run out and possibly also model the fact
that Pentium4 had faster i387 additions than SSE additions. I also
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