Re: [PATCH] Deprecate ia64*-*-*

On Thu, 2019-06-13 at 09:09 -0600, Jeff Law wrote: > On 6/13/19 5:13 AM, Richard Biener wrote: > > > > ia64 has no maintainer anymore so the following deprecates it > > with the goal of eliminating the port for GCC 11 if no maintainer > > steps up. OK with me since I'm not the maintainer

Re: [PATCH] Deprecate ia64*-*-*

On Thu, Jun 13, 2019 at 10:39 AM Joel Sherrill wrote: > Ok with me if no one steps up and the downstream projects like Debian gets > notice. This is just a reflection of this architecture's status in the > world. I sent email to the debian-ia64 list half an hour ago. Just got a response. They

Re: Please help!!!

On Mon, May 6, 2019 at 6:02 AM Алексей Хилаев via gcc wrote: > Gcc riscv won`t emit my insns, binutils and spike(riscv sim) work correctly, > but gcc don`t. I want to add min/max for integer, gcc compiling correct, sim > executing correctly. > (define_insn "*min_" > [(set (match_operand:GPR 0

Re: Dejagnu output size limit and flaky test ( c-c++-common/builtins.c -Wc++-compat )

On 5/8/19 3:34 AM, Matthew Malcomson wrote: The cause seems to be a restriction in dejagnu where it stops reading after a given read if its output buffer is greater than 512000 bytes. This dejagnu restriction was removed in 2016. Try using a newer dejagnu release. 2016-03-27 Ben Elliston

Re: gcc vs clang for non-power-2 atomic structures

I was pointed at https://bugs.llvm.org/show_bug.cgi?id=26462 for the LLVM discussion of this problem. Another issue here is that we should have ABI testing for atomic. For instance, gcc/testsuite/gcc.dg/compat has no atomic testcases. Likewise g++.dg/compat. Jim

gcc vs clang for non-power-2 atomic structures

We got a change request for the RISC-V psABI to define the atomic structure size and alignment. And looking at this, it turned out that gcc and clang are implementing this differently. Consider this testcase rohan:2274$ cat tmp.c #include struct s { int a; int b; int c;}; int main(void) {

Re: gcc/config/arch/arch.opt: Option mask gen problem

On Mon, Jul 22, 2019 at 4:05 AM Maxim Blinov wrote: > Is it possible, in the arch.opt file, to have GCC generate a bitmask > relative to a user-defined variable without an associated name? To > illustrate my problem, consider the following option file snippet: > ... > But, I don't want the user

Re: Update on SVE/sizeless types for C and C++

On Tue, Nov 12, 2019 at 2:12 PM Richard Sandiford wrote: > Are both RVV intrinsic proposals like SVE in that all sizeless types > can be/are built into the compiler? If so, do you think the target hook > added in: > https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00942.html > would be enough

Re: Update on SVE/sizeless types for C and C++

On Tue, Nov 12, 2019 at 8:06 AM Richard Sandiford wrote: > If the use of sizeless types does expand beyond SVE built-in types > in future, the places that call the hook are the places that would > need to deal directly with sizeless types. We are using the same sizeless type infrastructure for

Re: Modifying RTL cost model to know about long-latency loads

On Thu, Apr 16, 2020 at 7:28 PM Sasha Krassovsky wrote: > @Jim I saw you were from SiFive - I noticed that modifying the costs for > integer multiplies in the riscv_tune_info structs didn’t affect the generated > code. Could this be why? rtx_costs is used for instruction selection. For

Re: Modifying RTL cost model to know about long-latency loads

On Sat, Apr 11, 2020 at 4:28 PM Sasha Krassovsky via Gcc wrote: > I’m currently modifying the RISC-V backend for a manycore processor where > each core is connected over a network. Each core has a local scratchpad > memory, but can also read and write other cores’ scratchpads. I’d like to add

Re: `insn does not satisfy its constraints` when compiling a simple program.

On Sat, Apr 18, 2020 at 8:45 AM Joe via Gcc wrote: > test.c: In function ‘main’: > test.c:5:1: error: insn does not satisfy its constraints: The constrain_operands function is failing to match the insn to its constraints. Try putting a breakpoint there, and stepping through the code to see what

Re: Not usable email content encoding

I'm one of the old timers that likes our current work flow, but even I think that we are risking our future by staying with antiquated tools. One of the first things I need to teach new people is now to use email "properly". It is a barrier to entry for new contributors, since our requirements

Re: Is there a way to tell GCC not to reorder a specific instruction?

On Tue, Sep 29, 2020 at 3:47 AM 夏 晋 via Gcc wrote: > I tried to set the "vlen" after the add & multi, as shown in the following > code: > vf32 x3,x4; > void foo1(float16_t* input, float16_t* output, int vlen){ > vf32 add = x3 + x4; > vf32 mul = x3 * x4; > __builtin_riscv_vlen(vlen);

Re: New pseudos in splitters

On Wed, Sep 23, 2020 at 7:51 AM Ilya Leoshkevich via Gcc wrote: > Is this restriction still valid today? Is there a reason we can't > introduce new pseudos in a splitter before LRA? See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91683 for an example of what can go wrong when a splitter

Re: Is there a way to tell GCC not to reorder a specific instruction?

On Tue, Sep 29, 2020 at 7:22 PM 夏 晋 wrote: > vint16m1_t foo3(vint16m1_t a, vint16m1_t b){ > vint16m1_t add = a+b; > vint16m1_t mul = a*b; > vsetvl_e8m1(32); > return add + mul; > } Taking another look at your example, you have type confusion. Using vsetvl to specify an element width of

Re: Is there a way to tell GCC not to reorder a specific instruction?

On Tue, Sep 29, 2020 at 11:40 PM Richard Biener wrote: > But this also doesn't work on GIMPLE. On GIMPLE riscv_vlen would > be a barrier for code motion if you make it __attribute__((returns_twice)) > since then abnormal edges distort the CFG in a way preventing such motion. At the gimple

Re: Is there a way to tell GCC not to reorder a specific instruction?

On Wed, Sep 30, 2020 at 11:35 PM Richard Biener wrote: > On Wed, Sep 30, 2020 at 10:01 PM Jim Wilson wrote: > > We have a lot of examples in gcc/testsuite/gcc.target/riscv/rvv that > > we are using for testing the vector support. > > That doesn't seem to exist (but maybe i

Re: How to forbid register allocator to overlap bewteen DEST and SOURCE

On Wed, Jul 1, 2020 at 8:40 PM wrote: > GCC seems to overlap register bewteen DEST and SOURCE in different > machine mode, > Is there any target hooks to control this feature ? > I use ‘&’ to forbid register allocator to > overlap bewteen DEST and SOURCE, > but

Re: sign_and_send_pubkey: signing failed: agent refused operation

On Mon, Jun 1, 2020 at 3:33 PM Martin Sebor via Gcc wrote: > So it sounds like you wouldn't expect the "agent refused operation" > error either, and it's not just a poor error message that I should > learn to live with. That makes me think I should try to figure out > what's wrong. I think the

RISC-V -menable-experimental-extensions option

I'm not aware of any other target that has a similar feature, so I thought a bit of discussion first might be useful. For most ISAs, there is one organization that owns it, and does development internally, in private. For RISC-V, the ISA is owned by RISC-V International which has no developers.

Re: Wrong insn scheduled by Sched1 pass

On Mon, Nov 2, 2020 at 11:45 PM Jojo R wrote: > From origin insn seqs, I think the insn 'r500=unspec[r100] 300’ is in > Good place because of the bypass of my pipeline description, it is not > needed to schedule. > ... > Is there any way to control my case ? > Or my description of pipeline is

Re: __fp16 is ambiguous error in C++

On Thu, Jun 24, 2021 at 7:26 PM ALO via Gcc wrote: > foo.c: In function '__fp16 foo(__fp16, __fp16)': > foo.c:6:23: error: call of overloaded 'exp(__fp16&)' is ambiguous > 6 | return a + std::exp(b); > | ^ > No, there isn't a solution for this. You might want to try an ARM port clang/gcc to

Re: Having trouble getting my school to sign the copyright disclaimer

On Wed, Mar 31, 2021 at 8:27 AM PKU via Gcc wrote: > I’m trying to get my school to sign the copyright disclaimer. > Unfortunately the officials are reluctant to do that. Can anyone suggest > what to do next? > Maybe the PLCT Lab at the Chinese Academy of Sciences can help. They are doing GCC

Re: Default debug format for AVR

On Sat, Apr 3, 2021 at 6:24 PM Simon Marchi via Gcc wrote: > The default debug format (when using only -g) for the AVR target is > stabs. Is there a reason for it not being DWARF, and would it be > possible to maybe consider possibly thinking about making it default to > DWARF? I am asking

Re: HELP: MIPS PC Relative Addressing

On Wed, Feb 24, 2021 at 9:30 AM Maciej W. Rozycki wrote: > On Wed, 24 Feb 2021, Jiaxun Yang wrote: > > > For RISC-V, %pcrel_lo shall point to the label of corresponding > %pcrel_hi, > > like > > > > .LA0: > > auipca0, %pcrel_hi(sym) > > addi a0, a0, %pcrel_lo(.LA0) > > I

Re: HELP: MIPS PC Relative Addressing

On Wed, Feb 24, 2021 at 6:18 AM Jiaxun Yang wrote: > I found it's very difficult for GCC to generate this kind of pcrel_lo > expression, > RTX label_ref can't be lower into such LOW_SUM expression. > Yes, it is difficult. You need to generate a label, and put the label number in an unspec in

Re: Is this a compiler bug?

precision problem. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: bug report

bash, see the documentation for the ulimit command. If csh, I think it is limits. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: Inconsistent floating point result when using G++ 3.3.6 with option -O0 or -O1 separately

. For x86, there are some options that might help, such as -mfpmath=sse. This will only work with recent gcc versions and recent x86 processors, and may take some experimentation. Sometimes -ffloat-store helps. There is a lot of info about this problem in PR 323. -- Jim Wilson, GNU Tools Support

Re: Bug in strtof

they are meant for users to define. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: GCC Compiling Problem

. An alternative solution is to avoid building fastjar which may work if this is the only place that is failing. fastjar is only used by java, so you could try configuring without java support if you don't need it, e.g. something like --enable-languages=c,c++ if you only need C and C++ support. -- Jim

Re: long function name

space limit, then you might need root access to increase it past this limit. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: asm outport

about MS Windows programming. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: Typo in gcc/config/kfreebsdgnu.h

had the intended effect. -- Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com 2003-12-17 Santiago Vila [EMAIL PROTECTED] * config/kfreebsdgnu.h (TARGET_OS_CPP_BUILTINS): Rename from TARET_OS_CPP_BUILTINS. Index: kfreebsdgnu.h

Re: IS IT A BUG ????

anything with this bug report. We need to know the gcc version, the target (OS and CPU), the optimization options used, and possibly also other info. Also, bugs should be submitted into bugzilla rather than mailed to the list. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: PATCH: DWARF2 macinfo-related fixes for gdb and gcc

you won't. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: Compiler bug report

. Gcc version info. A testcase that can reproduce the bug. Etc. See http://gcc.gnu.org/bugs.html for info on how to report bugs. Also, bugs should be reported into our bugzilla bug database instead of emailed to this list. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: GCC bug report - Xubuntu kernel compile fails w/gcc bug report request

to a page where you can attach the file to the newly created bug report. This is a bit awkward, yes, but I believe all bugzilla installations work this way. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: internal compiler error: is this a known problem?

that crosstools already has the patch, so maybe you can get it from there also. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: Bugzilla administrator

an administrator, send mail to overseers. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: gcc bug WRT warning that should not be displayed

smaller than LONG_MIN. Adding casts to long long does not change this fact. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: Bitfield conversion bug in 4.2?

in the tcode == BOOLEAN_TYPE code where we fail to match the conditions due to this inconsistency. I'd suggest opening a bug report. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: Bug in g++ 4.1.2 when using inline function definied in cpp file but declared in h file

of the a.cpp file. This way it will be visible in main.cpp when we call it, and then gcc will emit it. Or you can fix it by using pragma implementation and pragma interface as you discovered. I'm not a C++ expert. There may also be other ways to fix this. -- Jim Wilson, GNU Tools Support, http

Re: IEEE Math is not working on Alpha Rawhide

- math on my system? It seems to be a bug, because on Kernel 2.4 I was able to compile the tool. If this worked on a different kernel with the same compiler version, then that indicates a kernel bug. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: code block simply not generated

that there is a branch to father. Branches are not supported in asms. This is mentioned in the gcc manual. We can not get control flow correct in this case, and hence can not optimize correctly. -- Jim Wilson, GNU Tools Support, http://www.specifix.com

Re: Couldn't install GCC properly in my cygwin!

poovizhi wrote: I've CYGWIN_NT-5.0 (1.3.22) version installed in my system. Here I try to install a fresh GCC version (GCC-3.4.6). But I don't have already any compiled version of GCC in my system. If you don't already have a compiler, then you won't be able to compile the gcc sources on your

Re: Works on dev-c..

beradero wrote: Hello, It's the code: http://www.nabble.com/file/p16128572/1.c 1.c Try enter the number 0010 (number then), 00010, etc.. and see the bizarre output.. Your code is buggy. This is an obvious string overflow problem. You can't fit a 6 character string into a 4 character

Re: Building GCC-3.2.3 failed on i686-pc-cygwin

se7en_hills wrote: [EMAIL PROTECTED] /cygdrive/f/project/gcc_build $ make all-gcc make.exe: *** No rule to make target `Makefile.in', needed by `Makefile'. Stop. If you look in Makefile, you should find a line that reads something like Makefile: $(srcdir)/Makefile.in ... which means Makefile

Re: gcc-4.3.0 configure can't identify ld 2.18 version

Yevgeniy Litvinenko wrote: I've found out that two configure scripts can not determine the linker version. These scripts are: gcc-4.3.0/libstdc++-v3/configure and gcc-4.3.0/libgomp/configure We don't track bugs mailed to the gcc-bugs mailing list. File a problem in bugzilla, or ask on

Re: Building newlib-1.15.0 with gcc-4.3.0 for arm-elf

Mariusz Janiak wrote: ../../../../../../../../newlib-1.15.0/newlib/libc/machine/arm/setjmp.S: Assembler messages: ../../../../../../../../newlib-1.15.0/newlib/libc/machine/arm/setjmp.S:123: Error: SP not allowed in register list -- `stmea a1!,{v1-v7,fp,ip,sp,lr}'

Re: can/should autoincrement get optimized away?

John Breitenbach wrote: char can't be less-than zero. However, can't make up my mind as to whether or not it should be allowed to optimize away the post-increment. It is not OK to optimize away the post-increment. This is a gcc optimization bug. Jim

Re: [patch] Add new -gmlt option for min. debug info with line tables (issue4440072)

On Tue, 2011-05-03 at 16:24 -0400, Jason Merrill wrote: That makes sense to me; it seems appropriate for -g1 to have information that makes a backtrace more informative, but not information for interactive debugging. Jim, do you have an opinion? I'm not aware of any significant use of -g1.

Re: [AArch64][PR65375] Fix RTX cost for vector SET

Resending, now that I've figured out how to make gmail send text email instead of html. Almost, what we want at the moment is COSTS_N_INSNS (1) + extra_cost-vect.alu This won't work, because extra_cost-vect.alu is COSTS_N_INSNS (1), which means the total is COSTS_N_INSNS (2). The

[wwwdocs] Update my association in steering committee list

I have checked in this change. Validated as XHTML 1.0 Transitional. Jim Index: htdocs/steering.html === RCS file: /cvs/gcc/wwwdocs/htdocs/steering.html,v retrieving revision 1.39 diff -r1.39 steering.html 41c41 liJim Wilson

gcc make clean fixes

/ChangeLog (revision 222394) +++ ada/ChangeLog (working copy) @@ -1,3 +1,8 @@ +2015-04-23 Jim Wilson jim.wil...@linaro.org + + * gcc-interface/Makefile-lan.in (ada.mostlyclean): Remove gnatbind + and gnat1. + 2015-04-13 Eric Botcazou ebotca...@adacore.com * gnatvsn.ads (Library_Version): Bump to 6

update docs for --enable-languages

language if bootstrapping. And lto is a boot language if --enable-lto which is the default. Jim Index: ChangeLog === --- ChangeLog (revision 222491) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2015-04-27 Jim Wilson jim.wil

Re: gcc make clean fixes

On Mon, Apr 27, 2015 at 12:30 PM, Jeff Law l...@redhat.com wrote: Looks good to me. Please install if you haven't already done so. Thanks, I checked in the patch. I'm not maintainer of anything currently, so I'm assuming all of my patches need to be approved before check in. I'm pretty rusty,

Re: [Bug target/66015] New: align directives not propagated after __attribute__ ((__optimize__ (O2)))

On Tue, 2015-05-05 at 14:19 +0200, Christian Bruel wrote: I don't the environment to run the testsuite for ia64. would you mind giving it a try and verify that it fixes the issue ? I don't have ia64 hardware anymore. The GCC compile farm advertises ia64 hardware

[PATCH, doc] fix match-and-simplify API doc errors

-in ternary function case with four tree args is missing. Jim 2015-05-07 Jim Wilson jim.wil...@linaro.org * doc/match-and-simplify.texi (GIMPLE API): Add missing fourth tree arg to last gimple_simplify declaration. Add missing gimple_build declaration for built-in function case with four tree args

[PATCH, ARM, doc] add missing -mtune options

I noticed that the list of -mtune options in the arm-cores.def file didn't match the list in the doc/invoke.texi file. There are 3 cores missing: generic-armv7-a, cortex-a17, and cortex-a17.cortex-a7. This patch adds the missing cores to the docs. Jim 2015-05-07 Jim Wilson jim.wil

Re: update docs for --enable-languages

ping https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01690.html Jim On Mon, Apr 27, 2015 at 5:09 PM, Jim Wilson jim.wil...@linaro.org wrote: I noticed this while working on my mostlyclean patch. The list of languages in the docs for --enable-languages is incomplete. It is missing jit and lto

[PATCH] move check-gcc parallelize value into C front end

to be the only testsuite target that hasn't already been parallelized. This also looks like an oversight, but I haven't tested a patch for that yet. Jim gcc/ 2015-05-17 Jim Wilson jim.wil...@linaro.org * Makefile.in (check_gcc_parallelize): Delete. (lang_checks_parallelized): Update comment. gcc/c 2015

[PATCH, AARCH64] improve long double 0.0 support

patterns. I plan to submit a patch to fix them after this one is accepted. Jim 2015-06-03 Jim Wilson jim.wil...@linaro.org * config/aarch64/aarch64.c (aarch64_valid_floating_const): Move aarch64_float_const_zero_rtx_p check before TFmode check. * config/aarch64/aarch64.md (movtf): Don't call

Re: [PATCH, AARCH64] make stdarg functions work with +nofp

On Tue, Jun 2, 2015 at 3:45 AM, James Greenhalgh james.greenha...@arm.com wrote: On Tue, Jun 02, 2015 at 11:38:29AM +0100, Kyrill Tkachov wrote: Hi James, Jim, On 02/06/15 10:42, James Greenhalgh wrote: On Sat, May 23, 2015 at 12:24:00AM +0100, Jim Wilson wrote: The compiler currently ICEs

[PATCH, AARCH64] improve float/double 0.0 support

with a default languages make bootstrap and make check.. I see an additional 8 passes, and no other change in the testsuite results. Jim gcc/ 2015-06-19 Jim Wilson jim.wil...@linaro.org * config/aarch64/aarch64.md (movmode:GPF): Don't call force_reg if op1 is an fp zero. (movsf_aarch64): Change

Re: [PATCH, AARCH64] make stdarg functions work with +nofp

On Tue, Jun 16, 2015 at 1:46 AM, James Greenhalgh james.greenha...@arm.com wrote: I'm happy for this to be backported. Thanks. Applied. I think Grub probably wants to change if they want to be safe, from what I've read it looks like they are hoping to use something like a standard printf

[PATCH, AARCH64] movi type attribute confusion

is still waiting review, but the overlap is trivial to resolve so this should not be a problem. Jim 2015-06-12 Jim Wilson jim.wil...@linaro.org * config/aarch64/aarch64.md (movmode_aarch64): Change alternative 2 to use neon_move instead of mov_imm. (movdi_aarch64): Change alternative 14

Re: [PATCH, AARCH64] improve long double 0.0 support

On 06/03/2015 05:35 PM, Jim Wilson wrote: I noticed that poor code is emitted for a long double 0.0. ping https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00370.html Jim

Re: why - warning: array subscript is above array bounds

On 05/28/2015 12:41 PM, 田部 wrote: gcc is, in this code, or put out a warning? -O4 only??? -O3 and higher enables more aggressive loop unrolling. This happens in the pass_complete_unrolli function. With -O3 or higher, the inner loop is unrolled 12 times because the array size is 12. The array

Re: C++ PATCH to change default dialect to C++14

that. Trying it now, I see that my build gets past the point that it failed, so this does appear to work. I won't be able to finish a proper test until tomorrow, but for now this patch seems to work. Jim 2015-07-01 Jim Wilson jim.wil...@linaro.org * graphite-blocking.c (HAVE_isl): Include

Re: C++ PATCH to change default dialect to C++14

On 07/01/2015 11:26 AM, Jason Merrill wrote: I've been threatening to do this for a couple of months, and now that the regressions are under control I think it's time. This patch changes the default C++ dialect to C++14. Tested x86_64-pc-linux-gnu, applying to trunk. This causes a build

Re: C++ PATCH to change default dialect to C++14

On 07/01/2015 11:17 PM, Jim Wilson wrote: On Wed, Jul 1, 2015 at 10:21 PM, Jason Merrill ja...@redhat.com wrote: This document also says that A workaround until libraries get updated is to include cstddef or stddef.h before any headers from that library. Can you try modifying the graphite

Re: C++ PATCH to change default dialect to C++14

On Thu, Jul 2, 2015 at 6:08 AM, Richard Biener richard.guent...@gmail.com wrote: On Thu, Jul 2, 2015 at 3:05 PM, Richard Biener richard.guent...@gmail.com wrote: Yeah, I _think_ the fix is to move the isl includes below the system.h include. I tried this, and got a conflict for pretty much

[PATCH, AARCH64] make stdarg functions work with +nofp

. The testsuite already has multiple stdarg tests, so there is no need for another one. I tested this by verifying I get the same results for some simple testcasess with and without the patch, with and without using -mgeneral-regs-only and -mcpu=cortex-a53+nofp. 2015-05-22 Jim Wilson jim.wil...@linaro.org

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jul 7, 2015 at 8:07 AM, Jeff Law l...@redhat.com wrote: On 06/29/2015 07:15 PM, Jim Wilson wrote: So if these copies require a conversion, then isn't it fundamentally wrong to have a PHI node which copies between them? That would seem to implicate the eipa_sra pass as needing

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Thu, Jul 2, 2015 at 2:07 AM, Richard Earnshaw richard.earns...@foss.arm.com wrote: Not quite, ARM state still has more flexible addressing modes for unsigned byte loads than for signed byte loads. It's even worse with thumb1 where some signed loads have no single-register addressing mode

[PATCH, ARM] stop changing signedness in PROMOTE_MODE

/ 2015-06-29 Jim Wilson jim.wil...@linaro.org PR target/65932 * config/arm/arm.h (PROMOTE_MODE): Don't set UNSIGNEDP for QImode and HImode. gcc/testsuite/ 2015-06-29 Jim Wilson jim.wil...@linaro.org PR target/65932 * gcc.target/arm/wmul-1.c (mac): Change a and b to int pointers. Cast

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jul 14, 2015 at 9:13 AM, Richard Earnshaw richard.earns...@foss.arm.com wrote: We went through this a couple of weeks back. The backend documentation for PROMOTE_MODE says: I disagree that this is a fully resolved issue. I see clear problems with how the ARM port uses PROMOTE_MODE.

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Wed, Jul 15, 2015 at 6:04 AM, Michael Matz m...@suse.de wrote: Hi, On Tue, 14 Jul 2015, Jim Wilson wrote: Now that we do have the problem, we can't fix it without an ARM port ABI change, which is undesirable, so we may have to fix it with a MI change. What's the ABI implication

[PATCH] [ARM] neon-testgen.ml typo

knows ocaml will have to fix this. Meanwhile, the patch to fix the typo should still be OK, as this is a separate problem. Jim 2015-10-29 Jim Wilson <jim.wil...@linaro.org> * config/arm/neon-testgen.ml: Fix comment typo. Index: config/arm/neon-test

[PATCH] [C] fix for ICE with -g

problem may no longer be necessary. I haven't looked at that. Jim Index: gcc/c/ChangeLog === --- gcc/c/ChangeLog (revision 229395) +++ gcc/c/ChangeLog (working copy) @@ -1,3 +1,9 @@ +2015-10-26 Jim Wilson <jim.wil...@linaro.

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

ot already done. This was tested with a arm-eabi cross compiler build configured --with-multilib-list=aprofile, and then using ./xgcc -B./ -mcpu=X --print-libgcc to verify that processor names map to the correct libgcc multilib. Jim 2015-11-12 Jim Wilson <jim.wil...@linaro.org> * gcc/

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

On Fri, Nov 13, 2015 at 9:02 AM, Kyrill Tkachov wrote: > Sorry to chime in late on this, but while you're at it could > you please add an xgene1 entry? Yes, I just realized that xgene1 is missing too, I rushed the patch a little too much. I will revise it to add xgene1

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

Revised patch with the also missing xgene1 part added. Jim 2015-11-13 Jim Wilson <jim.wil...@linaro.org> * gcc/config/arm/t-aprofile (MULTILIB_MATCHES): Add lines for exynos-m1 and qdf24xx and xgene1 to match -march=armv8-a. Index: gcc/config/arm/t-ap

[PATCH] [ARM/Aarch64] add initial Qualcomm support

) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,13 @@ +2015-11-10 Jim Wilson <jim.wil...@linaro.org> + + * config/aarch64/aarch64-cores.def (qdf24xx): New. + * config/aarch64/aarch64-tune.md: Regenerated. + * config/arm/arm-cores.def (qdf24xx): New. + * config/arm/arm-tables.opt, config/arm/arm-t

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

On Wed, Nov 11, 2015 at 10:34 AM, Jim Wilson <jim.wil...@linaro.org> wrote: > I had to disable the cortex-a57 fma steering pass in the aarch64 port > while testing the patch. A bootstrap for aarch64 configured > --with-cpu=cortex-a57 gives multiple ICEs while building the s

Re: [PATCH] PR67305, tighten neon_vector_mem_operand on eliminable registers

On 11/04/2015 01:45 AM, Jiong Wang wrote: > So as Jim Wilson commented on the bugzilla, instead of "return !strict", > we need to only do the check if strict be true, and only does rejection > which means return FALSE, for all other cases, we need to go through > those n

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Wed, Jul 8, 2015 at 3:54 PM, Jeff Law l...@redhat.com wrote: On 07/07/2015 10:29 AM, Jim Wilson wrote: This is critically important as various parts of the compiler will take a degenerate PHI node and propagate the RHS of the PHI into the uses of the LHS of the PHI -- without doing any

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jul 7, 2015 at 2:35 PM, Richard Biener richard.guent...@gmail.com wrote: On July 7, 2015 6:29:21 PM GMT+02:00, Jim Wilson jim.wil...@linaro.org wrote: signed sub-word locals. Thus to detect the need for a conversion, you have to have the decls, and we don't have them here

Re: [4/7] Use correct promoted mode sign for result of GIMPLE_CALL

On 09/08/2015 08:39 AM, Jeff Law wrote: > Is this another instance of the PROMOTE_MODE issue that was raised by > Jim Wilson a couple months ago? It looks like a closely related problem. The one I am looking at has confusion with a function arg and a local variable as they have differen

Re: [ping] pending patches

On 12/01/2015 11:58 PM, Eric Botcazou wrote: > IA-64 (stack checking improvement): > https://gcc.gnu.org/ml/gcc-patches/2015-11/msg01604.html OK. Jim

Re: [ARM][PR69194] Fix ICE in in extract_insn

Here is a smaller simpler testcase. Only the first four args get passed in regs, so the fifth one has address equal to the virtual incoming args reg which triggers the failure. typedef __simd128_float32_t float32x4_t; float32x4_t sub (float32x4_t a, float32x4_t b, float32x4_t c, float32x4_t d,

[PATCH] fix vectorizer performance problem on cygwin hosted cross compiler

no regressions. I've also done a SPEC CPU2000 run with and without the patch on aarch64-linux, there is no performance change. And I've verified it by building linpack for aarch64-linux with cygwin hosted cross compiler, x86_64 hosted cross compiler, and an aarch64 native compiler. Jim 2015-11-19 Jim

Re: [RFC][ARM][PR67714] signed char is zero-extended instead of sign-extended

On Tue, Jan 12, 2016 at 5:40 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > The info is in here > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65932 > See the comments on gcc.target/arm/wmul-[123].c which no longer > generate smulbb etc instructions, which are 16x16=32 expa

Re: [RFC][ARM][PR67714] signed char is zero-extended instead of sign-extended

On Mon, Jan 11, 2016 at 10:22 PM, kugan wrote: > When promote_function_mode and promote_ssa_mode changes the sign > differently, following is the cause for the problem in PR67714. > This is similar to PR65932 where sign change in PROMOTE_MODE causes problem >

Re: [RFC][ARM][PR67714] signed char is zero-extended instead of sign-extended

On Tue, Jan 12, 2016 at 5:10 PM, Kugan wrote: > Yes, making PROMOTE_MODE to work the same way as in > promote_function_mode in arm will fix this. Can you please point me to > the test cases that are regressing so that I can also start looking at them. The info

Re: [PATCH][wwwdocs][AArch64] Mention -mcpu=qdf24xx support for GCC 6

On Thu, Jun 9, 2016 at 1:43 AM, Kyrill Tkachov wrote: > On 03/06/16 21:32, Evandro Menezes wrote: >> Shouldn't this read "The Qualcomm QDF24xx processors are now supported via >> the"? >> > I used Jim's suggestion at >

[PATCH, AARCH64] add qdf24xx tuning structure

This adds a tuning structure for qdf24xx. This was tested with an aarch64-linux bootstrap and a make check, with no regressions. I also tested it with an x86_64-linux C make check to verify that I didn't break the testsuite for non aarch64 targets. I had to change one testcase because it

Re: [PATCH][AArch64] Enable -frename-registers at -O2 and higher

On Tue, May 31, 2016 at 2:56 AM, James Greenhalgh wrote: > As you're proposing to have this on by default, I'd like to give a chance > to hear whether there is consensus as to this being the right choice for > the thunderx, xgene1, exynos-m1 and qdf24xx subtargets. I

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