Hi Kaz,
This patch fixes a case in sh.c:find_barrier(), triggered by a testcase
in glibc. The scanning starts from a GOT move instruction, records
itself in 'last_got', but does not find a second GOT move (to reset
last_got to NULL).
It finishes by trying to insert a new barrier in the insn
On Mon, 26 Mar 2012, Eric Botcazou wrote:
Uh. When is a field a bit field though? At least stor-layout.c
resets DECL_BIT_FIELD
when local relative alignment is proper and the filed has an integer
mode. That's
overly optimistic if the record is placed at a bit position. Of
course
On Mon, 26 Mar 2012, Eric Botcazou wrote:
The patch looks reasonable - can we compute this backward from the
result of the outer get_inner_reference call and the outermost
field-decl though? Or make get_inner_reference compute that while
analyzing the full reference and return a flag?
Btw, I put things in stor-layout.c exactly to allow a langhook
eventually controlling things for the bitfield representative.
Mind adding one that simply disables them completely for Ada?
Or maybe, for selected record types, so that we do
if (lang_hooks.types.lower_bitfield_layout (rli-t))
On Mon, Mar 26, 2012 at 10:56 PM, Steven Bosscher stevenb@gmail.com wrote:
Hello,
This patch is one way to address PR44982. I see no good reason to
cgraph_finalize_compilation_unit if there were parse errors. As Richi
already pointed out, GCC traditionally has proceeded after parse
On Tue, 27 Mar 2012, Eric Botcazou wrote:
Btw, I put things in stor-layout.c exactly to allow a langhook
eventually controlling things for the bitfield representative.
Mind adding one that simply disables them completely for Ada?
Or maybe, for selected record types, so that we do
if
On Mar 26, 2012, at 11:43 PM, Janne Blomqvist wrote:
[...]
On x86_64-unknown-linux-gnu bootstrap I see the following:
make[1]: Entering directory
`/home/janne/src/gfortran/trunk/objdir-git/x86_64-unknown-linux-gnu/libgfortran'
make check-am
make[2]: Entering directory
Now that we are back in stage1, I'd like to apply
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00304.html, a change to
toc reference rtl in order to properly specify r2 dependencies. More
commentary in that url. I'm reposting the patch here since the old
one no longer applies cleanly, and I've
On Mar 27, 2012, at 9:51 AM, Tristan Gingold wrote:
On Mar 26, 2012, at 11:43 PM, Janne Blomqvist wrote:
[...]
On x86_64-unknown-linux-gnu bootstrap I see the following:
make[1]: Entering directory
`/home/janne/src/gfortran/trunk/objdir-git/x86_64-unknown-linux-gnu/libgfortran'
Hi!
Ping.
On Wed, 21 Mar 2012 15:56:04 +0100, I wrote:
On Thu, 15 Mar 2012 11:57:00 -0400, Carlos O'Donell car...@systemhalted.org
wrote:
On Thu, Mar 15, 2012 at 11:05 AM, Thomas Schwinge
tho...@codesourcery.com wrote:
On 26 Feb 2012 18:17:52 -, drep...@sourceware.org wrote:
I see. Though the code does not affect layout but only access layout
for bitfields. I'm fine with fixing the issues we run into elsewhere,
just the langhook is a possibility I had in mind from the start, in
case frontends differ in their memory model for bitfields.
Understood. According to
On Tue, Mar 27, 2012 at 11:01, Tristan Gingold ging...@adacore.com wrote:
Hi,
this patch fixes this issue. Is it OK ?
Ok.
Maybe we should include the AC_DEFINE action within GCC_CHECK_MATH_FUNC.
Will try to do that.
That looks like a cleaner solution, yes, and less chance for typos to
Hi,
this fixes a thinko that leads to wrong-code generation that is in the
new SRA since the beginning. When there are two unscalarizable
regions in an access tree, one within another, the aggregate
assignment modification code may use them as basis of new memory
accesses, which means it very
This fixes a couple of bugs I noticed in std::result_of, the first new
test covers those bugs, the second new test is just taken from the
standard to test result_of a little more thoroughly.
* include/std/type_traits (result_of): Fix handling of cv-quals.
*
On Tue, 27 Mar 2012, Martin Jambor wrote:
Hi,
this fixes a thinko that leads to wrong-code generation that is in the
new SRA since the beginning. When there are two unscalarizable
regions in an access tree, one within another, the aggregate
assignment modification code may use them as
On Mar 27, 2012, at 10:38 AM, Janne Blomqvist wrote:
On Tue, Mar 27, 2012 at 11:01, Tristan Gingold ging...@adacore.com wrote:
Hi,
this patch fixes this issue. Is it OK ?
Ok.
No check-gfortran regressions on x86_64-darwin, committed.
Maybe we should include the AC_DEFINE action
Hi,
On Mon, Mar 26, 2012 at 10:56 PM, Steven Bosscherstevenb@gmail.com wrote:
Hello,
This patch is one way to address PR44982. I see no good reason to
cgraph_finalize_compilation_unit if there were parse errors. As Richi
already pointed out, GCC traditionally has proceeded after parse
On Mar 22, 2012, at 6:34 PM, Richard Henderson wrote:
On 03/22/12 07:55, Tristan Gingold wrote:
2012-03-22 Tristan Gingold ging...@adacore.com
* config/ia64/unwind-ia64.h: Declare unw_word and unw_sword.
(unw_table_entry): Use unw_word instead of unsigned long.
Oleg Endo oleg.e...@t-online.de wrote:
The attached patch generalizes the move insn displacement calculations a
little bit. Before, the same address rebasing code was present in
sh_legitimize_address as well as sh_legitimize_reload_address. I've
pulled those out into a separate function as a
Chung-Lin Tang clt...@codesourcery.com wrote:
This patch fixes a case in sh.c:find_barrier(), triggered by a testcase
in glibc. The scanning starts from a GOT move instruction, records
itself in 'last_got', but does not find a second GOT move (to reset
last_got to NULL).
It finishes by
Hi,
I noticed that the tests were failing in ARM mode. Fixed thusly as
these tests are only meant to be run for Thumb state.
Committed to trunk.
regards.
Ramana
2012-03-27 Ramana Radhakrishnan ramana.radhakrish...@linaro.org
* gcc.target/arm/thumb-ifcvt.c: Only run for -mthumb.
This patch fixes a problem with the -mtiny-stack option:
Architectures avr2 and avr25 mix targets with 8-bit SP and 16-bit SP so that
-mtiny-stack is no good for multilib selection:
If a frame pointer has to be set up from an 8-bit SP it is a difference if
there is no SP_H or of the SP is just
Thomas Schwinge tho...@codesourcery.com writes:
libgcc/
* config/alpha/linux-unwind.h (alpha_fallback_frame_state): Use
siginfo_t instead of struct siginfo.
* config/bfin/linux-unwind.h (bfin_fallback_frame_state): Likewise.
* config/i386/linux-unwind.h
This fixes PR52720.
Bootstrapped and tested on x86_64-unknown-linux-gnu, applied on the
trunk and the branch.
Richard.
2012-03-27 Richard Guenther rguent...@suse.de
PR middle-end/52720
* fold-const.c (try_move_mult_to_index): Handle x.array more
explicitely.
Hi,
One of the problems with ivopts is that the auto-increment modelling
just takes into account whether HAVE_PRE_INC and friends are defined
for the architecture. However on ARM the VFP addressing modes don't
really support PRE_INCREMENT and POST_DECREMENT forms and hence there
is a bias in
Ping
13 марта 2012 г. 15:13 пользователь Ilya Enkovich
enkovich@gmail.com написал:
Ping
27 февраля 2012 г. 6:41 пользователь Ilya Enkovich
enkovich@gmail.com написал:
You should keep those *_SPEC and define them with new
GNU_*_SPEC in gnu-user.h since gnu-user.h is also used
by
Ping
13 марта 2012 г. 15:12 пользователь Ilya Enkovich
enkovich@gmail.com написал:
Ping
27 февраля 2012 г. 6:39 пользователь Ilya Enkovich
enkovich@gmail.com написал:
Undef TARGET_OS_CPP_BUILTINS and define TARGET_OS_CPP_BUILTINS
in linux.h with GNU_USER_TARGET_OS_CPP_BUILTINS and
On Mon, 26 Mar 2012, H.J. Lu wrote:
The same set of macros are provided. The only differences are the
order of bits used and macro definitions. I am doing a full bootstrap and
test on Linux/x86-64. OK for trunk if there are no regressions?
OK.
--
Joseph S. Myers
jos...@codesourcery.com
On 03/09/2012 10:01 AM, Sebastian Huber wrote:
Hi,
please have a look at the attached patch. Test suite results for GCC 4.7
http://gcc.gnu.org/ml/gcc-testresults/2012-03/msg00986.html
I get the same test suite results with:
powerpc-*-eabi* | powerpc-*-rtems*)
tmake_file=${tmake_file}
On Mon, Mar 26, 2012 at 9:03 PM, H.J. Lu hjl.to...@gmail.com wrote:
Attached patch fixes this situation by (partially) reloading only
remaining pseudo(s), leaving UNSPEC in the address RTX.
2012-03-26 Uros Bizjak ubiz...@gmail.com
PR target/52698
* config/i386/i386-protos.h
Sebastian Huber sebastian.hu...@embedded-brains.de writes:
What is the purpose of the ctrbegin.o and crtend.o?
The same as crtbeginS.o and crtendS.o, except for non-shared linking.
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5
Uros Bizjak wrote:
In a corner case of a reload, reload pass can generate partially
reloaded address, where not all registers get allocated to a hard reg.
When this address is checked with ix86_legitimate_address, it is
rejected, since in strict mode, pseudos are not valid address
registers.
On Tue, Mar 27, 2012 at 6:13 PM, Ulrich Weigand uweig...@de.ibm.com wrote:
Since fixing reload issues is some kind of black magic, I'd like to
ask Ulrich and Richard for their opinion on this approach.
Well, generally speaking, reload makes a lot of assumptions on how
addresses can look
On Tue, Mar 27, 2012 at 9:37 AM, Uros Bizjak ubiz...@gmail.com wrote:
On Tue, Mar 27, 2012 at 6:13 PM, Ulrich Weigand uweig...@de.ibm.com wrote:
Since fixing reload issues is some kind of black magic, I'd like to
ask Ulrich and Richard for their opinion on this approach.
Well, generally
On Tue, Mar 27, 2012 at 6:57 PM, H.J. Lu hjl.to...@gmail.com wrote:
Well, generally speaking, reload makes a lot of assumptions on how
addresses can look like; it needs to, since if a target rejects an
address as invalid as-is, reload must fix it up -- and it can do
so only by making
Adds a new flag -fpph-statistics. When used, it shows various collected
stats at the end of PPH processing.
2012-03-27 Diego Novillo dnovi...@google.com
c-family/ChangeLog.pph
* c.opt (fpph-stats): Add flag.
cp/ChangeLog.pph
* pph-core.c (pph_stats): Declare.
The following patch implements general spilling one class pseudos
into another class hard registers *instead of memory* in LRA.
Currently, the patch implements spilling of general reg pseudos into
SSE regs for Intel Core architecture as it is recommended by Intel
optimization guide. Such
On 03/27/12 09:37, Uros Bizjak wrote:
Now, in this particular case, there might be another option to
avoid this hassle completely: I understand that this UNSPEC is
simply a magic marker to make the address use the fs: or gs:
segment override, right? Now that GCC supports address spaces,
The optimization might be useful for some other processors which
have direct move insns for the two considered classes and when IRA for
some reasons did not use the class union. At least I see
that we could try this for ARM (spilling general regs into VF regs)
and for extended powerpc
On Tue, Mar 27, 2012 at 9:57 AM, Uros Bizjak ubiz...@gmail.com wrote:
On Tue, Mar 27, 2012 at 6:57 PM, H.J. Lu hjl.to...@gmail.com wrote:
Well, generally speaking, reload makes a lot of assumptions on how
addresses can look like; it needs to, since if a target rejects an
address as invalid
Hi,
This patch removes MaskExists property from config/*/*.opt files
since MaskExists handling has been removed. Tested on Linux/x86-64.
There is no difference between options.h before and after the patch.
OK for trunk?
Thanks.
H.J.
---
2012-03-27 H.J. Lu hongjiu...@intel.com
*
On Sat, Mar 24, 2012 at 03:42:29PM -0700, H.J. Lu wrote:
Hi,
In i386 option mask, there is OPTION_MASK_ISA_64BIT for -m64 or -mx32
code generations and OPTION_MASK_ISA_X32 for -mx32 code generation. We
support
-m64: OPTION_MASK_ISA_64BIT !OPTION_MASK_ISA_X32
-mx32: OPTION_MASK_ISA_64BIT
2012/3/27 Georg-Johann Lay a...@gjlay.de:
This patch fixes a problem with the -mtiny-stack option:
Architectures avr2 and avr25 mix targets with 8-bit SP and 16-bit SP so that
-mtiny-stack is no good for multilib selection:
If a frame pointer has to be set up from an 8-bit SP it is a
On Tue, Mar 27, 2012 at 7:28 PM, H.J. Lu hjl.to...@gmail.com wrote:
GCC needs to move the value in the %fs segment
register into %r32 or %r64. This instruction
mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}
does exactly what GCC wants.
Sorry, I really don't understand what you are trying to
On Tue, Mar 27, 2012 at 10:53 AM, Uros Bizjak ubiz...@gmail.com wrote:
On Tue, Mar 27, 2012 at 7:28 PM, H.J. Lu hjl.to...@gmail.com wrote:
GCC needs to move the value in the %fs segment
register into %r32 or %r64. This instruction
mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}
does exactly
On Tue, Mar 27, 2012 at 8:34 PM, H.J. Lu hjl.to...@gmail.com wrote:
%fs and %gs are special in 64bit mode. For a memory operand
%fs:address, its effective address is base address of %fs + address.
The base address of %fs and %fs are hidden. mov %fs, %eax
will only access the visible part of
On Mar 26, 2012, at 1:56 PM, Steven Bosscher wrote:
This patch is one way to address PR44982.
That's a great idea, I like it. There is only one problem that I know of that
prevents it from going in now. We emit errors/warnings from below finalize and
there is a feature in which we emit all
On Tue, Mar 27, 2012 at 8:59 PM, Mike Stump mikest...@comcast.net wrote:
and errors from the middle end are mostly for exotic
code (involving asm()s and the like). Bailing out after parse errors
is therefore IMHO the right thing to do for the common case.
Some are for very exotic things, yes,
On Tue, 27 Mar 2012, H.J. Lu wrote:
Hi,
This patch removes MaskExists property from config/*/*.opt files
since MaskExists handling has been removed. Tested on Linux/x86-64.
There is no difference between options.h before and after the patch.
OK for trunk?
OK.
--
Joseph S. Myers
Add more PPH timers and stats.
We are spending too much time inside the reading of template bodies.
This patch adds more timers that pinpoint the problem to be the
hashing of specialization tables. We spend roughly 50% of PPH reading
inside the hashing code.
2012-03-27 Diego Novillo
Applied.
Index: htdocs/gcc-4.7/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.105
diff -u -r1.105 changes.html
--- htdocs/gcc-4.7/changes.html 26 Mar 2012 13:04:45 - 1.105
+++
On 08/03/12 18:03, Richard Henderson wrote:
On 03/08/12 08:19, Andrew Stubbs wrote:
+ (set_attr arch nota8,*,*,onlya8)
+ (set_attr_alternative insn_enabled
+ [(if_then_else (match_test TARGET_NEON)
+ (const_string yes) (const_string no))
+(const_string
* include/std/functional (mem_fn): Qualify to prevent ADL.
* testsuite/20_util/function_objects/mem_fn/adl.cc: New.
Tested x86_64-linux, committed to trunk. Not a regression but should
be safe for all branches.
commit be288d23ed09bfabb8d1bc736e236c5b9e80beb3
Author: Jonathan Wakely
Hello,
The Java front end emits assembly from class.c:emit_register_classes()
to fill the .jcr section. This is not something a front end ought to
be doing. Things to write out to the assembler output file should go
through the varpool/varasm mechanism. The attached patch makes
Hi!
As the following testcase shows, the sse2_loadlpd splitter when
the destination (and at the same operand from which the second
DFmode element is taken) is a MEM and the other DFmode operand
is a register stores into wrong part of memory, it does what
the sse2_loadhpd splitter does, while it
On 03/27/12 13:23, Andrew Stubbs wrote:
gcc/
* config/arm/arm.md (arch): Add neon_onlya8 and neon_nota8.
(arch_enabled): Handle new arch types.
(one_cmpldi2): Add NEON support.
Looks good to me.
r~
Changelog:
* expmed.c (store_bit_field_1): Fix wordnum value for big endian targets
The author line was missing so I put:
2012-03-27 Aurelien Buhrig aurelien.buhrig@gmail.com
PR middle-end/51893
* expmed.c (store_bit_field_1): Fix wordnum value for big-endian
Bootstrapped/regtested on x86_64-suse-linux, applied on mainline. Should
it be applied to the release branches as well?
2012-03-26 Eric Botcazou ebotca...@adacore.com
PR rtl-optimization/52629
* reload1.c (count_pseudo): Short-circuit common case.
With this patch a variable named _Jv_CLS is written out. The
assembly before and after the patch is the same, except for the
variable name. I want to write out a nameless variable but I don't
know how.
Try tree_output_constant_def.
--
Eric Botcazou
Hi All,
This patch fixes an issue reported by one of our customers where an instruction
exception gets raised when using '__sync_fetch_and_add' on a PowerPC 440
processor. The instruction causing the exception is 'lwsync'. Luckily Joseph
laid the groundwork when solving a similar issue for e500
On Tue, Mar 27, 2012 at 11:07 PM, Eric Botcazou ebotca...@adacore.com wrote:
With this patch a variable named _Jv_CLS is written out. The
assembly before and after the patch is the same, except for the
variable name. I want to write out a nameless variable but I don't
know how.
Try
Hi Richard,
Segment registers %fs and %gs are special in 64bit mode. For a memory
operand %fs:address, its effective address is the base address of %fs +
address. The base address of %fs are hidden and mov %fs, %ax will only
access the visible part of %fs, which is the 16bit segment selector.
On Tue, Mar 27, 2012 at 11:51 PM, Steven Bosscher stevenb@gmail.com wrote:
On Tue, Mar 27, 2012 at 11:07 PM, Eric Botcazou ebotca...@adacore.com wrote:
With this patch a variable named _Jv_CLS is written out. The
assembly before and after the patch is the same, except for the
variable
On 03/28/2012 03:15 AM, Terry Guo wrote:
Hello,
Thanks Paolo Carlini for pointing out that I should put code changes in
Makefile.am. This updated patch addresses this issue. Is it OK to trunk?
Sure, thanks.
Paolo.
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