Re: [PATCH], Pr 71667, Fix PowerPC ISA 3.0 DImode Altivec load/store

On Mon, Jun 27, 2016 at 08:08:20PM -0400, Michael Meissner wrote: > This patch fixes PR 71667 that I discovered when trying to build the Spec 2006 > xalancbmk benchmark for the Power9. The Altivec indexed memory load/stores > need to go before the D-form (register + offset) load/stores, because

[PATCH, contrib] download_prerequisites: check for existing symlinks before making new ones

The last time I ran ./contrib/download_prerequisites, I already had previous symlinks set up from a previous run of the script, so `ln` followed the existing symlinks and created the new ones in the directories to which the symlinks pointed. This patch should fix that by removing the old symlinks

Re: [PATCH, rs6000] Fix PR target 71656, reload ICE when -mcpu=power9 -mpower9-dform-vector

On 6/27/16 3:21 PM, Segher Boessenkool wrote: On Sat, Jun 25, 2016 at 07:14:01PM -0500, Peter Bergner wrote: Okay for trunk, okay for 6 later. One comment: + if (VECTOR_MODE_P (mode) + && !mode_supports_vsx_dform_quad (mode)) +return false; if (GET_CODE (addr) != PLUS)

Re: [PATCH, AARCH64] add qdf24xx tuning structure

On Mon, Jun 13, 2016 at 3:01 AM, Kyrill Tkachov wrote: > Hi Jim, > > On 10/06/16 23:48, Jim Wilson wrote: >> >> This adds a tuning structure for qdf24xx. This was tested with an >> aarch64-linux bootstrap and a make check, with no regressions. I also >> tested it

Re: [PATCH, AARCH64] add qdf24xx tuning structure

On Mon, Jun 13, 2016 at 1:53 AM, James Greenhalgh wrote: > On Fri, Jun 10, 2016 at 03:48:38PM -0700, Jim Wilson wrote: >> This adds a tuning structure for qdf24xx. This was tested with an > Have you seen my recent patch for Cortex-A57 that changes the costs there > to

PING Re: [PATCH 0/9] separate shrink-wrapping

Ping. On Wed, Jun 08, 2016 at 01:47:31AM +, Segher Boessenkool wrote: > This patch series introduces separate shrink-wrapping. > > There are many things the prologue/epilogue of a function do, and most of > those things can be done independently. For example, most of the time, > for many

[PATCH] rs6000: Fix split of ashdi3_extswsli_dot for memory (PR71670)

The splitter for ashdi3_extswsli_dot for cr0 with memory uses emit_insn gen_ashdi3_extswsli_dot, which does not work because that emits a scratch, while the splitter runs after reload so there should be a real register instead. We can laboriously fix that up, or emit using

Re: OpenACC wait clause

On 06/27/2016 12:23 PM, Jakub Jelinek wrote: > On Mon, Jun 27, 2016 at 11:36:26AM -0700, Cesar Philippidis wrote: >> @@ -630,9 +653,10 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, uint64_t >> mask, >> { >>gfc_omp_clauses *c = gfc_get_omp_clauses (); >>locus old_loc; >> + bool

[PATCH] Offer suggestions for misspelled --param names.

Another use of spellcheck.{c|h}, this time for --param. Successfully bootstrapped on x86_64-pc-linux-gnu; adds 4 PASS results to gcc.sum. OK for trunk? gcc/ChangeLog: * opts.c (handle_param): Use find_param_fuzzy to offer suggestions for misspelled param names. *

Re: [PATCH, rs6000] Scheduling update

On Mon, Jun 27, 2016 at 04:46:00PM -0500, Pat Haugen wrote: > On 06/22/2016 02:10 PM, Segher Boessenkool wrote: > >> Index: config/rs6000/htm.md > >> === > >> --- config/rs6000/htm.md (revision 237621) > >> +++ config/rs6000/htm.md

Re: [PATCH, rs6000] Scheduling update

On 06/22/2016 02:10 PM, Segher Boessenkool wrote: >> Index: config/rs6000/htm.md >> === >> --- config/rs6000/htm.md (revision 237621) >> +++ config/rs6000/htm.md (working copy) >> @@ -72,7 +72,8 @@ (define_insn "*tabort" >>

Re: [PATCH], Add PowerPC ISA 3.0 lxsihzx, lxsibzx, stxsihx, stxsibx support

On Mon, Jun 27, 2016 at 05:37:57PM -0400, Michael Meissner wrote: > > > @@ -872,7 +878,6 @@ (define_insn_and_split "*zero_extendsi > > (set_attr "dot" "yes") > > > (set_attr "length" "4,8")]) > > > > > > - > > > (define_insn "extendqi2" > > >[(set (match_operand:EXTQI 0

Re: [PATCH, rs6000] Scheduling update

On Mon, Jun 27, 2016 at 04:24:39PM -0500, Pat Haugen wrote: > On 06/27/2016 03:41 PM, Segher Boessenkool wrote: > >> * config/rs6000/rs6000.md ('type' attribute): Add > >> > vec_logical,veccmp_fx,vec_extend,vecmove insn types. > > Those names are a bit irregular (underscore vs. no

Re: [PATCH], Add PowerPC ISA 3.0 lxsihzx, lxsibzx, stxsihx, stxsibx support

On Mon, Jun 27, 2016 at 03:05:19PM -0500, Segher Boessenkool wrote: > On Thu, Jun 23, 2016 at 06:37:15PM -0400, Michael Meissner wrote: > > PowerPC ISA 3.0 adds new instructions (LXSIHZX, LXSIBZX, STXSIHX, and > > STXSIBX) > > that allow you to load and zero extend byte and half word values from

Re: Ping Re: Implement C _FloatN, _FloatNx types [version 3]

On Mon, Jun 27, 2016 at 09:22:54PM +, Joseph Myers wrote: > > > Ping. This patch > > > is pending > > > review. Built-in functions are available in the followup patch > > >

Re: [PATCH,rs6000] Add support for Power9 DFP Test Significance Immediate instruction

Hi Kelvin, On Mon, Jun 27, 2016 at 11:47:52AM -0600, Kelvin Nilsen wrote: > > This patch adds built-in function support for the new Power9 dtstsfi > instruction. > > This has bootstrapped and regression tested on > powerpc64le-unknown-linux-gnu without regressions. Is this ok for the > trunk?

Re: Ping Re: Implement C _FloatN, _FloatNx types [version 3]

On Mon, 27 Jun 2016, Bill Schmidt wrote: > Hi Joseph, > > > On Jun 27, 2016, at 12:21 PM, Joseph Myers wrote: > > > > Ping. This patch > > is pending > > review. Built-in functions are available in the

Re: [PATCH, rs6000] Scheduling update

On 06/27/2016 03:41 PM, Segher Boessenkool wrote: >> * config/rs6000/rs6000.md ('type' attribute): Add >> > vec_logical,veccmp_fx,vec_extend,vecmove insn types. > Those names are a bit irregular (underscore vs. no underscore after "vec", > "extend" is called "exts" for integer,

Re: [PATCH] Fix FFI return type for closures in the java interpreter

> "Matthew" == Matthew Fortune writes: Matthew> I've identified a latent bug in the java interpreter that affects MIPS Matthew> n32 and n64 ABIs both little and big endian and, I presume, any 64-bit Matthew> big endian target with int as 32-bit. Thanks. Matthew>

Re: Ping Re: Implement C _FloatN, _FloatNx types [version 3]

Hi Joseph, > On Jun 27, 2016, at 12:21 PM, Joseph Myers wrote: > > Ping. This patch > is pending > review. Built-in functions are available in the followup patch >

Re: [PATCH] Document behavior of __builtin_*_overflow_p on bitfields

On Mon, 27 Jun 2016, Jakub Jelinek wrote: > Hi! > > While the docs say that no integral argument promotions are performed, I > think it is better to make the behavior for bit-fields explicitly > documented. > > Ok for trunk? OK. -- Joseph S. Myers jos...@codesourcery.com

Re: [Bug libstdc++/71640] [7 Regression] include/c++/7.0.0/bits/hashtable.h:293:7: error: too many template parameters in template redeclaration

Trivial attached patch applied to fix this regression. I am surprised that gcc had not detected it. 2016-06-27 François Dumont PR libstdc++/71640 * include/bits/hashtable.h: Remove _Unique_keya parameter in _Insert friend declaration. On 26/06/2016 18:21,

Re: [PATCH, rs6000] Scheduling update

On Mon, Jun 27, 2016 at 09:54:09AM -0500, Pat Haugen wrote: > On 06/22/2016 02:10 PM, Segher Boessenkool wrote: > > The "power9_alu2" attribute is writing part of the scheduling description > > inside the machine description proper. Can this be reduced, maybe by > > adding an attribute describing

Re: [PATCH, rs6000] Fix PR target 71656, reload ICE when -mcpu=power9 -mpower9-dform-vector

On Sat, Jun 25, 2016 at 07:14:01PM -0500, Peter Bergner wrote: > This patch fixes PR71656 by adding support to rs6000_legitimize_reload_address > for POWER9 vector-dform addresses. Previously, -mpower9-dform-vector was > disabled when using reload due to this bug and it was not added to the

[PATCH] Fix FFI return type for closures in the java interpreter

Hi, I've identified a latent bug in the java interpreter that affects MIPS n32 and n64 ABIs both little and big endian and, I presume, any 64-bit big endian target with int as 32-bit. A full description is in my original post: https://gcc.gnu.org/ml/java-patches/2016-q2/msg00020.html Patch

Re: [PATCH], Add PowerPC ISA 3.0 lxsihzx, lxsibzx, stxsihx, stxsibx support

On Thu, Jun 23, 2016 at 06:37:15PM -0400, Michael Meissner wrote: > PowerPC ISA 3.0 adds new instructions (LXSIHZX, LXSIBZX, STXSIHX, and STXSIBX) > that allow you to load and zero extend byte and half word values from memory > and to store them back. Okay for trunk with fixes below; okay for 6

Re: OpenACC wait clause

On Mon, Jun 27, 2016 at 11:36:26AM -0700, Cesar Philippidis wrote: > With that aside, this patch should correct the issues you pointed out. > gfc_match_omp_clauses now uses a common function to parse the gang, > worker and vector clauses. Also, this patch takes extra care with > MATCH_ERRORs when

Re: OpenACC wait clause

On 06/24/2016 08:53 AM, Jakub Jelinek wrote: > On Fri, Jun 24, 2016 at 08:42:49AM -0700, Cesar Philippidis wrote: @@ -1328,7 +1328,8 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, uint64_t mask, && gfc_match ("wait") == MATCH_YES) { c->wait =

Re: Implement loop guard heuristics

> Jan Hubicka writes: > > Hi, > > this patch implements loop guard heuristics predicting that if one loop is > > nested in another and controlled by a conditional that conditional is likely > > false. This helps to get more realistic predictionsin larger loop nests. > > Just

[PATCH] Document behavior of __builtin_*_overflow_p on bitfields

Hi! While the docs say that no integral argument promotions are performed, I think it is better to make the behavior for bit-fields explicitly documented. Ok for trunk? 2016-06-27 Jakub Jelinek * doc/extend.texi (__builtin_add_overflow_p): Clarify behavior when

[PATCH] Fix ICE with __builtin_*_overflow_p on bitfields (PR rtl-optimization/71673)

Hi! On targets which don't support sub-word operations trying OPTAB_DIRECT AND on e.g. QImode or HImode leads to NULL being returned, so we ICE on builtin-arith-overflow-p-19.c e.g. on arm, aarch64 or sparc*. Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, tested with

[PATCH] Fix ICE with V1DImode ctor (PR middle-end/71626)

Hi! This patch is an attempt to fix ICE on the following testcase. In output_constant_pool_2 we assume that for vector modes, force_const_mem must be a CONST_VECTOR, but for the weirdo vector modes with single element it could very well be just a SUBREG of some other constant. This isn't enough

Re: Implement loop guard heuristics

Jan Hubicka writes: > Hi, > this patch implements loop guard heuristics predicting that if one loop is > nested in another and controlled by a conditional that conditional is likely > false. This helps to get more realistic predictionsin larger loop nests. Just curious: what's

Re: Importing gnulib into the gcc tree

On Sat, 25 Jun 2016, ayush goel wrote: > Initially I have just imported the bcopy module from gnulib which will > eventually replace gcc’s dependency on libiberty’s bcopy.  GCC should not depend on bcopy. Any bcopy use is a bug and it should be replaced by memcpy or memmove as appropriate.

[PATCH,rs6000] Add support for Power9 DFP Test Significance Immediate instruction

This patch adds built-in function support for the new Power9 dtstsfi instruction. This has bootstrapped and regression tested on powerpc64le-unknown-linux-gnu without regressions. Is this ok for the trunk? Is this patch ok for gcc-6 after some burn-in time on the trunk? Thanks.

Re: [PATCH, rs6000] Add minimum __float128 built-in support required for glibc

> On Jun 27, 2016, at 12:41 PM, Richard Sandiford > wrote: > > Joseph Myers writes: >> On Wed, 22 Jun 2016, Bill Schmidt wrote: >>> The fact that I hook this built-in directly to a pattern named infkf1 >>> doesn't seem to preclude anything

Re: [PATCH, rs6000] Add minimum __float128 built-in support required for glibc

Joseph Myers writes: > On Wed, 22 Jun 2016, Bill Schmidt wrote: >> The fact that I hook this built-in directly to a pattern named infkf1 >> doesn't seem to preclude anything you suggest. I named it this way >> on the off-chance that inf1 becomes a standard pattern in the

-fopt-info handling

The manual says about -fop-info: If OPTIONS is omitted, it defaults to 'all-all', which means dump all available optimization info from all the passes. The current implementation (at at least recent gcc 6.1) don't follow that, though. They just ignore the option in that case. How about

Ping Re: Implement C _FloatN, _FloatNx types [version 3]

Ping. This patch is pending review. Built-in functions are available in the followup patch . -- Joseph S. Myers jos...@codesourcery.com

Re: [PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions

Hi Ramana, On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: > > From here down to > > > -#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \ > > -|| defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ > > -|| defined(__ARM_ARCH_5TEJ__) > > -#define

Re: [PATCH, PR middle-end/71488] Fix vectorization of comparison of booleans

Looks like it caused PR71655 and therefore is not so safe :/ Ilya 2016-06-22 17:00 GMT+03:00 Ilya Enkovich : > 2016-06-21 23:57 GMT+03:00 Jeff Law : >> On 06/16/2016 05:06 AM, Ilya Enkovich wrote: >>> >>> Hi, >>> >>> This patch fixes incorrect comparison

Re: [Patch, lra] PR70751, correct the cost for spilling non-pseudo into memory

On Thu, Jun 09, 2016 at 09:52:39AM -0600, Jeff Law wrote: > On 06/08/2016 10:47 AM, Jiong Wang wrote: > >As discussed on the PR > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70751, > > > >here is the patch. This commit has introduced an ICE with s390x, march=z13. Is it a backend bug or

Re: [PATCH, libgcc/ARM 1a/6, ping] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions

Ping? Best regards, Thomas On Friday 17 June 2016 18:21:44 Thomas Preudhomme wrote: > On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: > > Please fix up the macros, post back and redo the test. Otherwise this > > is ok from a quick read. > > What about the updated patch in

[PATCH, obvious] Update comments for several vectorizator functions

Hi, This patch adds args description for some vectorizer functions. I'm going to commit it to trunk. Thanks, Ilya -- gcc/ 2016-06-27 Ilya Enkovich * tree-vect-loop-manip.c (vect_update_ivs_after_vectorizer): Update comment.

Re: [AArch64] ARMv8.2 command line and feature macros support

On 07/06/16 09:46, Jiong Wang wrote: 2016-06-07 Matthew Wahab Jiong Wang * config/aarch64/aarch64-arches.def: Add "armv8.2-a". * config/aarch64/aarch64.h (AARCH64_FL_V8_2): New. (AARCH64_FL_F16): New.

Re: [PATCH, rs6000] Scheduling update

On 06/22/2016 02:10 PM, Segher Boessenkool wrote: > The "power9_alu2" attribute is writing part of the scheduling description > inside the machine description proper. Can this be reduced, maybe by > adding an attribute describing something about the insns that makes them > be handled by the alu2?

Determine more IVs to be non-overflowing

Hi, this patch makes simple_iv to determine more often that IV can not overflow. First I commonized the logic in simple_iv with nowrap_type_p because it tests the same. Second I added iv_can_overflow_p which uses known upper bound on number of iteration to see if the IV calculation can overflow.

Re: RFC (attributes): PATCH for c++/50800 to set affects_type_identity for may_alias

On Thu, Jun 23, 2016 at 9:39 PM, Jason Merrill wrote: > My earlier patch for 50800 fixed the ICE by consistently stripping > non-mangled attributes from template arguments, and mangling those that > affect type identity. At the C++ meeting this week someone pointed out to > me

Re: Fix zero size debug array swap noexcept qualification

On 23/06/16 22:22 +0200, François Dumont wrote: Debug mode array had simply been forgotten when fixing zero-size swap method as part of swappable traits implementation. * include/debug/array (array<>::swap): Fix noexcept qualificaton for zero-size array. Tested under Linux x86_64

[PATCH] remove unused CTOR_LISTS_DEFINED_EXTERNALLY macro

From: Trevor Saunders Hi, The last target to use this was i386-interix, so since that is gone we don't need this anymore. bootstrapped and regtested on x86-linux-gnu, ok? Trev libgcc/ChangeLog: 2016-06-27 Trevor Saunders *

[PATCH, CHKP, PR ipa/71624] Fix local.can_change_signature computation for instrumentation thunk callees

Hi, This patch sets local.can_change_signature to false for instrumentation thunk callees. We have two reasons for that: - We don't support modification of instrumentation thunks - We don't actually emit instrumentation thunk and therefore its signature should be in sync with callee This

Re: [patch, avr,wwwdocs] PR 58655

Ping! On Wednesday 22 June 2016 12:05 PM, Pitchumani Sivanupandi wrote: On Tuesday 21 June 2016 09:39 PM, Georg-Johann Lay wrote: Pitchumani Sivanupandi schrieb: Attached patches add documentation for -mfract-convert-truncate option and add that info to release notes (gcc-4.9 changes). If

Re: RFC (attributes): PATCH for c++/50800 to set affects_type_identity for may_alias

On 06/23/2016 09:39 PM, Jason Merrill wrote: -/* { dg-final { scan-assembler "_ZN1AIdEC1Ev" } } */ +/* { dg-final { scan-assembler "_ZN1AIU9may_aliasdEC1Ev" } } */ I find this rather worrying. In glibc, we want to use the may_alias attribute on struct sockaddr_storage for POSIX conformance.

Re: [ARM][testsuite] Add missing guards to fp16 AdvSIMD tests

On 21/06/16 09:45, Christophe Lyon wrote: Hi, I've noticed that some guards were missing on some of the AdvSIMD tests involving fp16 code. The attached patch fixes, although I didn't notice any difference in validation: I have no configuration where check_effective_target_arm_neon_fp16_ok

Re: [ARM][testsuite] neon-testgen.ml removal

ping? On 22 June 2016 at 17:52, Christophe Lyon wrote: > Hi, > > This is a new attempt at removing neon-testgen.ml and generated files. > > Compared to my previous version several months ago: > - I have recently added testcases to make sure we do not lose coverage >

Re: [ARM][testsuite] Add missing guards to fp16 AdvSIMD tests

ping? On 21 June 2016 at 10:45, Christophe Lyon wrote: > Hi, > > I've noticed that some guards were missing on some of the AdvSIMD > tests involving fp16 code. > > The attached patch fixes, although I didn't notice any difference in > validation: I have no

[ARM] FP16 ARM Alternative format variants of AAPCS tests.

Hello, Tests added for FP16 argument and return values being passed in registers only check the case when the FP16 IEEE format is used. This patch adds equivalent tests that also check the behaviour when the ARM Alternative format is used. This patch depends on the testsuite directives added

Re: [ARM] Fix, add tests for FP16 aapcs.

On 10/06/16 15:30, Matthew Wahab wrote: > On 10/06/16 15:22, Christophe Lyon wrote: >> On 10 June 2016 at 15:56, Matthew Wahab wrote: >>> On 10/06/16 09:32, Christophe Lyon wrote: On 9 June 2016 at 17:21, Matthew Wahab wrote:

Re: [PATCH] Allow fwprop to undo vectorization harm (PR68961)

On Wed, 15 Jun 2016, Richard Sandiford wrote: > Richard Biener writes: > > With the proposed cost change for vector construction we will end up > > vectorizing the testcase in PR68961 again (on x86_64 and likely > > on ppc64le as well after that target gets adjustments).

Re: [PATCH] Backport PowerPC complex __float128 compiler support to GCC 6.x

On Wed, 22 Jun 2016, Michael Meissner wrote: > On Wed, Jun 15, 2016 at 11:01:05AM +0200, Richard Biener wrote: > > And I don't understand the layout_type change either - it looks to me > > it could just have used > > > > SET_TYPE_MODE (type, GET_MODE_COMPLEX_MODE (TYPE_MODE > > (TREE_TYPE

Re: Fix for PR70926 in Libiberty Demangler (5)

Hi Jeff, On 23 Jun 2016, at 4:21 AM, Jeff Law wrote: > > OK for the trunk. Please install. > > Sorry for the delays. > > Jeff I might not have the access rights to commit to trunk. Best regards - Marcel