On Mon, Dec 18, 2023 at 11:44:22AM +0800, YunQiang Su wrote:
> For reconcat, if the `optr` can only be used as the last one
> of string list, aka, we cannot append something to it.
> Let's add some note into the document.
>
> libiberty:
> * concat.c (reconcat): Add note about append string
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, December 18, 2023 3:37 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Bugfix for the RVV const vector
OK. LGTM. It's an obvious fix and not easy to add the test
Hi Jeff,
Sorry for this missing.
I've removed riscv_asm_output_pool_epilogue because the pool beginning is
always aligned from FUNCTION_BOUNDARY.
Please find attached. Thank you.
Jeff Law 於 2023年12月18日 週一 上午3:15寫道：
>
>
> On 11/10/23 02:10, KuanLin Chen wrote:
> > Sorry. It missed a semicolon
OK. LGTM. It's an obvious fix and not easy to add the test (No need to add such
test).
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-12-18 15:35
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for the RVV const vector
From: Pan Li
From: Pan Li
This patch would like to fix one bug of const vector for interleave.
Assume we need to generate interleave const vector like below.
V = {{4, -4, 3, -3, 2, -2, 1, -1,}
Before this patch:
vsetvl a3, zero, e64, m8, ta, ma
vid.v v8v8 = {0, 1, 2, 3, 4}
li
The fix is reasonable.
But the test ASM check is too fragile which will easily break in the feature.
The key of the check should be:
vid.v v8 -> can be v0, v8, v16, v24 since LMUL = 8
vadd.vi v8, v8, -4 -> should be using the result of vid.
I think you should adjust test check
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-18 15:05
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] testsuite: Fix cpymem-1.c dump checks under different
riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
*
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 29 +--
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
From: Pan Li
This patch would like to fix one bug of const vector for interleave.
Assume we need to generate interleave const vector like below.
V = {{4, -4, 3, -3, 2, -2, 1, -1,}
Before this patch:
vsetvl a3, zero, e64, m8, ta, ma
vid.v v8v8 = {0, 1, 2, 3, 4}
li
After recent fixes, almost all real FAILs on RV64 full coverage testing are
fixed.
So, it's reasonable to start test RV32 vect testing now.
We will enable full coverage testing RV32 soon and to see what else need to be
fixed.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Enable
Could you add -fno-schedule-insns -fno-schedule-insns2 ?
So that the test won't be fragile to break a again when we tune the scheduling
model and cost model.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-18 14:40
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH]
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
LGTM from my side.
Give kito 1 day to chime in,
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-18 11:28
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Add required_extensions in function_group
In order to add other vector related extensions in
For reconcat, if the `optr` can only be used as the last one
of string list, aka, we cannot append something to it.
Let's add some note into the document.
libiberty:
* concat.c (reconcat): Add note about append string to NULL
into document.
---
libiberty/concat.c | 3 +++
1 file
The function `reconcat` cannot append string(s) to NULL,
as the concat process will stop at the first NULL.
Let's initialize `ret` with `concat (" ", NULL)`, then
it can be used by reconcat.
gcc/
PR target/112759
* config/mips/driver-native.cc (host_detect_local_cpu):
In order to add other vector related extensions in the future, this
patch add one more parameter in the function_group_info, it will be
used to determine whether intrinsic registration processing is required.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def
This patch fixes 12 ICEs of "full coverage" testing:
Running target
riscv-sim/-march=rv64gc_zve32f/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/torture/pr96513.c -O3 -fomit-frame-pointer -funroll-loops
-fpeel-loops
Hi,
This patch cleans up pre-checkings of expand_block_compare. It does
1. Assert only P7 above can enter this function as it's already guard
by the expand.
2. Return false when optimizing for size.
3. Remove P7 processor test as only P7 above can enter this function and
P7 LE is excluded by
Hi,
The patch corrects the definition of
TARGET_EFFICIENT_OVERLAPPING_UNALIGNED and replace it with the call of
slow_unaligned_access.
Compared with last version,
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640076.html
the main change is to replace the macro with
Pushed to r14-6648 r14-6649 and r14-6650.
Thanks.
在 2023/12/8 下午6:09, Yang Yujie 写道:
This patchset is based on Zixing Liu's initial support patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631260.html
Updates
v1 -> v2: Rebased onto the dmd/druntime upstream state.
v2 -> v3:
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zhong
Date: 2023-12-18 09:08
To: Li Xu
CC: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com
Subject: Re: [PATCH] RISC-V: Add viota missed avl_type attribute
lgtm
Replied Message
FromLi Xu
Date12/18/2023
On 2023/12/14 03:35, Kees Cook wrote:
> On Wed, Dec 13, 2023 at 05:01:07PM +0800, Wang wrote:
>> On 2023/12/13 16:48, Dan Li wrote:
>>> + Likun
>>>
>>> On Tue, 28 Mar 2023 at 06:18, Sami Tolvanen wrote:
On Mon, Mar 27, 2023 at 2:30 AM Peter Zijlstra
wrote:
> On Sat, Mar 25, 2023
lgtm Replied Message FromLi XuDate12/18/2023 09:04 Togcc-patches@gcc.gnu.org Cckito.ch...@gmail.com,pal...@dabbelt.com,juzhe.zh...@rivai.aiSubject[PATCH] RISC-V: Add viota missed avl_type attribute
On 2023/12/13 22:45, Mark Rutland wrote:
> On Wed, Dec 13, 2023 at 05:01:07PM +0800, Wang wrote:
>> On 2023/12/13 16:48, Dan Li wrote:
>>> + Likun
>>>
>>> On Tue, 28 Mar 2023 at 06:18, Sami Tolvanen wrote:
On Mon, Mar 27, 2023 at 2:30 AM Peter Zijlstra wrote:
> On Sat, Mar 25, 2023 at
From: Juzhe-Zhong
This patch fixes the following FAIL when LMUL = 8:
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medany/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=scalable
FAIL: gcc.dg/vect/slp-multitypes-2.c execution test
The rootcause is we missed viota avl_type, so we
lgtm. Replied Message Frompan2...@intel.comDate12/18/2023 08:22 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Fix POLY INT handle bug
From: Pan Li
This patch fixes the following FAIL:
Running target
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
FAIL: gcc.dg/vect/fast-math-vect-complex-3.c execution test
The root cause is we generate incorrect codegen for (const_poly_int:DI
[549755813888,
On Sun, 17 Dec 2023 at 15:38, Florian Weimer wrote:
>
> This matches other compiler diagnostics. No test updates are needed
> because c-c++-common/pr95378.c does not match a specific -W option.
>
> Fixes commit d2384b7b24f8557b66f6958a05ea99ff4307e75c ("c-family:
> check qualifiers of arguments
Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
An alternative approach for the lambda issue would be to modify
'maybe_add_lambda_conv_op' to not pass a null pointer, but I wasn't sure
what the best approach for that would be.
-- >8 --
Calling a non-static member function on a
On 11/10/23 02:10, KuanLin Chen wrote:
Sorry. It missed a semicolon in the previos patch. Please find the new
one in the attachment. Thanks.
Thanks. I was going to do some final testing with the plan to integrate
this patch today, but I think there's a piece missing. Specifically I
think
With the change to use enumerators instead of strings to represent
context selector and selector-set names, the default tree-list output
for dumping selectors is less helpful for debugging and harder to use
in test cases. This patch adds support for dumping context selectors
using syntax similar
This patch introduces enumerators to represent trait-set names and
trait names, which makes it easier to use tables to control other
behavior and for switch statements to dispatch on the tags. The tags
are stored in the same place in the TREE_LIST structure (OMP_TSS_ID or
OMP_TS_ID) and are
On 12/12/23 05:05, Tobias Burnus wrote:
Hi Sandra,
On 07.12.23 16:52, Sandra Loosemore wrote:
This patch introduces enumerators to represent trait-set names and
trait names, which makes it easier to use tables to control other
behavior and for switch statements to dispatch on the tags. The
Support for constructing composite types for structs and unions
in C23.
gcc/c:
* c-typeck.cc (composite_type_internal): Adapted from
composite_type to support structs and unions.
(composite_type): New wrapper function.
(build_conditional_operator): Return
Tell the backend which types are equivalent by setting
TYPE_CANONICAL to one struct in the set of equivalent
structs. Structs are considered equivalent by ignoring
all sizes of arrays nested in types below field level.
The following two structs are incompatible and lvalues
with these types
Allow redefinition of enum types and enumerators. Diagnose
nested redefinitions including redefinitions in the enum
specifier for enum types with fixed underlying type.
gcc/c:
* c-tree.h (c_parser_enum_specifier): Add parameter.
* c-decl.cc (start_enum): Allow redefinition.
Here is the revised series. The first three patches only
have changes in the tests as well as the return value
changes. The fourth patch was now also revised,
with changes and tests to make sure that the composite
type works correctly for bit-fields, anonymous structs/unions,
alignment,
Hi Harald,
It might be a simple patch but I have to confess it took a while for me to
get my head around the difference between gfc_is_not_contiguous and
!gfc_is_simply_contigous :-(
Yes, this is OK for mainline and, after a short delay, for 13-branch.
Thanks for the patch
Paul
On Sat, 16
This matches other compiler diagnostics. No test updates are needed
because c-c++-common/pr95378.c does not match a specific -W option.
Fixes commit d2384b7b24f8557b66f6958a05ea99ff4307e75c ("c-family:
check qualifiers of arguments to __atomic built-ins (PR 95378)").
gcc/c-family/
PR
On Sun, 2023-12-10 at 01:03 +0800, Xi Ruoyao wrote:
> Update LoongArch instruction costs based on the micro-benchmark results
> on LA464 and LA664. In particular, this allows generating alsl/slli or
> alsl/slli + add pairs for multiplying some constants as on LA464/LA664
> a mul instruction is 4x
Remove a redundant sign extension.
gcc/ChangeLog:
* config/loongarch/loongarch.md (rotrsi3_extend): New
define_insn.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/rotrw.c: New test.
---
Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk?
We had the following mappings between vfcmp submenmonics and RTX
codes:
(define_code_attr fcc
[(unordered "cun")
(ordered "cor")
(eq "ceq")
(ne "cne")
(uneq "cueq")
(unle "cule")
(unlt "cult")
(le "cle")
On 2023-12-17 2:28 a.m., Gerald Pfeifer wrote:
Hi Dave,
based on our earlier e-mail, I understand we don't support hppa*-hp-hpux10
any longer, so let's remove them from the installation docs.
On the way remove references to GCC 2.95 and 3.0 from hppa*-hp-hpux11.
Okay?
The sentence about
Hello Thomas,
> -Original Message-
> From: Thomas Schwinge
> Sent: Friday, December 15, 2023 5:46 PM
> To: Di Zhao OS ; gcc-patches@gcc.gnu.org
> Cc: Richard Biener
> Subject: RE: [PATCH v4] [tree-optimization/110279] Consider FMA in
> get_reassociation_width
>
> Hi!
>
> On
> Am 17.12.2023 um 04:29 schrieb Jeff Law :
>
>
> So mcore-elf is the slowest target to test with a simulator. Not because
> it's simulator is particularly bad, but because some tests timeout as they've
> gotten into infinite loops. This causes the mcore-elf port to take about 2X
>
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