Re: [testsuite, i386] Fix for PR50185
Hi, This is a ping. Is the patch ok for trunk? Thanks, K On Fri, Aug 26, 2011 at 5:52 PM, H.J. Lu hjl.to...@gmail.com wrote: On Fri, Aug 26, 2011 at 6:45 AM, Kirill Yukhin kirill.yuk...@gmail.com wrote: Hi guys, Thanks for your objections. HJ, I scanned all AVX2 tests. So, every tests has at least tab which distinguishes it from filename: $ pwd /export/users/kyukhin/ws/gcc/gcc/testsuite/gcc.target/i386 $ grep scan-assembler avx2-* |grep -v \t |wc -l 0 Uros, you're right. Patch contains usless file. Updated one is attached. Thanks, K On Fri, Aug 26, 2011 at 5:04 PM, H.J. Lu hjl.to...@gmail.com wrote: On Fri, Aug 26, 2011 at 5:04 AM, Kirill Yukhin kirill.yuk...@gmail.com wrote: According to Jakub's input, I've updated test to scan instruction, not pattern name. Is it ok? Thanks, K On Fri, Aug 26, 2011 at 3:45 PM, Kirill Yukhin kirill.yuk...@gmail.com wrote: Hi, Here is a fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50182 testsuite/ChangeLog entry: 2011-08-26 Kirill Yukhin kirill.yuk...@intel.com PR testsuite/50185 * gcc.target/i386/avx2-vmovmskb-2.c: Rename to ... * gcc.target/i386/avx2-vpmovmskb-2.c: ... this. Update. Test passes. Ok for trunk? Thanks, K Please check ALL AVX2 tests to see if they have similar problems. Thanks. -- H.J.
Re: [PATCH] Fix Ada bootstrap
The following patch fixed the bootstrap for me, will commit it as obvious once also regtesting finishes. 2011-08-29 Jakub Jelinek ja...@redhat.com * gcc-interface/Makefile.in (../stamp-gnatlib1-$(RTSDIR)): Copy tsystem.h into $(RTSDIR) instead of rts. Patch is certainly fine, thanks for looking into it, and sorry for the breakage. Arno
Re: [PATCH, committed] Change default for powerpc -msave-toc-indirect
On Mon, Aug 29, 2011 at 11:32 PM, Michael Meissner
meiss...@linux.vnet.ibm.com wrote:
David asked me to reverse the default for the -msave-toc-indirect option,
since
it is buggy in a few cases, and in other places causes slowdowns if the
function has an early exit before calling the indrect function. I also
documented the switch.
I did the usual bootstrap and make check with no regressions, and committed
the
patch.
Was this switch available in 4.6.x? If so please document the change of the
default in gcc-4.7/changes.html.
Thanks,
Richard.
2011-08-29 Michael Meissner meiss...@linux.vnet.ibm.com
* config/rs6000/rs6000.opt (-msave-toc-indirect): Change default
to off. Document switch.
* doc/invoke.texi (-msave-toc-indirect): Ditto.
Index: gcc/config/rs6000/rs6000.opt
===
--- gcc/config/rs6000/rs6000.opt (revision 178259)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -526,5 +526,5 @@ Target Report Var(TARGET_POINTERS_TO_NES
Use/do not use r11 to hold the static link in calls to functions via
pointers.
msave-toc-indirect
-Target Undocumented Var(TARGET_SAVE_TOC_INDIRECT) Save Init(1)
-; Control whether we save the TOC in the prologue for indirect calls or
generate the save inline
+Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save
+Control whether we save the TOC in the prologue for indirect calls or
generate the save inline
Index: gcc/doc/invoke.texi
===
--- gcc/doc/invoke.texi (revision 178259)
+++ gcc/doc/invoke.texi (working copy)
@@ -814,7 +814,8 @@ See RS/6000 and PowerPC Options.
-mrecip -mrecip=@var{opt} -mno-recip -mrecip-precision @gol
-mno-recip-precision @gol
-mveclibabi=@var{type} -mfriz -mno-friz @gol
--mpointers-to-nested-functions -mno-pointers-to-nested-functions}
+-mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol
+-msave-toc-indirect -mno-save-toc-indirect}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
@@ -16438,6 +16439,15 @@ static chain value to be loaded in regis
not be able to call through pointers to nested functions or pointers
to functions compiled in other languages that use the static chain if
you use the @option{-mno-pointers-to-nested-functions}.
+
+@item -msave-toc-indirect
+@itemx -mno-save-toc-indirect
+@opindex msave-toc-indirect
+Generate (do not generate) code to save the TOC value in the reserved
+stack location in the function prologue if the function calls through
+a pointer on AIX and 64-bit Linux systems. If the TOC value is not
+saved in the prologue, it is saved just before the call through the
+pointer. The @option{-mno-save-toc-indirect} option is the default.
@end table
@node RX Options
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Mon, Aug 29, 2011 at 9:44 PM, Richard Guenther rguent...@suse.de wrote:
This patch makes a conversion optab from the direct optabs vcond
and vcondu. This allows to specify different modes for the
actual comparison and the value that is selected.
All targets but i386 are trivially converted by
s/vcondmode/vcondmodemode/. The i386 port is enhanced
to support a OP b ? c : d as ({ mask = a OP b; (c mask) | (d ~mask);
}), constraining it to what the middle-end constrained itself to
(matching number of vector elements in the comparison operands with
the result vector types) would explode patterns too much.
Thus, only a subset of mode combinations will be excercised
(but none at the moment - a followup will fix the vectorizer,
and generic vectors from the C extensions have a patch pending).
Bootstrapped on x86_64-unknown-linux-gnu, tests are currently
running for {,-m32}.
Ok if that succeeds?
Thanks,
Richard.
2011-08-29 Richard Guenther rguent...@suse.de
* genopinit.c (optabs): Turn vcond{,u}_optab into a conversion
optab with two modes.
* optabs.h (enum convert_optab_index): Add COI_vcond, COI_vcondu.
(enum direct_optab_index): Remove DOI_vcond, DOI_vcondu.
(vcond_optab): Adjust.
(vcondu_optab): Likewise.
(expand_vec_cond_expr_p): Adjust prototype.
* optabs.c (get_vcond_icode): Adjust.
(expand_vec_cond_expr_p): Likewise.
(expand_vec_cond_expr): Likewise.
* tree-vect-stmt.c (vectorizable_condition): Adjust.
* config/i386/sse.md (vcondmode): Split to
vcondV_256:modeVF_256:mode, vcondV_128:modeVF_128:mode,
vcondV_128:modeVI124_128:mode and
vconduV_128:modeVI124_128:mode.
(vcondv2di): Change to vcondVI8F_128:modev2di.
(vconduv2di): Likewise.
* config/arm/neon.md (vcondmode): Change to vcond*modemode.
(vcondumode): Likewise.
* config/ia64/vect.md (vcondmode): Likewise.
(vcondumode): Likewise.
(vcondv2sf): Likewise.
* config/mips/mips-ps-3d.md (vcondv2sf): Likewise.
* config/rs6000/paired.md (vcondv2sf): Likewise.
* config/rs6000/vector.md (vcondmode): Likewise.
(vcondumode): Likewise.
* config/spu/spu.md (vcondmode): Likewise.
(vcondumode): Likewise.
Do we really want to introduce stuff like:
! (define_expand vcondV_128:modeVF_128:mode
You are in fact introducing 6x2 = 12 patterns, many of them (i.e.
v16qiv2df combination) invalid.
Well, in principle they are not invalid they would be a short-hand -
the example of (subreg:V16QI (vcond:V2DI (... )).
I'd prefer a pattern with mode-less operands 4 and 5, rejected in insn
constraints for invalid combinations:
Hm, ok - that was the first variant I tried (well, but with modeless
operands 1 and 2, to keep 4 and 5 selcting int vs. fp compare). But
modeless operands get you that annoying warning from the gen* programs.
Only for define_insn, if your c_test does not include string operands.
How'd you ask if a pattern is available for vcondv4si with v4sf
operands 4 and 5? The vectorizer would need to be able to ask this
question.
Maybe with something along the lines of:
(define_expand vcondmode
[(set (match_operand:VI124_128 0 register_operand )
(if_then_else:VI124_128
(match_operator 3
[(match_operand 4 nonimmediate_operand )
(match_operand 5 nonimmediate_operand )])
(match_operand:VI124_128 1 general_operand )
(match_operand:VI124_128 2 general_operand )))]
TARGET_SSE2
{
if (GET_MODE (operands[4]) != GET_MODE (operands[5])
|| (GET_MODE_NUNITS (GET_MODE (operands[4]))
!= GET_MODE_NUNITS (GET_MODE (operands[0]
FAIL;
bool ok = ix86_expand_int_vcond (operands);
gcc_assert (ok);
DONE;
})
This means that vcond pattern is allowed to FAIL, so when vectorizer
tentatively tries to expand the pattern, FAIL signalizes that operand
modes are not supported.
In the end putting both mask generation and apply into one
instruction pattern causes all this issues - but it helps
not exposing the mask representation of the HW.
No, but we should be sure that the widths are the same...
Uros.
Re: [PATCH, MELT, minor] add a primitive read_strv
Hello,
this is a ping for
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01503.html. I thought this
was integrated into MELT but it does not look to be in the current trunk.
It just add a primitive read_strv allowing to use meltgc_read_from_val
to get a list of s-expression from a boxed C string of a strbuf.
Pierre Vittet
Index: gcc/melt/warmelt-base.melt
===
--- gcc/melt/warmelt-base.melt (revision 176434)
+++ gcc/melt/warmelt-base.melt (working copy)
@@ -272,6 +272,11 @@ number $NUM opaque location number $LOC.}#
:doc #{Read from file named by the $FILNAM string balue a list of MELT
s-expressions.}#
#{(meltgc_read_file (melt_string_str((melt_ptr_t)($filnam)), (char*)0))}#)
+(defprimitive read_strv (strv) :value
+ :doc #{Return the list of sexpr contained in $STRV. $STRV can be a boxed
+ string or a strbuf value.}#
+ #{(meltgc_read_from_val ($strv, NULL))}#
+)
;; to signal an error in a source with some additional string value
(defprimitive error_strv (loc :cstring cmsg :value strv) :void
@@ -2441,6 +2446,7 @@ polyhedron values.}#
pair_set_head
ppstrbuf_mixbigint
read_file
+ read_strv
register_pass_execution_hook
register_pragma_handler
register_pre_genericize_hook
2011-07-18 Pierre Vittet pier...@pvittet.com
* melt/warmelt-base.melt (read_strv): New primitive.
Re: [PATCH 01/20] Make CLooG-ISL the only supported CLooG version.
On 08/29/2011 04:01 PM, Joseph S. Myers wrote: I looked at the ISL sources and saw that they generally had license notices of the form: * Use of this software is governed by the GNU LGPLv2.1 license Hi Joseph, at least according to a license compatibility chart[1] published by the FSF, it is OK to combine a LGPLv2.1 only library with a GPLv3 project. Is there any reason the compatibility matrix published by the FSF might be outdated or may not apply to us, or do you think we can rely on this information? Cheers Tobi [1] http://gplv3.fsf.org/dd3-faq
Re: [testsuite, i386] Fix for PR50185
On Tue, Aug 30, 2011 at 8:39 AM, Kirill Yukhin kirill.yuk...@gmail.com wrote: Hi, This is a ping. Is the patch ok for trunk? OK. Thanks, Uros.
RE: [PATCH, testsuite] Avoid architecture options conflict for case pr42894.c
Ping.
BR,
Terry
-Original Message-
From: Terry Guo [mailto:terry@arm.com]
Sent: Thursday, August 25, 2011 7:46 PM
To: 'gcc-patches@gcc.gnu.org'
Subject: [PATCH, testsuite] Avoid architecture options conflict for
case pr42894.c
Hello,
I think it is useful to run this case for newer arm targets. So the
patch intends to skip the warning of architecture conflicts. Is it ok
to commit to trunk?
BR,
Terry
gcc/testsuite/ChangeLog:
2011-08-25 Terry Guo terry@arm.com
* gcc.dg/tls/pr42894.c: Add dg-prune-output to skip
architecture conflict.
diff --git a/gcc/testsuite/gcc.dg/tls/pr42894.c
b/gcc/testsuite/gcc.dg/tls/pr42894.c
index c3bd76c..cda6719 100644
--- a/gcc/testsuite/gcc.dg/tls/pr42894.c
+++ b/gcc/testsuite/gcc.dg/tls/pr42894.c
@@ -2,6 +2,7 @@
/* { dg-do compile } */
/* { dg-options -march=armv5te -mthumb { target arm*-*-* } } */
/* { dg-require-effective-target tls } */
+/* { dg-prune-output switch .* conflicts with } */
extern __thread int t;
Re: [Ada] Reimplement Ada.Numerics.Generic_Real_Arrays in pure Ada
Dear Arnaud, Arnaud Charlet wrote: +-- This version of Generic_Real_Arrays avoids the use of BLAS and LAPACK. One +-- reason for this is new Ada 2012 requirements that prohibit algorithms such +-- as Strassen's algorithm, which may be used by some BLAS implementations. In May I ask why Ada requirements prohibit algorithms such as Strassen's? Thanks, mqk -- View this message in context: http://old.nabble.com/-Ada--Reimplement-Ada.Numerics.Generic_Real_Arrays-in-pure-Ada-tp32356733p32362652.html Sent from the gcc - patches mailing list archive at Nabble.com.
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, 30 Aug 2011, Uros Bizjak wrote:
On Mon, Aug 29, 2011 at 9:44 PM, Richard Guenther rguent...@suse.de wrote:
This patch makes a conversion optab from the direct optabs vcond
and vcondu. This allows to specify different modes for the
actual comparison and the value that is selected.
All targets but i386 are trivially converted by
s/vcondmode/vcondmodemode/. The i386 port is enhanced
to support a OP b ? c : d as ({ mask = a OP b; (c mask) | (d ~mask);
}), constraining it to what the middle-end constrained itself to
(matching number of vector elements in the comparison operands with
the result vector types) would explode patterns too much.
Thus, only a subset of mode combinations will be excercised
(but none at the moment - a followup will fix the vectorizer,
and generic vectors from the C extensions have a patch pending).
Bootstrapped on x86_64-unknown-linux-gnu, tests are currently
running for {,-m32}.
Ok if that succeeds?
Thanks,
Richard.
2011-08-29 Richard Guenther rguent...@suse.de
* genopinit.c (optabs): Turn vcond{,u}_optab into a conversion
optab with two modes.
* optabs.h (enum convert_optab_index): Add COI_vcond, COI_vcondu.
(enum direct_optab_index): Remove DOI_vcond, DOI_vcondu.
(vcond_optab): Adjust.
(vcondu_optab): Likewise.
(expand_vec_cond_expr_p): Adjust prototype.
* optabs.c (get_vcond_icode): Adjust.
(expand_vec_cond_expr_p): Likewise.
(expand_vec_cond_expr): Likewise.
* tree-vect-stmt.c (vectorizable_condition): Adjust.
* config/i386/sse.md (vcondmode): Split to
vcondV_256:modeVF_256:mode, vcondV_128:modeVF_128:mode,
vcondV_128:modeVI124_128:mode and
vconduV_128:modeVI124_128:mode.
(vcondv2di): Change to vcondVI8F_128:modev2di.
(vconduv2di): Likewise.
* config/arm/neon.md (vcondmode): Change to vcond*modemode.
(vcondumode): Likewise.
* config/ia64/vect.md (vcondmode): Likewise.
(vcondumode): Likewise.
(vcondv2sf): Likewise.
* config/mips/mips-ps-3d.md (vcondv2sf): Likewise.
* config/rs6000/paired.md (vcondv2sf): Likewise.
* config/rs6000/vector.md (vcondmode): Likewise.
(vcondumode): Likewise.
* config/spu/spu.md (vcondmode): Likewise.
(vcondumode): Likewise.
Do we really want to introduce stuff like:
! (define_expand vcondV_128:modeVF_128:mode
You are in fact introducing 6x2 = 12 patterns, many of them (i.e.
v16qiv2df combination) invalid.
Well, in principle they are not invalid they would be a short-hand -
the example of (subreg:V16QI (vcond:V2DI (... )).
I'd prefer a pattern with mode-less operands 4 and 5, rejected in insn
constraints for invalid combinations:
Hm, ok - that was the first variant I tried (well, but with modeless
operands 1 and 2, to keep 4 and 5 selcting int vs. fp compare). But
modeless operands get you that annoying warning from the gen* programs.
Only for define_insn, if your c_test does not include string operands.
How'd you ask if a pattern is available for vcondv4si with v4sf
operands 4 and 5? The vectorizer would need to be able to ask this
question.
Maybe with something along the lines of:
(define_expand vcondmode
[(set (match_operand:VI124_128 0 register_operand )
(if_then_else:VI124_128
(match_operator 3
[(match_operand 4 nonimmediate_operand )
(match_operand 5 nonimmediate_operand )])
(match_operand:VI124_128 1 general_operand )
(match_operand:VI124_128 2 general_operand )))]
TARGET_SSE2
{
if (GET_MODE (operands[4]) != GET_MODE (operands[5])
|| (GET_MODE_NUNITS (GET_MODE (operands[4]))
!= GET_MODE_NUNITS (GET_MODE (operands[0]
FAIL;
bool ok = ix86_expand_int_vcond (operands);
gcc_assert (ok);
DONE;
})
This means that vcond pattern is allowed to FAIL, so when vectorizer
tentatively tries to expand the pattern, FAIL signalizes that operand
modes are not supported.
Hmm. But then I'd have to try emit an insn, right? Currently
the vectorizer simply looks for an optab handler ... the
operands are not readily available (but their mode is known).
So I'd create some fake regs, setup operands and call GEN_FCN
on it? If it succeds I'd have to delete emitted insns, etc.
Or I could add a target hook ...
That shifts the ugliness towards the users, for just saving
a few redundant patterns?
In the end putting both mask generation and apply into one
instruction pattern causes all this issues - but it helps
not exposing the mask representation of the HW.
No, but we should be sure that the widths are the same...
Yes. We'd guarantee that we'd never try to expand something
where that doesn't hold.
I just saw PR29269 - vcond is
[PATCH, MELT] add primitive isnull_tree
Hello,
This is a small patch adding primitive isnull_tree (as there is already
a primitive isnull_basicblock).
Pierre Vittet
Index: gcc/melt/xtramelt-ana-base.melt
===
--- gcc/melt/xtramelt-ana-base.melt (révision 178282)
+++ gcc/melt/xtramelt-ana-base.melt (copie de travail)
@@ -1447,12 +1447,15 @@
(defprimitive gimpleseq_content (v) :gimple_seq
#{(melt_gimpleseq_content((melt_ptr_t)($v)))}# )
+
-
-
(defprimitive is_tree (v) :long
#{(melt_magic_discr((melt_ptr_t)($v)) == MELTOBMAG_TREE)}# )
+(defprimitive isnull_tree (:tree tr) :long
+ #{$tr == (tree)0}#
+)
+
(defprimitive make_tree (discr :tree g) :value
#{(meltgc_new_tree((meltobject_ptr_t)($discr),($g)))}# )
@@ -3597,7 +3600,8 @@ and discriminant $DIS, usually $DISCR_MIXED_LOCATI
is_mapgimple
is_maploop
is_maptree
- is_tree
+ is_tree
+ isnull_tree
isnull_basicblock
loop_body_tuple
loop_can_be_parallel
2011-08-30 Pierre Vittet pier...@pvittet.com
* melt/xtramelt-ana-base.melt(isnull_tree): Add primitive.
Re: [patch libstdc++]: Add some missing errno-constants for mingw-targets
... I committed the below because what we have now cannot possibly be
right, can easily break the build. Please the target maintainers double
check the whole thing, test it.
Paolo.
//
2011-08-30 Paolo Carlini paolo.carl...@oracle.com
* config/os/mingw32/error_constants.h: Fix commas.
Index: config/os/mingw32/error_constants.h
===
--- config/os/mingw32/error_constants.h (revision 178284)
+++ config/os/mingw32/error_constants.h (working copy)
@@ -1,6 +1,6 @@
// Specific definitions for mingw32 platform -*- C++ -*-
-// Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+// Copyright (C) 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the
@@ -33,7 +33,6 @@
#include bits/c++config.h
#include cerrno
-
namespace std _GLIBCXX_VISIBILITY(default)
{
_GLIBCXX_BEGIN_NAMESPACE_VERSION
@@ -129,11 +128,12 @@
too_many_files_open_in_system = ENFILE,
too_many_files_open =EMFILE,
too_many_links = EMLINK
- // too_many_symbolic_link_levels = ELOOP,
+//too_many_symbolic_link_levels = ELOOP,
#ifdef _GLIBCXX_HAVE_EOVERFLOW
- value_too_large =EOVERFLOW,
+ ,
+ value_too_large =EOVERFLOW
#endif
- // wrong_protocol_type =EPROTOTYPE
+//wrong_protocol_type =EPROTOTYPE
};
_GLIBCXX_END_NAMESPACE_VERSION
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, Aug 30, 2011 at 10:50 AM, Richard Guenther rguent...@suse.de wrote:
Hm, ok - that was the first variant I tried (well, but with modeless
operands 1 and 2, to keep 4 and 5 selcting int vs. fp compare). But
modeless operands get you that annoying warning from the gen* programs.
Only for define_insn, if your c_test does not include string operands.
How'd you ask if a pattern is available for vcondv4si with v4sf
operands 4 and 5? The vectorizer would need to be able to ask this
question.
Maybe with something along the lines of:
(define_expand vcondmode
[(set (match_operand:VI124_128 0 register_operand )
(if_then_else:VI124_128
(match_operator 3
[(match_operand 4 nonimmediate_operand )
(match_operand 5 nonimmediate_operand )])
(match_operand:VI124_128 1 general_operand )
(match_operand:VI124_128 2 general_operand )))]
TARGET_SSE2
{
if (GET_MODE (operands[4]) != GET_MODE (operands[5])
|| (GET_MODE_NUNITS (GET_MODE (operands[4]))
!= GET_MODE_NUNITS (GET_MODE (operands[0]
FAIL;
bool ok = ix86_expand_int_vcond (operands);
gcc_assert (ok);
DONE;
})
This means that vcond pattern is allowed to FAIL, so when vectorizer
tentatively tries to expand the pattern, FAIL signalizes that operand
modes are not supported.
Hmm. But then I'd have to try emit an insn, right? Currently
the vectorizer simply looks for an optab handler ... the
operands are not readily available (but their mode is known).
So I'd create some fake regs, setup operands and call GEN_FCN
on it? If it succeds I'd have to delete emitted insns, etc.
Or I could add a target hook ...
Hm... indeed, too much complication...
I'd say, let's go with modeless operands and a target hook. IMO, this
is much more flexible than checking optab for supported modes.
Existing way is appropriate for single mode patterns, but we have
interdependent modes here, at least on x86.
The hook would have two input arguments, insn mode and compare mode,
where the hook returns suggested supported compare mode, or no mode,
if it really can't handle requested modes.
That shifts the ugliness towards the users, for just saving
a few redundant patterns?
I think that hook solves this in the most elegant way.
Uros.
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, Aug 30, 2011 at 11:02:02AM +0200, Uros Bizjak wrote: Hmm. But then I'd have to try emit an insn, right? Currently the vectorizer simply looks for an optab handler ... the operands are not readily available (but their mode is known). So I'd create some fake regs, setup operands and call GEN_FCN on it? If it succeds I'd have to delete emitted insns, etc. Or I could add a target hook ... Hm... indeed, too much complication... I'd say, let's go with modeless operands and a target hook. IMO, this is much more flexible than checking optab for supported modes. Existing way is appropriate for single mode patterns, but we have interdependent modes here, at least on x86. The hook would have two input arguments, insn mode and compare mode, where the hook returns suggested supported compare mode, or no mode, if it really can't handle requested modes. I think a two mode vcond pattern is in fact much cleaner than a one mode + modeless pattern which gen* will complain about and a target hook. Jakub
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, 30 Aug 2011, Jakub Jelinek wrote: On Tue, Aug 30, 2011 at 11:02:02AM +0200, Uros Bizjak wrote: Hmm. But then I'd have to try emit an insn, right? Currently the vectorizer simply looks for an optab handler ... the operands are not readily available (but their mode is known). So I'd create some fake regs, setup operands and call GEN_FCN on it? If it succeds I'd have to delete emitted insns, etc. Or I could add a target hook ... Hm... indeed, too much complication... I'd say, let's go with modeless operands and a target hook. IMO, this is much more flexible than checking optab for supported modes. Existing way is appropriate for single mode patterns, but we have interdependent modes here, at least on x86. The hook would have two input arguments, insn mode and compare mode, where the hook returns suggested supported compare mode, or no mode, if it really can't handle requested modes. I think a two mode vcond pattern is in fact much cleaner than a one mode + modeless pattern which gen* will complain about and a target hook. Btw, what I meant with lumping together two insns in vcond is that it is really a combination of vcreatecondmaskmode where mode is the comparison and mask mode, a convert-move and a vapplycondmaskmode where the mode is now the mode of the values and the converted mask. But that would of course make it difficult for targets with vector condition codes to support vcond. Richard.
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, Aug 30, 2011 at 11:07 AM, Jakub Jelinek ja...@redhat.com wrote: On Tue, Aug 30, 2011 at 11:02:02AM +0200, Uros Bizjak wrote: Hmm. But then I'd have to try emit an insn, right? Currently the vectorizer simply looks for an optab handler ... the operands are not readily available (but their mode is known). So I'd create some fake regs, setup operands and call GEN_FCN on it? If it succeds I'd have to delete emitted insns, etc. Or I could add a target hook ... Hm... indeed, too much complication... I'd say, let's go with modeless operands and a target hook. IMO, this is much more flexible than checking optab for supported modes. Existing way is appropriate for single mode patterns, but we have interdependent modes here, at least on x86. The hook would have two input arguments, insn mode and compare mode, where the hook returns suggested supported compare mode, or no mode, if it really can't handle requested modes. I think a two mode vcond pattern is in fact much cleaner than a one mode + modeless pattern which gen* will complain about and a target hook. OK, but in this case, do not use mode iterators too much in order to avoid invalid patterns. Uros.
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, 30 Aug 2011, Uros Bizjak wrote: On Tue, Aug 30, 2011 at 11:07 AM, Jakub Jelinek ja...@redhat.com wrote: On Tue, Aug 30, 2011 at 11:02:02AM +0200, Uros Bizjak wrote: Hmm. But then I'd have to try emit an insn, right? Currently the vectorizer simply looks for an optab handler ... the operands are not readily available (but their mode is known). So I'd create some fake regs, setup operands and call GEN_FCN on it? If it succeds I'd have to delete emitted insns, etc. Or I could add a target hook ... Hm... indeed, too much complication... I'd say, let's go with modeless operands and a target hook. IMO, this is much more flexible than checking optab for supported modes. Existing way is appropriate for single mode patterns, but we have interdependent modes here, at least on x86. The hook would have two input arguments, insn mode and compare mode, where the hook returns suggested supported compare mode, or no mode, if it really can't handle requested modes. I think a two mode vcond pattern is in fact much cleaner than a one mode + modeless pattern which gen* will complain about and a target hook. OK, but in this case, do not use mode iterators too much in order to avoid invalid patterns. I don't see them as invalid. They will be unused (maybe combine would create them though?), but they have well-defined semantics with my proposed documentation. And x86 can handle them just fine. Richard.
Re: [patch libstdc++]: Add some missing errno-constants for mingw-targets
Hi Pedro, The update of copyright date is ok. The rest of the patch doesn't look right. Why you have here a stray comma? Why you remove here leading spaces for comments? Kai 2011/8/30 Paolo Carlini paolo.carl...@oracle.com: ... I committed the below because what we have now cannot possibly be right, can easily break the build. Please the target maintainers double check the whole thing, test it. Paolo. // -- | (\_/) This is Bunny. Copy and paste | (='.'=) Bunny into your signature to help | ()_() him gain world domination
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, Aug 30, 2011 at 11:15 AM, Richard Guenther rguent...@suse.de wrote: Hmm. But then I'd have to try emit an insn, right? Currently the vectorizer simply looks for an optab handler ... the operands are not readily available (but their mode is known). So I'd create some fake regs, setup operands and call GEN_FCN on it? If it succeds I'd have to delete emitted insns, etc. Or I could add a target hook ... Hm... indeed, too much complication... I'd say, let's go with modeless operands and a target hook. IMO, this is much more flexible than checking optab for supported modes. Existing way is appropriate for single mode patterns, but we have interdependent modes here, at least on x86. The hook would have two input arguments, insn mode and compare mode, where the hook returns suggested supported compare mode, or no mode, if it really can't handle requested modes. I think a two mode vcond pattern is in fact much cleaner than a one mode + modeless pattern which gen* will complain about and a target hook. OK, but in this case, do not use mode iterators too much in order to avoid invalid patterns. I don't see them as invalid. They will be unused (maybe combine would create them though?), but they have well-defined semantics with my proposed documentation. And x86 can handle them just fine. OK, let's go this way then... We can clean up this later if at all. Uros.
Re: [patch libstdc++]: Add some missing errno-constants for mingw-targets
On 08/30/2011 11:18 AM, Kai Tietz wrote: Hi Pedro, Paolo The update of copyright date is ok. The rest of the patch doesn't look right. Why you have here a stray comma? Actually, *you* had wrong commas. Look closer. Paolo.
Re: [patch libstdc++]: Add some missing errno-constants for mingw-targets
2011/8/30 Paolo Carlini paolo.carl...@oracle.com: On 08/30/2011 11:18 AM, Kai Tietz wrote: Hi Pedro, Paolo The update of copyright date is ok. The rest of the patch doesn't look right. Why you have here a stray comma? Actually, *you* had wrong commas. Look closer. Paolo. Yes, saw it now. Thanks for catching it. Is ok. Thanks, Kai
Re: [testsuite, i386] Fix for PR50185
Thank you! Guys who is able to write, could you please check-in my changes? K On Tue, Aug 30, 2011 at 12:12 PM, Uros Bizjak ubiz...@gmail.com wrote: On Tue, Aug 30, 2011 at 8:39 AM, Kirill Yukhin kirill.yuk...@gmail.com wrote: Hi, This is a ping. Is the patch ok for trunk? OK. Thanks, Uros.
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, 30 Aug 2011, Uros Bizjak wrote:
On Tue, Aug 30, 2011 at 11:15 AM, Richard Guenther rguent...@suse.de wrote:
Hmm. But then I'd have to try emit an insn, right? Currently
the vectorizer simply looks for an optab handler ... the
operands are not readily available (but their mode is known).
So I'd create some fake regs, setup operands and call GEN_FCN
on it? If it succeds I'd have to delete emitted insns, etc.
Or I could add a target hook ...
Hm... indeed, too much complication...
I'd say, let's go with modeless operands and a target hook. IMO, this
is much more flexible than checking optab for supported modes.
Existing way is appropriate for single mode patterns, but we have
interdependent modes here, at least on x86.
The hook would have two input arguments, insn mode and compare mode,
where the hook returns suggested supported compare mode, or no mode,
if it really can't handle requested modes.
I think a two mode vcond pattern is in fact much cleaner than
a one mode + modeless pattern which gen* will complain about and
a target hook.
OK, but in this case, do not use mode iterators too much in order to
avoid invalid patterns.
I don't see them as invalid. They will be unused (maybe combine
would create them though?), but they have well-defined semantics
with my proposed documentation. And x86 can handle them just fine.
OK, let's go this way then... We can clean up this later if at all.
Certainly what I prefer (less work for me now) ;) The smallest
number of patterns would probably result from using vcondmodemode
to cover the same-mode cases and then add the 12 other patterns
with the respective integer / float mode variant. Thus we'd have
15 patterns in total (still much for my taste).
Ideally we could have a mode attribute that would map possibly
to an iterator, thus
(define_mode_attr matching [(V4SF [V4SF V4SI]) (V8HI V8HI) ...])
or similar. But I don't feel like adding this sort of mode
attr that really is a hidden iterator ... ;)
Thus, the following is the combined patch which bootstrapped and
tested ok on x86_64-unknown-linux-gnu with {,-m32} over night,
with the documentation for vcond added.
Ok for trunk?
Thanks,
Richard.
2011-08-30 Richard Guenther rguent...@suse.de
PR tree-optimization/27460
PR middle-end/29269
* doc/md.texi (vcond): Document.
* genopinit.c (optabs): Turn vcond{,u}_optab into a conversion
optab with two modes.
* optabs.h (enum convert_optab_index): Add COI_vcond, COI_vcondu.
(enum direct_optab_index): Remove DOI_vcond, DOI_vcondu.
(vcond_optab): Adjust.
(vcondu_optab): Likewise.
(expand_vec_cond_expr_p): Adjust prototype.
* optabs.c (get_vcond_icode): Adjust.
(expand_vec_cond_expr_p): Likewise.
(expand_vec_cond_expr): Likewise.
* tree-vect-stmts.c (vect_is_simple_cond): Return the comparison
vector type.
(vectorizable_condition): Allow differing types for comparison
and result.
* config/i386/i386.c (ix86_expand_sse_cmp): Use proper mode
for the comparison.
* config/i386/sse.md (vcondmode): Split to
vcondV_256:modeVF_256:mode, vcondV_128:modeVF_128:mode,
vcondV_128:modeVI124_128:mode and
vconduV_128:modeVI124_128:mode.
(vcondv2di): Change to vcondVI8F_128:modev2di.
(vconduv2di): Likewise.
* config/arm/neon.md (vcondmode): Change to vcond*modemode.
(vcondumode): Likewise.
* config/ia64/vect.md (vcondmode): Likewise.
(vcondumode): Likewise.
(vcondv2sf): Likewise.
* config/mips/mips-ps-3d.md (vcondv2sf): Likewise.
* config/rs6000/paired.md (vcondv2sf): Likewise.
* config/rs6000/vector.md (vcondmode): Likewise.
(vcondumode): Likewise.
* config/spu/spu.md (vcondmode): Likewise.
(vcondumode): Likewise.
* gcc.dg/vect/vect-cond-7.c: New testcase.
Index: trunk/gcc/config/arm/neon.md
===
*** trunk.orig/gcc/config/arm/neon.md 2011-08-30 10:50:52.0 +0200
--- trunk/gcc/config/arm/neon.md2011-08-30 10:51:30.0 +0200
***
*** 1600,1606
;; where op3 is , =, ==, !=, = or . Operations are performed
;; element-wise.
! (define_expand vcondmode
[(set (match_operand:VDQW 0 s_register_operand )
(if_then_else:VDQW
(match_operator 3 arm_comparison_operator
--- 1600,1606
;; where op3 is , =, ==, !=, = or . Operations are performed
;; element-wise.
! (define_expand vcondmodemode
[(set (match_operand:VDQW 0 s_register_operand )
(if_then_else:VDQW
(match_operator 3 arm_comparison_operator
***
*** 1680,1686
DONE;
})
! (define_expand vcondumode
[(set (match_operand:VDQIW 0 s_register_operand )
Re: [PATCH] Change vcondmode to vcondmode1mode2
On Tue, 30 Aug 2011, Richard Guenther wrote:
On Tue, 30 Aug 2011, Uros Bizjak wrote:
On Tue, Aug 30, 2011 at 11:15 AM, Richard Guenther rguent...@suse.de
wrote:
Hmm. But then I'd have to try emit an insn, right? Currently
the vectorizer simply looks for an optab handler ... the
operands are not readily available (but their mode is known).
So I'd create some fake regs, setup operands and call GEN_FCN
on it? If it succeds I'd have to delete emitted insns, etc.
Or I could add a target hook ...
Hm... indeed, too much complication...
I'd say, let's go with modeless operands and a target hook. IMO, this
is much more flexible than checking optab for supported modes.
Existing way is appropriate for single mode patterns, but we have
interdependent modes here, at least on x86.
The hook would have two input arguments, insn mode and compare mode,
where the hook returns suggested supported compare mode, or no mode,
if it really can't handle requested modes.
I think a two mode vcond pattern is in fact much cleaner than
a one mode + modeless pattern which gen* will complain about and
a target hook.
OK, but in this case, do not use mode iterators too much in order to
avoid invalid patterns.
I don't see them as invalid. They will be unused (maybe combine
would create them though?), but they have well-defined semantics
with my proposed documentation. And x86 can handle them just fine.
OK, let's go this way then... We can clean up this later if at all.
Certainly what I prefer (less work for me now) ;) The smallest
number of patterns would probably result from using vcondmodemode
to cover the same-mode cases and then add the 12 other patterns
with the respective integer / float mode variant. Thus we'd have
15 patterns in total (still much for my taste).
Ideally we could have a mode attribute that would map possibly
to an iterator, thus
(define_mode_attr matching [(V4SF [V4SF V4SI]) (V8HI V8HI) ...])
or similar. But I don't feel like adding this sort of mode
attr that really is a hidden iterator ... ;)
Thus, the following is the combined patch which bootstrapped and
tested ok on x86_64-unknown-linux-gnu with {,-m32} over night,
with the documentation for vcond added.
Ok for trunk?
I'm re-testing with the patterns having an extra condition like
(GET_MODE_NUNITS (V_256:MODEmode)
== GET_MODE_NUNITS (VF_256:MODEmode))
to have the HAVE_vcond* defines easily optimized.
Ok?
Thanks,
Richard.
2011-08-30 Richard Guenther rguent...@suse.de
PR tree-optimization/27460
PR middle-end/29269
* doc/md.texi (vcond): Document.
* genopinit.c (optabs): Turn vcond{,u}_optab into a conversion
optab with two modes.
* optabs.h (enum convert_optab_index): Add COI_vcond, COI_vcondu.
(enum direct_optab_index): Remove DOI_vcond, DOI_vcondu.
(vcond_optab): Adjust.
(vcondu_optab): Likewise.
(expand_vec_cond_expr_p): Adjust prototype.
* optabs.c (get_vcond_icode): Adjust.
(expand_vec_cond_expr_p): Likewise.
(expand_vec_cond_expr): Likewise.
* tree-vect-stmts.c (vect_is_simple_cond): Return the comparison
vector type.
(vectorizable_condition): Allow differing types for comparison
and result.
* config/i386/i386.c (ix86_expand_sse_cmp): Use proper mode
for the comparison.
* config/i386/sse.md (vcondmode): Split to
vcondV_256:modeVF_256:mode, vcondV_128:modeVF_128:mode,
vcondV_128:modeVI124_128:mode and
vconduV_128:modeVI124_128:mode.
(vcondv2di): Change to vcondVI8F_128:modev2di.
(vconduv2di): Likewise.
* config/arm/neon.md (vcondmode): Change to vcond*modemode.
(vcondumode): Likewise.
* config/ia64/vect.md (vcondmode): Likewise.
(vcondumode): Likewise.
(vcondv2sf): Likewise.
* config/mips/mips-ps-3d.md (vcondv2sf): Likewise.
* config/rs6000/paired.md (vcondv2sf): Likewise.
* config/rs6000/vector.md (vcondmode): Likewise.
(vcondumode): Likewise.
* config/spu/spu.md (vcondmode): Likewise.
(vcondumode): Likewise.
* gcc.dg/vect/vect-cond-7.c: New testcase.
Index: trunk/gcc/config/arm/neon.md
===
*** trunk.orig/gcc/config/arm/neon.md 2011-08-30 10:53:47.0 +0200
--- trunk/gcc/config/arm/neon.md2011-08-30 11:46:51.0 +0200
***
*** 1600,1606
;; where op3 is , =, ==, !=, = or . Operations are performed
;; element-wise.
! (define_expand vcondmode
[(set (match_operand:VDQW 0 s_register_operand )
(if_then_else:VDQW
(match_operator 3 arm_comparison_operator
--- 1600,1606
;; where op3 is , =, ==, !=, = or . Operations are performed
;; element-wise.
!
Re: [PATCH][ARM] -m{cpu,tune,arch}=native
On 29/08/11 04:29, Michael Hope wrote: On Sat, Aug 27, 2011 at 3:19 AM, Andrew Stubbsa...@codesourcery.com wrote: Hi all, This patch adds support for -mcpu=native, -mtune=native, and -march=native for ARM Linux hosts. So far, it only recognises Cortex-A8 and Cortex-A9, so I really need to find out what the magic part numbers are for other cpus before this patch is complete. I couldn't just find this information listed anywhere. I think there are a lot of clues in the kernel code, but it's hard to mine and it mostly only goes as far the architecture version, not the individual cpu. Could you send linaro-dev@ an email and ask them where this API is documented? API? It reads /proc/cpuinfo, and that just spits out the magic numbers from the processor registers. Linaro-dev might know more magic numbers though. Hmm. Should there be a -mfpu=native that picks between soft, VFP, and NEON based on the host? Yes, we could do that also, based on the CPU feature flags. I'll add it to my list of things to do, but save it for another patch. Andrew
Re: [PING][PATCH PR43513, 1/3] Replace vla with array - Implementation.
On Wed, Aug 24, 2011 at 10:47 AM, Tom de Vries vr...@codesourcery.com wrote: Hi Richard, On 07/30/2011 09:21 AM, Tom de Vries wrote: This is an updated version of the patch. I have 2 new patches and an updated testcase which I will sent out individually. Patch set was bootstrapped and reg-tested on x86_64. Ok for trunk? You already approved the the 2 new patches, and I checked them in. Ping for the updated patch and updated testcase: http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02730.html http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02733.html The patch replaces a vla __builtin_alloca that has a constant argument with an array declaration. Ok with + /* Declare array. */ + elem_type = build_nonstandard_integer_type (BITS_PER_UNIT, 1); + n_elem = size * 8 / BITS_PER_UNIT; + align = MIN (size * 8, GET_MODE_PRECISION (word_mode)); changed to use BIGGEST_ALIGNMENT instead of GET_MODE_PRECISION (word_mode). For the future, can you please include the testcases in the main patch instead of sending them separately? You're the only one separating them and it's really not helpful. Thanks, Richard. Thanks, - Tom
Re: [PATCH 01/20] Make CLooG-ISL the only supported CLooG version.
On Tue, 30 Aug 2011, Tobias Grosser wrote: On 08/29/2011 04:01 PM, Joseph S. Myers wrote: I looked at the ISL sources and saw that they generally had license notices of the form: * Use of this software is governed by the GNU LGPLv2.1 license Hi Joseph, at least according to a license compatibility chart[1] published by the FSF, it is OK to combine a LGPLv2.1 only library with a GPLv3 project. Is there any reason the compatibility matrix published by the FSF might be outdated or may not apply to us, or do you think we can rely on this information? Thanks for pointing this out. Having checked the LGPLv2.1 I think it is in fact OK after all (I may have been thinking of two other problems, the problem we had with polylib which was GPLv2 rather than LGPL and the inability to use LGPLv3+ libraries with GPLv2-only programs). -- Joseph S. Myers jos...@codesourcery.com
[0/4] Make SMS schedule register moves
I'm seeing several cases in which SMS's register move handling is
causing it to generate worse code than the normal schedulers on ARM
Cortex-A8. The problem is that we first schedule the loop without
taking the moves into account, then emit the required moves immediately
before the initial definition.
A simple example is:
void
loop (unsigned char *__restrict q, unsigned char *__restrict p, int n)
{
while (n 0)
{
q[0] = (p[0] + p[1]) 1;
q++;
p += 2;
n--;
}
}
(taken from libav). Compiled with:
-mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp
-mvectorize-with-neon-quad -O2 -ftree-vectorize -fno-auto-inc-dec
-fmodulo-sched -fmodulo-sched-allow-regmoves
on arm-linux-gnueabi-gcc (with current trunk), the scheduled loop has an
ii of 27, a stage count of 6, and requires 14 register moves, 12 of which
are vector moves. Vector moves cannot be dual-issued with most other
vector instructions, and the scheduled loop only has one free slot
for a vector move, so even in the best case, this loop theoretically
needs 27 + 12 - 1 cycles per iteration, significantly higher than the ii.
(It actually ends up much worse than that, because with so many live
vector values, we end up with lots of spills.)
The aim of the patches is to schedule the moves, and to reject the
current ii if this scheduling fails. Revital pointed out that Mustafa
Hagog had tried the same thing, so this is effectively a reimplementation
of that idea. For those who've seen Mustafa's patch, the main functional
differences are that:
- Mustafa's version scheduled from low rows to high rows, with the
high row being the one associated with the previous move. These
patches instead schedule high-to-low, which should leave a larger
window for later moves.
- The patches use a cyclic scheduling window. E.g., for a move
related to the instruction in column 1 of row 0, the patches first
try row 0 (column 0 only), then row ii-1, etc.
- The patches take instruction latency into account.
On the loop above, we reject the ii of 27 and try again with an ii of 28.
This leads to a stage count of 3 and no register moves, which is
theoretically 10 cycles quicker than before. The lack of spills means
that the real figures are much better though: on a BeagleBoard, the new
loop is 5.45 times faster than the old one. I've seen similar improvements
in other real libav loops too, not all of them due to fewer spills.
(BTW, in the ii=27 version, most of the moves are for distance-1 true
dependencies between a stage N instruction in row R and a stage N+1
instruction in row R+1.)
As well as testing on a collection of libav-derived microbenchmarks like
the one above, I tested on a commercial embeeded testsuite. It showed a
significant improvement in one test and no change for the rest.
Bootstrapped regression-tested on powerp-ibm-aix5.3.0, using a
compiler that had -fmodulo-sched and -fmodulo-sched-allow-regmoves
turned on at -O and above.
Richard
[1/4] SMS: remove register undo list
This patch removes the (unused) undo_replace_buff_elem list.
Verges on the obvious, but still.
Patch 3 splits the generation of moves into two: one function to record
what needs to happen, and another function to actually do it. It's then
easy to bail out if we decide that we don't want the moves.
Richard
gcc/
* modulo-sched.c (undo_replace_buff_elem): Delete.
(generate_reg_moves): Don't build and return an undo list.
(free_undo_replace_buff): Delete.
(sms_schedule): Adjust call to generate_reg_moves.
Don't call free_undo_replace_buff.
Index: gcc/modulo-sched.c
===
--- gcc/modulo-sched.c 2011-08-24 12:38:37.171362916 +0100
+++ gcc/modulo-sched.c 2011-08-24 12:56:17.754942951 +0100
@@ -165,17 +165,6 @@ struct partial_schedule
int stage_count; /* The stage count of the partial schedule. */
};
-/* We use this to record all the register replacements we do in
- the kernel so we can undo SMS if it is not profitable. */
-struct undo_replace_buff_elem
-{
- rtx insn;
- rtx orig_reg;
- rtx new_reg;
- struct undo_replace_buff_elem *next;
-};
-
-
static partial_schedule_ptr create_partial_schedule (int ii, ddg_ptr, int
history);
static void free_partial_schedule (partial_schedule_ptr);
@@ -456,13 +445,12 @@ print_node_sched_params (FILE *file, int
nreg_moves = --- + 1 - { dependence.
ii { 1 if not.
*/
-static struct undo_replace_buff_elem *
+static void
generate_reg_moves (partial_schedule_ptr ps, bool rescan)
{
ddg_ptr g = ps-g;
int ii = ps-ii;
int i;
- struct undo_replace_buff_elem *reg_move_replaces = NULL;
for (i = 0; i g-num_nodes; i++)
{
@@ -543,22 +531,6 @@ generate_reg_moves (partial_schedule_ptr
EXECUTE_IF_SET_IN_SBITMAP (uses_of_defs[i_reg_move], 0, i_use, sbi)
{
- struct undo_replace_buff_elem *rep;
-
- rep = (struct undo_replace_buff_elem *)
- xcalloc (1, sizeof (struct undo_replace_buff_elem));
- rep-insn = g-nodes[i_use].insn;
- rep-orig_reg = old_reg;
- rep-new_reg = new_reg;
-
- if (! reg_move_replaces)
- reg_move_replaces = rep;
- else
- {
- rep-next = reg_move_replaces;
- reg_move_replaces = rep;
- }
-
replace_rtx (g-nodes[i_use].insn, old_reg, new_reg);
if (rescan)
df_insn_rescan (g-nodes[i_use].insn);
@@ -568,21 +540,6 @@ generate_reg_moves (partial_schedule_ptr
}
sbitmap_vector_free (uses_of_defs);
}
- return reg_move_replaces;
-}
-
-/* Free memory allocated for the undo buffer. */
-static void
-free_undo_replace_buff (struct undo_replace_buff_elem *reg_move_replaces)
-{
-
- while (reg_move_replaces)
-{
- struct undo_replace_buff_elem *rep = reg_move_replaces;
-
- reg_move_replaces = reg_move_replaces-next;
- free (rep);
-}
}
/* Update the sched_params (time, row and stage) for node U using the II,
@@ -1472,8 +1429,6 @@ sms_schedule (void)
}
else
{
- struct undo_replace_buff_elem *reg_move_replaces;
-
if (!opt_sc_p)
{
/* Rotate the partial schedule to have the branch in row ii-1. */
@@ -1523,13 +1478,11 @@ sms_schedule (void)
/* The life-info is not valid any more. */
df_set_bb_dirty (g-bb);
- reg_move_replaces = generate_reg_moves (ps, true);
+ generate_reg_moves (ps, true);
if (dump_file)
print_node_sched_params (dump_file, g-num_nodes, g);
/* Generate prolog and epilog. */
generate_prolog_epilog (ps, loop, count_reg, count_init);
-
- free_undo_replace_buff (reg_move_replaces);
}
free_partial_schedule (ps);
[PATCH] Fix PR48571, remove (most) array-ref re-construction
I've run into PR48571 again, and after having fun with out data-dep
analysis code I indeed believe that we should not try to re-construct
ARRAY_REFs from code involving pointer arithmetic. ARRAY_REFs
have constraints imposed on them that are relied on by data dependence
analysis and that are indeed useful to have (the index is within
bounds, otherwise undefined behavior). We can't recover from
lowering that happened, much as Zdenek argued when I initially
proposed to lower all ARRAY_REFs to pointer arithmetic with the
original MEM_REF design.
Thus, the following completes the partial removal of reference
re-constructing I did when merging MEM_REFs (I removed the code
re-constructing COMPONENT_REFs back then).
Not much fallout, much to my surprise (I've tried it initially
on the MEM_REF branch, but quickly gave up on this additional task).
We've appearantly become better in handling of pointer based accesses
(we've already much experience here with GFortran lowering
multi-dimensional array accesses to one-dimensional ones).
The patch XFAILs one -Warray-bounds testcase, the -Warray-bounds
infrastructure needs some serious TLC which I didn't want to fold
into this patch. The testcase in question also really asks for
an 'access outside of object' warning, similar to the
'offset outside bounds of constant string' one we have.
Bootstrapped and tested an earlier version on x86_64-unknown-linux-gnu,
a final bootstrap and regtest cycle is currently running.
(yes, there are still
tree-ssa-forwprop.c:forward_propagate_addr_into_variable_array_index and
fold-const.c:try_move_mult_to_index)
Richard.
2011-08-30 Richard Guenther rguent...@suse.de
PR middle-end/48571
* gimple.h (maybe_fold_offset_to_address): Remove.
(maybe_fold_offset_to_reference): Likewise.
(maybe_fold_stmt_addition): Likewise.
(may_propagate_address_into_dereference): Likewise.
* tree-inline.c (remap_gimple_op_r): Do not reconstruct
array references.
* gimple-fold.c (canonicalize_constructor_val): Likewise.
Canonicalize invariant POINTER_PLUS_EXPRs to invariant MEM_REF
addresses instead.
(may_propagate_address_into_dereference): Remove.
(maybe_fold_offset_to_array_ref): Likewise.
(maybe_fold_offset_to_reference): Likewise.
(maybe_fold_offset_to_address): Likewise.
(maybe_fold_stmt_addition): Likewise.
(fold_gimple_assign): Do not reconstruct array references but
instead canonicalize invariant POINTER_PLUS_EXPRs to invariant
MEM_REF addresses.
(gimple_fold_stmt_to_constant_1): Likewise.
* tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
* gimplify.c (gimplify_conversion): Likewise.
(gimplify_expr): Likewise.
* gcc.c-torture/execute/pr48571-1.c: New testcase.
* gcc.dg/pr36902.c: XFAIL.
Index: gcc/tree-inline.c
===
*** gcc/tree-inline.c.orig 2011-08-30 13:01:16.0 +0200
--- gcc/tree-inline.c 2011-08-30 13:05:45.0 +0200
*** remap_gimple_op_r (tree *tp, int *walk_s
*** 853,895
tree ptr = TREE_OPERAND (*tp, 0);
tree type = remap_type (TREE_TYPE (*tp), id);
tree old = *tp;
- tree tem;
/* We need to re-canonicalize MEM_REFs from inline substitutions
that can happen when a pointer argument is an ADDR_EXPR.
Recurse here manually to allow that. */
walk_tree (ptr, remap_gimple_op_r, data, NULL);
! if ((tem = maybe_fold_offset_to_reference (EXPR_LOCATION (*tp),
!ptr,
!TREE_OPERAND (*tp, 1),
!type))
! TREE_THIS_VOLATILE (tem) == TREE_THIS_VOLATILE (old))
! {
! tree *tem_basep = tem;
! while (handled_component_p (*tem_basep))
! tem_basep = TREE_OPERAND (*tem_basep, 0);
! if (TREE_CODE (*tem_basep) == MEM_REF)
! *tem_basep
! = build2 (MEM_REF, TREE_TYPE (*tem_basep),
! TREE_OPERAND (*tem_basep, 0),
! fold_convert (TREE_TYPE (TREE_OPERAND (*tp, 1)),
! TREE_OPERAND (*tem_basep, 1)));
! else
! *tem_basep
! = build2 (MEM_REF, TREE_TYPE (*tem_basep),
! build_fold_addr_expr (*tem_basep),
! build_int_cst
! (TREE_TYPE (TREE_OPERAND (*tp, 1)), 0));
! *tp = tem;
! TREE_THIS_VOLATILE (*tem_basep) = TREE_THIS_VOLATILE (old);
! TREE_THIS_NOTRAP (*tem_basep) = TREE_THIS_NOTRAP (old);
! }
! else
! {
! *tp =
[2/4] SMS: Use ids to represent ps_insns
Instructions in a partial schedule are currently represented as a
ddg node. This patch uses a more abstract id instead. At the moment,
the ids map directly to ddg nodes, but the next patch will add register
moves to the end.
One slight advantage of using ids is that we can leave the ASAP value
on the node; we don't need to copy it across to the scheduling info.
(Later patches use the same scheduling info for moves, for which an ASAP
value would be wasted space.)
Richard
gcc/
* modulo-sched.c (ps_insn): Replace node field with an identifier.
(SCHED_ASAP): Replace with..
(NODE_ASAP): ...this macro.
(SCHED_PARAMS): New macro.
(SCHED_TIME, SCHED_FIRST_REG_MOVE, SCHED_NREG_MOVES, SCHED_ROW)
(SCHED_STAGE, SCHED_COLUMN): Redefine using SCHED_PARAMS.
(node_sched_params): Remove asap.
(ps_rtl_insn, ps_first_note): New functions.
(set_node_sched_params): Use XCNEWVEC. Don't copy across the
asap values.
(print_node_sched_params): Use SCHED_PARAMS and NODE_ASAP.
(generate_reg_moves): Pass ids to the SCHED_* macros.
(update_node_sched_params): Take a ps_insn identifier rather than
a node as parameter. Use ps_rtl_insn.
(set_columns_for_ps): Update for above field and SCHED_* macro changes.
(permute_partial_schedule): Use ps_rtl_insn and ps_first_note.
(optimize_sc): Update for above field and SCHED_* macro changes.
Update calls to try_scheduling_node_in_cycle and
update_node_sched_params.
(duplicate_insns_of_cycles): Adjust for above field and SCHED_*
macro changes. Use ps_rtl_insn and ps_first_note.
(sms_schedule): Pass ids to the SCHED_* macros.
(get_sched_window): Adjust for above field and SCHED_* macro changes.
Use NODE_ASAP instead of SCHED_ASAP.
(try_scheduling_node_in_cycle): Remove node parameter. Update
call to ps_add_node_check_conflicts. Pass ids to the SCHED_*
macros.
(sms_schedule_by_order): Update call to try_scheduling_node_in_cycle.
(ps_insert_empty_row): Adjust for above field changes.
(compute_split_row): Use ids rather than nodes.
(verify_partial_schedule): Adjust for above field changes.
(print_partial_schedule): Use ps_rtl_insn.
(create_ps_insn): Take an id rather than a node.
(ps_insn_find_column): Adjust for above field changes.
Use ps_rtl_insn.
(ps_insn_advance_column): Adjust for above field changes.
(add_node_to_ps): Remove node parameter. Update call to
create_ps_insn.
(ps_has_conflicts): Use ps_rtl_insn.
(ps_add_node_check_conflicts): Replace node parameter than an id.
Index: gcc/modulo-sched.c
===
--- gcc/modulo-sched.c 2011-08-24 12:26:13.899926738 +0100
+++ gcc/modulo-sched.c 2011-08-24 13:29:01.956079514 +0100
@@ -124,8 +124,8 @@ #define PS_STAGE_COUNT(ps) (((partial_sc
/* A single instruction in the partial schedule. */
struct ps_insn
{
- /* The corresponding DDG_NODE. */
- ddg_node_ptr node;
+ /* The number of the ddg node whose instruction is being scheduled. */
+ int id;
/* The (absolute) cycle in which the PS instruction is scheduled.
Same as SCHED_TIME (node). */
@@ -183,9 +183,7 @@ static void reset_partial_schedule (part
void print_partial_schedule (partial_schedule_ptr, FILE *);
static void verify_partial_schedule (partial_schedule_ptr, sbitmap);
static ps_insn_ptr ps_add_node_check_conflicts (partial_schedule_ptr,
- ddg_node_ptr node, int cycle,
- sbitmap must_precede,
- sbitmap must_follow);
+ int, int, sbitmap, sbitmap);
static void rotate_partial_schedule (partial_schedule_ptr, int);
void set_row_column_for_ps (partial_schedule_ptr);
static void ps_insert_empty_row (partial_schedule_ptr, int, sbitmap);
@@ -208,25 +206,23 @@ static void calculate_must_precede_follo
int, int, sbitmap, sbitmap, sbitmap);
static int get_sched_window (partial_schedule_ptr, ddg_node_ptr,
sbitmap, int, int *, int *, int *);
-static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
- int, int, sbitmap, int *, sbitmap,
- sbitmap);
+static bool try_scheduling_node_in_cycle (partial_schedule_ptr, int, int,
+ sbitmap, int *, sbitmap, sbitmap);
static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
-#define SCHED_ASAP(x) (((node_sched_params_ptr)(x)-aux.info)-asap)
-#define SCHED_TIME(x) (((node_sched_params_ptr)(x)-aux.info)-time)
-#define SCHED_FIRST_REG_MOVE(x) \
-
[3/4] SMS: Record moves in the partial schedule
This patch adds infrastructure that will be used by the final patch.
Specifically:
- it splits the generation of register moves into two: schedule_reg_moves
records moves in the partial schedule, while apply_reg_moves makes the
register substitutions.
This patch doesn't actually schedule the moves. Instead, there's
some throw-away code in apply_reg_moves to emit the moves in the
same as we do now. That's throw-away code that will be removed
in the final patch.
- schedule_reg_moves is allowed to fail. We then try again with the
next ii (subject to the usual ii limits).
In this patch, schedule_reg_moves always returns true.
- The partial schedule uses ids to represent register moves.
The first register move has id g-num_nodes.
Richard
gcc/
* modulo-sched.c (ps_insn): Adjust comment.
(ps_reg_move_info): New structure.
(partial_schedule): Add reg_moves field.
(SCHED_PARAMS): Use node_sched_param_vec instead of node_sched_params.
(node_sched_params): Turn first_reg_move into an identifier.
(ps_reg_move): New function.
(ps_rtl_insn): Cope with register moves.
(ps_first_note): Adjust comment and assert that the instruction
isn't a register move.
(node_sched_params): Replace with...
(node_sched_param_vec): ...this vector.
(set_node_sched_params): Adjust accordingly.
(print_node_sched_params): Take a partial schedule instead of a ddg.
Use ps_rtl_insn and ps_reg_move.
(generate_reg_moves): Rename to...
(schedule_reg_moves): ...this. Remove rescan parameter. Record each
move in the partial schedule, but don't emit it here. Don't perform
register substitutions here either.
(apply_reg_moves): New function.
(duplicate_insns_of_cycles): Use register indices directly,
rather than finding instructions using PREV_INSN. Use ps_reg_move.
(sms_schedule): Call schedule_reg_moves before committing to
a partial schedule. Try the next ii if the schedule fails.
Use apply_reg_moves instead of generate_reg_moves. Adjust
call to print_node_sched_params. Free node_sched_param_vec
instead of node_sched_params.
(create_partial_schedule): Initialize reg_moves.
(free_partial_schedule): Free reg_moves.
Index: gcc/modulo-sched.c
===
*** gcc/modulo-sched.c 2011-08-30 11:32:13.924908138 +0100
--- gcc/modulo-sched.c 2011-08-30 13:06:36.528669762 +0100
*** #define PS_STAGE_COUNT(ps) (((partial_sc
*** 124,130
/* A single instruction in the partial schedule. */
struct ps_insn
{
! /* The number of the ddg node whose instruction is being scheduled. */
int id;
/* The (absolute) cycle in which the PS instruction is scheduled.
--- 124,132
/* A single instruction in the partial schedule. */
struct ps_insn
{
! /* Identifies the instruction to be scheduled. Values smaller than
! the ddg's num_nodes refer directly to ddg nodes. A value of
! X - num_nodes refers to register move X. */
int id;
/* The (absolute) cycle in which the PS instruction is scheduled.
*** struct ps_insn
*** 137,142
--- 139,170
};
+ /* Information about a register move that has been added to a partial
+schedule. */
+ struct ps_reg_move_info
+ {
+ /* The dependencies exist between the ps_insn with id DEF and the
+ ps_insns with the ids in USES. */
+ int def;
+ sbitmap uses;
+
+ /* DEF's instruction defines OLD_REG. The original form of
+ USES' instructions used it. */
+ rtx old_reg;
+
+ /* USES's instructions must now use NEW_REG instead of OLD_REG. */
+ rtx new_reg;
+
+ /* An instruction that sets NEW_REG to the correct value. The first
+ move associated with DEF will have an rhs of OLD_REG; later moves
+ use the result of the previous move. */
+ rtx insn;
+ };
+
+ typedef struct ps_reg_move_info ps_reg_move_info;
+ DEF_VEC_O (ps_reg_move_info);
+ DEF_VEC_ALLOC_O (ps_reg_move_info, heap);
+
/* Holds the partial schedule as an array of II rows. Each entry of the
array points to a linked list of PS_INSNs, which represents the
instructions that are scheduled for that row. */
*** struct partial_schedule
*** 148,153
--- 176,185
/* rows[i] points to linked list of insns scheduled in row i (0=iii). */
ps_insn_ptr *rows;
+ /* All the moves added for this partial schedule. Index X has
+ a ps_insn id of X + g-num_nodes. */
+ VEC (ps_reg_move_info, heap) *reg_moves;
+
/* rows_length[i] holds the number of instructions in the row.
It is used only (as an optimization) to back off quickly from
trying to schedule a node in a full row; that is, to avoid running
*** static bool remove_node_from_ps (partial
Re: [PATCH Atom][PR middle-end/44382] Tree reassociation improvement
On Wed, Aug 10, 2011 at 4:49 PM, Ilya Enkovich enkovich@gmail.com wrote:
Hello,
Here is a new version of the patch. Changes from the previous version
(http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02240.html):
- updated to trunk
- TODO_remove_unused_locals flag was removed from todo_flags_finish
of reassoc pass
Bootstrapped and checked on x86_64-linux.
The fact that you have to adjust gcc.dg/tree-ssa/pr38533.c looks problematic
to me. Can you investigate the problem report, look at the geneated
code with the atom default of the param and see whether it's still
reasonably fixed (maybe you'd already done this)?
+ /* Check if we may use less width and still compute sequence for
+ the same time. It will allow us to reduce registers usage. */
+ while (width 1
+ get_required_cycles (ops_num, width - 1) == cycles_best)
+width--;
I suppose get_required_cycles () is monotonic in width? Would it
make sense to binary search the best width then (I realize the
default is 1 and the only target differing has 2, but ...)? Maybe at
least add a comment to this effect? Or not decrement by one
but instead divide by two on each iteration (which is the same for 1 and 2 ...)?
It's also all a mapping that is constant - we should be able to
pre-compute it for all values, eventually compressing it to a
much simpler formula width = f (cpu_width, ops_num)?
+static void
+rewrite_expr_tree_parallel (gimple stmt, int width,
+ VEC(operand_entry_t, heap) * ops)
+{
+ enum tree_code opcode = gimple_assign_rhs_code (stmt);
+ int op_num = VEC_length (operand_entry_t, ops);
+ int stmt_num = op_num - 1;
+ gimple *stmts = XNEWVEC (gimple, stmt_num);
use XALLOCAVEC here and remove the free call.
+ if (ready_stmts_end == 0
+ (i - stmt_index = width || op_index 1))
s go to the next line, not at the end
+ else
+ {
+ tree var = create_tmp_reg (TREE_TYPE (last_rhs1), reassoc);
+ add_referenced_var (var);
please re-use a common variable for the whole chain, they will
all necessarily have compatible type. Creating and maintaining
decls is expensive (also avoid giving them names, thus just
pass NULL instead of reassoc).
+ {
+ enum machine_mode mode = TYPE_MODE (TREE_TYPE (lhs));
+ int width = get_reassociation_width (ops, rhs_code, mode);
as you are passing in the mode here, consider passing the number
of operands in ops as well instead of ops. This way we might consider
moving this whole function to the target or to generic code. Similar
move the dump printing in get_reassociation_width
+ if (dump_file (dump_flags TDF_DETAILS))
+fprintf (dump_file,
+Width = %d was chosen for reassociation\n, width);
here to the caller.
Sorry for taking so long to review this again. I'll promise to be quick
once you post an update.
Thanks,
Richard.
Thanks,
Ilya
---
gcc/
2011-08-10 Enkovich Ilya ilya.enkov...@intel.com
PR middle-end/44382
* target.def (reassociation_width): New hook.
* doc/tm.texi.in (reassociation_width): Likewise.
* doc/tm.texi (reassociation_width): Likewise.
* doc/invoke.texi (tree-reassoc-width): New param documented.
* hooks.h (hook_int_uint_mode_1): New default hook.
* hooks.c (hook_int_uint_mode_1): Likewise.
* config/i386/i386.h (ix86_tune_indices): Add
X86_TUNE_REASSOC_INT_TO_PARALLEL and
X86_TUNE_REASSOC_FP_TO_PARALLEL.
(TARGET_REASSOC_INT_TO_PARALLEL): New.
(TARGET_REASSOC_FP_TO_PARALLEL): Likewise.
* config/i386/i386.c (initial_ix86_tune_features): Add
X86_TUNE_REASSOC_INT_TO_PARALLEL and
X86_TUNE_REASSOC_FP_TO_PARALLEL.
(ix86_reassociation_width) implementation of
new hook for i386 target.
* params.def (PARAM_TREE_REASSOC_WIDTH): New param added.
* tree-ssa-reassoc.c (get_required_cycles): New function.
(get_reassociation_width): Likewise.
(swap_ops_for_binary_stmt): Likewise.
(rewrite_expr_tree_parallel): Likewise.
(rewrite_expr_tree): Refactored. Part of code moved into
swap_ops_for_binary_stmt.
(reassociate_bb): Now checks reassociation width to be used
and call rewrite_expr_tree_parallel instead of rewrite_expr_tree
if needed.
gcc/testsuite/
2011-08-10 Enkovich Ilya ilya.enkov...@intel.com
* gcc.dg/tree-ssa/pr38533.c (dg-options): Added option
--param tree-reassoc-width=1.
* gcc.dg/tree-ssa/reassoc-24.c: New test.
* gcc.dg/tree-ssa/reassoc-25.c: Likewise.
[4/4] Make SMS schedule register moves
This is the move-scheduling patch itself. It should be fairly
self-explanatory. Let me know if it isn't, and I'll try to improve
the commentary.
One potentially controversial change is to the way we handle moves
in the prologue and epilogue. The current code uses a conservative
check to decide which stages need which moves. This check copes
with values that are live before the loop, and emits some moves
that aren't actually needed. The code also emits chains of moves
that can be trivially optimised through propagation. We rely on
later patches to clean this up for us (and they do).
So, rather than keep a rather complicated check here, I've simply
emitted the moves for all stages. In principle, that will generate
a little more dead code than now in cases where chains of two moves
are needed, but that seems to be very rare (when moves are scheduled).
Richard
gcc/
* modulo-sched.c (extend_node_sched_params): New function.
(print_node_sched_params): Print the stage.
(set_columns_for_row, schedule_reg_move): New functions.
(set_columns_for_ps): Move up file and use set_columns_for_now.
(schedule_reg_moves): Call extend_node_sched_params and
schedule_reg_move. Extend size of uses bitmap. Return false
if a move could not be scheduled.
(apply_reg_moves): Don't emit moves here.
(permute_partial_schedule): Handle register moves.
(duplicate_insns_of_cycles): Remove for_prolog. Always emit moves.
(generate_prolog_epilog): Update calls accordingly.
Index: gcc/modulo-sched.c
===
--- gcc/modulo-sched.c 2011-08-30 13:06:36.528669762 +0100
+++ gcc/modulo-sched.c 2011-08-30 13:22:08.029124537 +0100
@@ -220,8 +220,6 @@ static partial_schedule_ptr sms_schedule
static void permute_partial_schedule (partial_schedule_ptr, rtx);
static void generate_prolog_epilog (partial_schedule_ptr, struct loop *,
rtx, rtx);
-static void duplicate_insns_of_cycles (partial_schedule_ptr,
- int, int, int, rtx);
static int calculate_stage_count (partial_schedule_ptr, int);
static void calculate_must_precede_follow (ddg_node_ptr, int, int,
int, int, sbitmap, sbitmap, sbitmap);
@@ -458,6 +456,15 @@ set_node_sched_params (ddg_ptr g)
node_sched_param_vec, g-num_nodes);
}
+/* Make sure that node_sched_param_vec has an entry for every move in PS. */
+static void
+extend_node_sched_params (partial_schedule_ptr ps)
+{
+ VEC_safe_grow_cleared (node_sched_params, heap, node_sched_param_vec,
+ps-g-num_nodes + VEC_length (ps_reg_move_info,
+ ps-reg_moves));
+}
+
static void
print_node_sched_params (FILE *file, int num_nodes, partial_schedule_ptr ps)
{
@@ -474,6 +481,7 @@ print_node_sched_params (FILE *file, int
INSN_UID (ps_rtl_insn (ps, i)));
fprintf (file, asap = %d:\n, NODE_ASAP (ps-g-nodes[i]));
fprintf (file, time = %d:\n, nsp-time);
+ fprintf (file, stage = %d:\n, nsp-stage);
fprintf (file, nreg_moves = %d:\n, nsp-nreg_moves);
for (j = 0; j nsp-nreg_moves; j++)
{
@@ -485,6 +493,168 @@ print_node_sched_params (FILE *file, int
}
}
+/* Set SCHED_COLUMN for each instruction in row ROW of PS. */
+static void
+set_columns_for_row (partial_schedule_ptr ps, int row)
+{
+ ps_insn_ptr cur_insn;
+ int column;
+
+ column = 0;
+ for (cur_insn = ps-rows[row]; cur_insn; cur_insn = cur_insn-next_in_row)
+SCHED_COLUMN (cur_insn-id) = column++;
+}
+
+/* Set SCHED_COLUMN for each instruction in PS. */
+static void
+set_columns_for_ps (partial_schedule_ptr ps)
+{
+ int row;
+
+ for (row = 0; row ps-ii; row++)
+set_columns_for_row (ps, row);
+}
+
+/* Try to schedule the move with ps_insn identifier I_REG_MOVE in PS.
+ The source of the move is provided by I_MUST_FOLLOW, which has
+ already been scheduled. MUST_FOLLOW is a scratch bitmap that
+ is big enough to hold I_MUST_FOLLOW.
+
+ Return true on success. */
+static bool
+schedule_reg_move (partial_schedule_ptr ps, int i_reg_move,
+ sbitmap must_follow, int i_must_follow)
+{
+ unsigned int u;
+ int i, start_row, end_row, this_start, this_end, this_row, latency;
+ int origin_row, origin_column;
+ sbitmap_iterator sbi;
+ ps_reg_move_info *move;
+
+ move = ps_reg_move (ps, i_reg_move);
+
+ /* The cyclic lifetime of move-new_reg starts and ends at move-def
+ (the instruction that defines move-old_reg). We need to decide
+ where in that cyclic lifetime the move should go. The position
+ is limited by I_MUST_FOLLOW (which defines the source of the move)
+ and the nodes in move-uses (which consume the result).
+
+ Specifically, the lowest possible row (relative to move-def)
+ is the maximum
Re: [4/4] Make SMS schedule register moves
On Tue, Aug 30, 2011 at 2:29 PM, Richard Sandiford
richard.sandif...@linaro.org wrote:
This is the move-scheduling patch itself. It should be fairly
self-explanatory. Let me know if it isn't, and I'll try to improve
the commentary.
Can you add some testcases?
Thanks,
Richard.
One potentially controversial change is to the way we handle moves
in the prologue and epilogue. The current code uses a conservative
check to decide which stages need which moves. This check copes
with values that are live before the loop, and emits some moves
that aren't actually needed. The code also emits chains of moves
that can be trivially optimised through propagation. We rely on
later patches to clean this up for us (and they do).
So, rather than keep a rather complicated check here, I've simply
emitted the moves for all stages. In principle, that will generate
a little more dead code than now in cases where chains of two moves
are needed, but that seems to be very rare (when moves are scheduled).
Richard
gcc/
* modulo-sched.c (extend_node_sched_params): New function.
(print_node_sched_params): Print the stage.
(set_columns_for_row, schedule_reg_move): New functions.
(set_columns_for_ps): Move up file and use set_columns_for_now.
(schedule_reg_moves): Call extend_node_sched_params and
schedule_reg_move. Extend size of uses bitmap. Return false
if a move could not be scheduled.
(apply_reg_moves): Don't emit moves here.
(permute_partial_schedule): Handle register moves.
(duplicate_insns_of_cycles): Remove for_prolog. Always emit moves.
(generate_prolog_epilog): Update calls accordingly.
Index: gcc/modulo-sched.c
===
--- gcc/modulo-sched.c 2011-08-30 13:06:36.528669762 +0100
+++ gcc/modulo-sched.c 2011-08-30 13:22:08.029124537 +0100
@@ -220,8 +220,6 @@ static partial_schedule_ptr sms_schedule
static void permute_partial_schedule (partial_schedule_ptr, rtx);
static void generate_prolog_epilog (partial_schedule_ptr, struct loop *,
rtx, rtx);
-static void duplicate_insns_of_cycles (partial_schedule_ptr,
- int, int, int, rtx);
static int calculate_stage_count (partial_schedule_ptr, int);
static void calculate_must_precede_follow (ddg_node_ptr, int, int,
int, int, sbitmap, sbitmap,
sbitmap);
@@ -458,6 +456,15 @@ set_node_sched_params (ddg_ptr g)
node_sched_param_vec, g-num_nodes);
}
+/* Make sure that node_sched_param_vec has an entry for every move in PS. */
+static void
+extend_node_sched_params (partial_schedule_ptr ps)
+{
+ VEC_safe_grow_cleared (node_sched_params, heap, node_sched_param_vec,
+ ps-g-num_nodes + VEC_length (ps_reg_move_info,
+ ps-reg_moves));
+}
+
static void
print_node_sched_params (FILE *file, int num_nodes, partial_schedule_ptr ps)
{
@@ -474,6 +481,7 @@ print_node_sched_params (FILE *file, int
INSN_UID (ps_rtl_insn (ps, i)));
fprintf (file, asap = %d:\n, NODE_ASAP (ps-g-nodes[i]));
fprintf (file, time = %d:\n, nsp-time);
+ fprintf (file, stage = %d:\n, nsp-stage);
fprintf (file, nreg_moves = %d:\n, nsp-nreg_moves);
for (j = 0; j nsp-nreg_moves; j++)
{
@@ -485,6 +493,168 @@ print_node_sched_params (FILE *file, int
}
}
+/* Set SCHED_COLUMN for each instruction in row ROW of PS. */
+static void
+set_columns_for_row (partial_schedule_ptr ps, int row)
+{
+ ps_insn_ptr cur_insn;
+ int column;
+
+ column = 0;
+ for (cur_insn = ps-rows[row]; cur_insn; cur_insn = cur_insn-next_in_row)
+ SCHED_COLUMN (cur_insn-id) = column++;
+}
+
+/* Set SCHED_COLUMN for each instruction in PS. */
+static void
+set_columns_for_ps (partial_schedule_ptr ps)
+{
+ int row;
+
+ for (row = 0; row ps-ii; row++)
+ set_columns_for_row (ps, row);
+}
+
+/* Try to schedule the move with ps_insn identifier I_REG_MOVE in PS.
+ The source of the move is provided by I_MUST_FOLLOW, which has
+ already been scheduled. MUST_FOLLOW is a scratch bitmap that
+ is big enough to hold I_MUST_FOLLOW.
+
+ Return true on success. */
+static bool
+schedule_reg_move (partial_schedule_ptr ps, int i_reg_move,
+ sbitmap must_follow, int i_must_follow)
+{
+ unsigned int u;
+ int i, start_row, end_row, this_start, this_end, this_row, latency;
+ int origin_row, origin_column;
+ sbitmap_iterator sbi;
+ ps_reg_move_info *move;
+
+ move = ps_reg_move (ps, i_reg_move);
+
+ /* The cyclic lifetime of move-new_reg starts and ends at move-def
+ (the instruction that defines move-old_reg). We need to decide
+ where in that cyclic lifetime the move should go. The position
[PATCH] [MELT] Fix versions comparisons
Comparison of MELT version were not consistent accross the codebase:
- MELT .c meltdesc were generated with melt_versionstr using
MELT_VERSION_STRING define
- comparison at several places in the source code was done against
MELT_VERSION_STRING
- comparision at other places was done between melt_genversionstr and
melt_version_str ().
This commit changes comparison/generation at all those place to
something more consistent:
- generate meltdesc's melt_versionstr with melt_version_str () call.
- compare between melt_versionstr and melt_version_str ().
---
gcc/ChangeLog.MELT | 10 ++
gcc/melt-runtime.c | 16
gcc/melt/warmelt-outobj.melt |2 +-
3 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/gcc/ChangeLog.MELT b/gcc/ChangeLog.MELT
index 46b1471..bb46c20 100644
--- a/gcc/ChangeLog.MELT
+++ b/gcc/ChangeLog.MELT
@@ -1,3 +1,13 @@
+2011-08-30 Alexandre Lissy ali...@mandriva.com
+ * melt-runtime.c (melt_load_module_index):
+ - Export melt_versionstr from meltdesc instead of
+ melt_genversionstr.
+ - Make use of melt_version_str() instead of MELT_VERSION_STR.
+ - Compare melt_version_str() against melt_versionstr instead of
+ melt_genversionstr.
+ * melt/warmelt-outobj.melt (output_melt_descriptor): Make use of
+ melt_version_str() to build melt_versionstr instead of using
+ MELT_VERSION_STRING.
2011-08-30 Basile Starynkevitch bas...@starynkevitch.net
* melt-predef.list (DISCR_BOX): Remove.
diff --git a/gcc/melt-runtime.c b/gcc/melt-runtime.c
index 08b3d7b..bb0505c 100644
--- a/gcc/melt-runtime.c
+++ b/gcc/melt-runtime.c
@@ -8548,7 +8548,7 @@ melt_load_module_index (const char*srcbase, const
char*flavor)
/* list of optional dynamic symbols (dlsymed in the module, provided
in the FOO+meltdesc.c file). */
#define MELTDESCR_OPTIONAL_LIST\
- MELTDESCR_OPTIONAL_SYMBOL (melt_genversionstr, char);\
+ MELTDESCR_OPTIONAL_SYMBOL (melt_versionstr, char); \
MELTDESCR_OPTIONAL_SYMBOL (melt_modulerealpath, char)
/* declare our dymamic symbols */
@@ -8646,10 +8646,10 @@ melt_load_module_index (const char*srcbase, const
char*flavor)
MELT module name %s in MELT descriptive file %s not as expected,
descmodulename, srcpath);
if (!flag_melt_bootstrapping
- strcmp(descversionmelt, MELT_VERSION_STRING))
+ strcmp(descversionmelt, melt_version_str ()))
warning (0,
MELT descriptive file %s for MELT version %s, but this MELT
runtime is version %s,
-srcpath, descversionmelt, MELT_VERSION_STRING);
+srcpath, descversionmelt, melt_version_str ());
sobase =
concat (lbasename(descmodulename), ., desccumulatedhexmd5, ., flavor,
.so, NULL);
debugeprintf (melt_load_module_index long sobase %s workdir %s,
@@ -8762,10 +8762,10 @@ melt_load_module_index (const char*srcbase, const
char*flavor)
time_t nowt = 0;
time (nowt);
if (strcmp (MELTDESCR_REQUIRED (melt_versionmeltstr),
- MELT_VERSION_STRING))
+melt_version_str ()))
warning (0,
MELT module %s for source %s has mismatching MELT version %s,
expecting %s,
-sopath, srcbase, MELTDESCR_REQUIRED (melt_versionmeltstr),
MELT_VERSION_STRING);
+sopath, srcbase, MELTDESCR_REQUIRED (melt_versionmeltstr),
melt_version_str ());
if (strcmp (MELTDESCR_REQUIRED (melt_prepromd5meltrun),
melt_run_preprocessed_md5))
warning (0,
@@ -8830,11 +8830,11 @@ melt_load_module_index (const char*srcbase, const
char*flavor)
free (srcpath), srcpath = NULL;
free (curpath), curpath = NULL;
};
- if (MELTDESCR_OPTIONAL(melt_genversionstr)
- strcmp(MELTDESCR_OPTIONAL(melt_genversionstr), melt_version_str()))
+ if (MELTDESCR_OPTIONAL(melt_versionstr)
+ strcmp(MELTDESCR_OPTIONAL(melt_versionstr), melt_version_str()))
warning (0,
MELT module %s generated by %s but used by %s [possible
version mismatch],
-sopath, MELTDESCR_OPTIONAL(melt_genversionstr),
melt_version_str ());
+sopath, MELTDESCR_OPTIONAL(melt_versionstr), melt_version_str
());
gentim = (time_t) (*MELTDESCR_REQUIRED(melt_gen_timenum));
if (gentim nowt)
warning (0,
diff --git a/gcc/melt/warmelt-outobj.melt b/gcc/melt/warmelt-outobj.melt
index 06b2261..10870d4 100644
--- a/gcc/melt/warmelt-outobj.melt
+++ b/gcc/melt/warmelt-outobj.melt
@@ -3778,7 +3778,7 @@
(code_chunk
genvmeltch
#{ /* output_melt_descriptor $GENVMELTCH + */
- meltgc_add_strbuf_cstr ($DEBUF, MELT_VERSION_STRING) ;
+ meltgc_add_strbuf_cstr ($DEBUF, melt_version_str ()) ;
}#)
(add2sbuf_strconst debuf \;)
(add2sbuf_indentnl debuf 0)
--
1.7.6
Re: [4/4] Make SMS schedule register moves
Richard Guenther richard.guent...@gmail.com writes: On Tue, Aug 30, 2011 at 2:29 PM, Richard Sandiford richard.sandif...@linaro.org wrote: This is the move-scheduling patch itself. It should be fairly self-explanatory. Let me know if it isn't, and I'll try to improve the commentary. Can you add some testcases? I don't think it's an easy thing to test for. E.g. with the resampling loop in the covering message, there might well be a reasonable ii=27 schedule that doesn't need as many moves. Richard
Re: Vector shuffling
On Tue, Aug 30, 2011 at 4:31 AM, Artem Shinkarov
artyom.shinkar...@gmail.com wrote:
Hi
This is a patch for the explicit vector shuffling we have discussed a
long time ago here:
http://gcc.gnu.org/ml/gcc-patches/2010-08/msg01092.html
The new patch introduces the new tree code, as we agreed, and expands
this code by checking the vshuffle pattern in the backend.
The patch at the moment lacks of some examples, but mainly it works
fine for me. It would be nice if i386 gurus could look into the way I
am doing the expansion.
Middle-end parts seems to be more or less fine, they have not changed
much from the previous time.
+@code{__builtin_shuffle (vec, mask)} and
+@code{__builtin_shuffle (vec0, vec1, mask)}. Both functions construct
the latter would be __builtin_shuffle2.
+bool
+expand_vec_shuffle_expr_p (enum machine_mode mode, tree v0,
+ tree v1, tree mask)
+{
+#define inner_type_size(vec) \
+ GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (TREE_TYPE (vec
missing comment. No #defines like this please, just initialize
two temporary variables.
+
+rtx
+expand_vec_shuffle_expr (tree type, tree v0, tree v1, tree mask, rtx target)
+{
comment.
+vshuffle:
+ gcc_assert (v1 == v0);
+
+ icode = direct_optab_handler (vshuffle_optab, mode);
hmm, so we don't have a vshuffle2 optab but always go via the
builtin function, but only for constant masks there? I wonder
if we should arrange for targets to only support a vshuffle
optab (thus, transition away from the builtin) and so
unconditionally have a vshuffle2 optab only (with possibly
equivalent v1 and v0?)
I suppose Richard might remember what he had in mind back
when we discussed this.
Index: gcc/c-typeck.c
===
--- gcc/c-typeck.c (revision 177758)
+++ gcc/c-typeck.c (working copy)
@@ -2815,6 +2815,68 @@ build_function_call_vec (location_t loc,
!check_builtin_function_arguments (fundecl, nargs, argarray))
return error_mark_node;
+ /* Typecheck a builtin function which is declared with variable
+ argument list. */
+ if (fundecl DECL_BUILT_IN (fundecl)
+ DECL_BUILT_IN_CLASS (fundecl) == BUILT_IN_NORMAL)
just add to check_builtin_function_arguments which is called right
in front of your added code.
+ /* Here we change the return type of the builtin function
+ from int f(...) -- t f(...) where t is a type of the
+ first argument. */
+ fundecl = copy_node (fundecl);
+ TREE_TYPE (fundecl) = build_function_type (TREE_TYPE (firstarg),
+TYPE_ARG_TYPES (TREE_TYPE (fundecl)));
+ function = build_fold_addr_expr (fundecl);
oh, hum - now I remember ;) Eventually the C frontend should handle
this not via the function call mechanism but similar to how Joseph
added __builtin_complex support with
2011-08-19 Joseph Myers jos...@codesourcery.com
* c-parser.c (c_parser_postfix_expression): Handle RID_BUILTIN_COMPLEX.
* doc/extend.texi (__builtin_complex): Document.
and then emit VEC_SHUFFLE_EXPRs directly from the frontend. Joseph?
FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (inside_init), ix, value)
- if (!CONSTANT_CLASS_P (value))
+ if (!CONSTANT_CLASS_P (value))
watch out for spurious whitespace changes.
Index: gcc/gimplify.c
===
--- gcc/gimplify.c (revision 177758)
+++ gcc/gimplify.c (working copy)
@@ -7050,6 +7050,7 @@ gimplify_expr (tree *expr_p, gimple_seq
break;
case BIT_FIELD_REF:
+ case VEC_SHUFFLE_EXPR:
I don't think that's quite the right place given the is_gimple_lvalue
predicate on the first operand. More like
case VEC_SHUFFLE_EXPR:
goto expr_3;
+/* Vector shuffle expression. A = VEC_SHUFFLE_EXPRv0, v1, maks
typo, mask
+ means
+
+ freach i in length (mask):
+ A = mask[i] length (v0) ? v0[mask[i]] : v1[mask[i]]
+*/
+DEFTREECODE (VEC_SHUFFLE_EXPR, vec_shuffle_expr, tcc_expression, 3)
what is the (is there any?) constraint on the operand types, especially
the mask type?
Index: gcc/gimple.c
===
--- gcc/gimple.c(revision 177758)
+++ gcc/gimple.c(working copy)
@@ -2623,6 +2623,7 @@ get_gimple_rhs_num_ops (enum tree_code c
|| (SYM) == ADDR_EXPR\
|| (SYM) == WITH_SIZE_EXPR \
|| (SYM) == SSA_NAME \
+ || (SYM) == VEC_SHUFFLE_EXPR \
|| (SYM) == VEC_COND_EXPR) ? GIMPLE_SINGLE_RHS \
: GIMPLE_INVALID_RHS),
#define END_OF_BASE_TREE_CODES (unsigned char) GIMPLE_INVALID_RHS,
please make it GIMPLE_TERNARY_RHS instead.
which requires adjustment at
Re: [4/4] Make SMS schedule register moves
On Tue, Aug 30, 2011 at 2:43 PM, Richard Sandiford richard.sandif...@linaro.org wrote: Richard Guenther richard.guent...@gmail.com writes: On Tue, Aug 30, 2011 at 2:29 PM, Richard Sandiford richard.sandif...@linaro.org wrote: This is the move-scheduling patch itself. It should be fairly self-explanatory. Let me know if it isn't, and I'll try to improve the commentary. Can you add some testcases? I don't think it's an easy thing to test for. E.g. with the resampling loop in the covering message, there might well be a reasonable ii=27 schedule that doesn't need as many moves. So, does it only improve code generation or does it expose more loops as SMS candidates? If the former, ok ... Richard. Richard
[Ada] Prefixed calls as generic actuals
Generic actuals are pre-analyzed in order to capture external names, but are only fully analyzed within the instance. If an actual is a prefixed call to a dispatching operation, it may appear syntactically as a call without actuals. It is necessary to parse it as an object.operation again in order to capture the controlling first argument in the call. The following must compile quietly: gcc -c -gnat05 synch.adb --- package Synch is type Si is synchronized interface; function Name (P : Si) return String is abstract; procedure Need_Body; end Synch; --- package body Synch is procedure Need_Body is begin null; end Need_Body; type Access_T is not null access Si'Class; task type T is new Si with end T; overriding function Name (P : T) return String; function Name (P : T) return String is begin return Hej hopp ditt feta nylle; end Name; task body T is begin null; end T; TP : Access_T := Access_T'(new T); I : T; generic S : in String; package G is end; S1 : constant String := TP.Name; S2 : constant String := TP.all.Name; S3 : constant String := I.Name; package Works_Fine_1 is new G (S = S1); package Works_Fine_2 is new G (S = I.Name); package Trouble_1 is new G (S = TP.Name); package Trouble_2 is new G (S = TP.all.Name); end Synch; Tested on x86_64-pc-linux-gnu, committed on trunk 2011-08-30 Ed Schonberg schonb...@adacore.com * sem_res.adb (Check_Parameterless_Call): If the node is a selected component and the selector is a dispatching operation, check if it is a prefixed call before rewriting as a parameterless function call. Index: sem_res.adb === --- sem_res.adb (revision 178293) +++ sem_res.adb (working copy) @@ -1115,6 +1115,20 @@ if Nkind (Parent (N)) /= N_Function_Call or else N /= Name (Parent (N)) then + +-- This may be a prefixed call that was not fully analyzed, e.g. +-- an actual in an instance. + +if Ada_Version = Ada_2005 + and then Nkind (N) = N_Selected_Component + and then Is_Dispatching_Operation (Entity (Selector_Name (N))) +then + Analyze_Selected_Component (N); + if Nkind (N) /= N_Selected_Component then + return; + end if; +end if; + Nam := New_Copy (N); -- If overloaded, overload set belongs to new copy
[Ada] Ada 2012 anonymous access conversions and membership tests
This set of changes implements support for the Ada 2012 features of implicit conversions for anonymous access types and membership tests with a test expression of an anonymous access type (see AI05-0149). Expressions of an anonymous access type are now generally allowed in contexts where the expected type is a general access type, unless the expression denotes the name of an access object that has a dynamically determined accessibility level (specifically, access parameters and stand-alone objects of anonymous access types are not allowed to be implicitly converted). If such an expression is resolved, then the expression is rewritten as a conversion to the expected type (except for the expression of a membership test), and the checks for valid conversions take care of applying the legality restrictions (the equivalent explicit conversion must be legal). In the case of membership tests, the test will return true if the conversion of the expression is legal, if it satisfies accessibility rules, and the designated object satisfies any constraints and tagged type coverage requirements of the tested type's designated type. The test given below must report the following errors when compiled with -gnat2012: ai05_0149_test_errors.adb:28:18: implicit conversion of anonymous access formal not allowed ai05_0149_test_errors.adb:54:18: implicit conversion of stand-alone anonymous access object not allowed ai05_0149_test_errors.adb:56:26: implicit conversion of anonymous access value violates accessibility ai05_0149_test_errors.adb:59:39: cannot convert local pointer to non-local access type ai05_0149_test_errors.adb:62:30: implicit conversion of anonymous access value violates accessibility ai05_0149_test_errors.adb:85:16: implicit conversion of stand-alone anonymous access object not allowed ai05_0149_test_errors.adb:87:15: implicit conversion of stand-alone anonymous access object not allowed procedure AI05_0149_Test_Errors is type Acc_Integer is access all Integer; type Extra_Acc_Integer is access all Integer; I : aliased Integer := 0; Acc_I_1 : Acc_Integer := I'Access; Anon_Acc_I_1 : access Integer := Acc_I_1; type Rec is record A : access Integer; end record; R : Rec; procedure Proc (A : access Integer) is type Nested_Acc_Integer is access all Integer; Nested_Acc_Int : Nested_Acc_Integer := I'Access; Local_Anon_Acc : access Integer := A; -- OK begin Acc_I_1 := A; -- ERROR (implicit conversion of access parameter) if A in Acc_Integer then I := A.all; end if; Nested_Acc_Int := Nested_Acc_Integer (A); -- OK if A in Nested_Acc_Integer then I := A.all; end if; end Proc; procedure Other_Proc (A : Acc_Integer) is Nested_Anon_Acc_I : access Integer := A; -- OK type Nested_Rec is record A : access Integer; end record; Nested_R : Nested_Rec; Local_Anon_Acc : access Integer := Nested_Anon_Acc_I; -- OK begin Acc_I_1 := Nested_Anon_Acc_I; -- ERROR: accessibility level violation Acc_I_1 := Nested_R.A; -- ERROR: accessibility level violation Acc_I_1 := Acc_Integer (Nested_R.A); -- ERROR: illegal conversion if Nested_R.A /= null then Other_Proc (Nested_R.A); -- ERROR: accessibility level violation end if; if Nested_R.A in Acc_Integer then -- OK (legal, but should it be?) I := Nested_R.A.all; end if; if Nested_Anon_Acc_I in Acc_Integer then -- OK (legal, but should it be?) I := Nested_Anon_Acc_I.all; end if; if Nested_Anon_Acc_I = Anon_Acc_I_1 then -- OK (unambiguous) I := 123; end if; if Nested_R.A = Nested_R.A then -- OK (unambiguous) I := 123; end if; end Other_Proc; begin Other_Proc (R.A); -- OK Other_Proc (Anon_Acc_I_1); -- ERROR Acc_I_1 := Anon_Acc_I_1; -- ERROR (implicit conversion of stand-alone obj) if Anon_Acc_I_1 in Acc_Integer then -- OK I := Anon_Acc_I_1.all; end if; end AI05_0149_Test_Errors; Tested on x86_64-pc-linux-gnu, committed on trunk 2011-08-30 Gary Dismukes dismu...@adacore.com * sem_ch6.adb (Check_Return_Subtype_Indication): Issue error if the return object has an anonymous access type and the function's type is a named access type. * sem_ch8.adb (Analyze_Object_Renaming): Suppress error about renaming conversions on implicit conversions, since such conversions can occur for anonymous access cases due to expansion. Issue error for attempt to rename an anonymous expression as an object of a named access type. * sem_res.ads (Valid_Conversion): Add defaulted parameter Report_Errs, to indicate whether this function should report errors on invalid conversions. * sem_res.adb (Resolve): For Ada 2012, in the case where the type of the expression is
Re: [4/4] Make SMS schedule register moves
Richard Guenther richard.guent...@gmail.com writes: On Tue, Aug 30, 2011 at 2:43 PM, Richard Sandiford richard.sandif...@linaro.org wrote: Richard Guenther richard.guent...@gmail.com writes: On Tue, Aug 30, 2011 at 2:29 PM, Richard Sandiford richard.sandif...@linaro.org wrote: This is the move-scheduling patch itself. It should be fairly self-explanatory. Let me know if it isn't, and I'll try to improve the commentary. Can you add some testcases? I don't think it's an easy thing to test for. E.g. with the resampling loop in the covering message, there might well be a reasonable ii=27 schedule that doesn't need as many moves. So, does it only improve code generation or does it expose more loops as SMS candidates? If the former, ok ... Yeah, it just improves code generation. The code I'm adding only kicks in once we've found a successful SMS schedule. At the moment, once we've found that kind of schedule, we always emit it, regardless of how many moves it needs. The new code instead allows the schedule to be rejected. So from that point of view, it reduces the number of SMS candidates (but hopefully only in cases where we would otherwise generate worse code). Richard
[Ada] Ada 2012 accessibility of anonymous access stand-alone objects
This set of changes implements support for AI05-0148, the Ada2012 rules concerting the accessibility of a stand-alone object of an anonymous access type (hereafter, a saooaaat). The Extra_Accessibility attribute was previously only used for a formal parameter of an anonymous access type. The use of this attribute is generalized so that this attribute is set for any Ada-2012 saooaaat which is not declared at library level. In this case, an object containing the current accessibility level of the saooaaat is also declared. The Extra_Accessibility attribute of the saooaaat refers to this object and the Is_Local_Anonymous_Access attribute is set to False for the anonymous access type. When the object is updated (either by an assignment statement or by parameter copy-back), the associated Extra_Accessibility object is also updated. An accessibility check is generated to ensure that the new value is not greater than the (static) accessibility level of the saooaaat. When the dynamic accessibility level of the anonymous access type is needed, the value of the Extra_Accessibility object is used. The two attributes RM_Size (defined on types) and Extra_Accessibility (defined on objects) share storage, so it is now more important to avoid accessing the RM_Size attribute of an object. The following tests are intended to test these changes. The first (AI05_0148_Test1) should execute without producing output; any exceptions raised should be handled within the program. The second (AI05_0148_Test2) should fail to compile and the lines ending in -- illegal comments should be flagged as containing errors. procedure AI05_0148_Test1 is subtype Designated is Integer; procedure Assert (Condition : Boolean) is Test_Failed : exception; begin if not Condition then raise Test_Failed; end if; end Assert; Aaa, Bbb : aliased Designated := 123; Ptr1 : access Designated := Aaa'Access; type Named1 is access all Designated; for Named1'Storage_Size use 0; procedure Test_Assignment is Ccc : aliased Designated := 456; Ptr2 : access Designated := Bbb'Access; begin for Exception_Expected in Boolean loop begin Ptr1 := Ptr2; Assert (not Exception_Expected); exception when Program_Error = Assert (Exception_Expected); end; Ptr2 := Ccc'Access; end loop; Assert (Ptr1 = Bbb'Access); Ptr1 := Aaa'Access; end Test_Assignment; procedure Test_Rename_Assignment is Ccc : aliased Designated := 456; Ptr2 : access Designated := Bbb'Access; begin for Exception_Expected in Boolean loop declare Intermediate_1 : access Designated renames Ptr1; Ptr1_Ren : access Designated renames Intermediate_1; Intermediate_2 : access Designated renames Ptr2; Ptr2_Ren : access Designated renames Intermediate_2; begin Ptr1_Ren := Ptr2_Ren; Assert (not Exception_Expected); exception when Program_Error = Assert (Exception_Expected); end; Ptr2 := Ccc'Access; end loop; Assert (Ptr1 = Bbb'Access); Ptr1 := Aaa'Access; end Test_Rename_Assignment; procedure Test_Copy_Back is type Named2 is access all Designated; for Named2'Storage_Size use 0; Ptr2 : access Designated; procedure Assign1 (Lhs1 : out Named1; Rhs1 : Named1) is begin Lhs1 := Rhs1; end Assign1; procedure Assign2 (Lhs2 : out Named2; Rhs2 : Named2) is begin Lhs2 := Rhs2; end Assign2; begin Assign1 (Named1 (Ptr2), Bbb'Access); for Exception_Expected in Boolean loop begin Ptr1 := Ptr2; Assert (not Exception_Expected); exception when Program_Error = Assert (Exception_Expected); end; Assign2 (Named2 (Ptr2), Aaa'Access); end loop; Assert (Ptr1 = Bbb'Access); Ptr1 :=
Re: [PATCH, i386, testsuite] FMA intrinsics
On Tue, Aug 30, 2011 at 2:42 AM, Ilya Tocar tocarip.in...@gmail.com wrote: Fixed. 2011/8/26 H.J. Lu hjl.to...@gmail.com: On Fri, Aug 26, 2011 at 8:47 AM, H.J. Lu hjl.to...@gmail.com wrote: On Fri, Aug 26, 2011 at 8:06 AM, Ilya Tocar tocarip.in...@gmail.com wrote: Done. Also fixed changelog: 2011-08-26 Ilya Tocar ilya.to...@intel.com * config/i386/fmaintrin.h: New. * config.gcc: Add fmaintrin.h. * config/i386/i386.c (enum ix86_builtins) IX86_BUILTIN_VFMADDSS3: New. IX86_BUILTIN_VFMADDSD3: Likewise. * config/i386/sse.md (fmai_vmfmadd_mode): New. (*fmai_fmadd_mode): Likewise. (*fmai_fmsub_mode): Likewise. (*fmai_fnmadd_mode): Likewise. (*fmai_fnmsub_mode): Likewise. * config/i386/immintrin.h: Add fmaintrin.h. -- +++ b/gcc/config/i386/fmaintrin.h @@ -0,0 +1,229 @@ +/* Copyright (C) 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + It should be just 2011. Also lines in fmaintrin.h are too long. I prefer 72 columns. Your patch won't apply. Please merge with master first and regenerate it. -- H.J.
[Ada] Define a light expansion mode for formal verification
Instead of the full expansion targetting code generation, a light expansion is
now used in formal verification mode. Light expansion has three main objectives:
1. Perform limited expansion to explicit some Ada rules and constructs
2. Facilitate treatment for the formal verification back-end
3. Avoid the introduction of low-level code that is difficult to analyze
formally, as typically done in the full expansion for high-level
constructs (tasking, dispatching)
Also remove special exits from full expansion that were previously needed.
Note that this is an intermediate step/change. A better/cleaner approach
will follow using exp_alfa.ad{s,b} files.
Tested on x86_64-pc-linux-gnu, committed on trunk
2011-08-30 Yannick Moy m...@adacore.com
* exp_aggr.adb, exp_ch11.adb, exp_prag.adb: Remove early exit during
expansion in Alfa mode.
* exp_ch6.adb, exp_ch6.ads (Expand_Actuals): Make subprogram public.
* exp_light.adb, exp_light.ads: New package defining light expansion.
* expander.adb (Expand): Call light expansion in Alfa mode
* exp_ch6_light.adb, exp_ch6_light.ads: Light expansion of chapter 6
constructs.
* exp_ch7_light.adb, exp_ch7_light.ads: Light expansion of chapter 7
constructs.
* exp_attr_light.adb, exp_attr_light.ads: Light expansion of attributes
* gnat1drv.adb (Adjust_Global_Switches): Comment
Index: exp_prag.adb
===
--- exp_prag.adb(revision 178293)
+++ exp_prag.adb(working copy)
@@ -321,15 +321,6 @@
-- be an explicit conditional in the source, not an implicit if, so we
-- do not call Make_Implicit_If_Statement.
- -- In formal verification mode, we keep the pragma check in the code,
- -- and its enclosed expression is not expanded. This requires that no
- -- transient scope is introduced for pragma check in this mode in
- -- Exp_Ch7.Establish_Transient_Scope.
-
- if ALFA_Mode then
- return;
- end if;
-
-- Case where we generate a direct raise
if ((Debug_Flag_Dot_G
Index: exp_ch6_light.adb
===
--- exp_ch6_light.adb (revision 0)
+++ exp_ch6_light.adb (revision 0)
@@ -0,0 +1,193 @@
+--
+-- --
+-- GNAT COMPILER COMPONENTS --
+-- --
+-- E X P _ C H 6 _ L I G H T--
+-- --
+-- B o d y --
+-- --
+-- Copyright (C) 2011, Free Software Foundation, Inc. --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --
+-- for more details. You should have received a copy of the GNU General --
+-- Public License distributed with GNAT; see file COPYING3. If not, go to --
+-- http://www.gnu.org/licenses for a complete copy of the license. --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+--
+
+with Atree;use Atree;
+with Einfo;use Einfo;
+with Exp_Ch6; use Exp_Ch6;
+with Exp_Dbug; use Exp_Dbug;
+with Rtsfind; use Rtsfind;
+with Sem_Aux; use Sem_Aux;
+with Sem_Res; use Sem_Res;
+with Sinfo;use Sinfo;
+with Stand;use Stand;
+with Tbuild; use Tbuild;
+
+package body Exp_Ch6_Light is
+
+ ---
+ -- Local Subprograms --
+ ---
+
+ procedure Expand_Simple_Function_Return (N : Node_Id);
+ -- Expand simple return from function
+
+ ---
+ -- Expand_Light_Call --
+ ---
+
+ procedure Expand_Light_Call (N : Node_Id) is
+ Call_Node : constant Node_Id := N;
+ Parent_Subp : Entity_Id;
+ Subp
[Ada] Add support to detect conflicting overriding primitive
This patch incorporates support in the compiler to detect conflicts in declarations of primitives of concurrent tagged types (see full documentation in AI05-0090-1). In addition the patch also performs a minor code cleanup in order to factorize the code which reports an error on wrong formal of protected type entity. After this patch the following test must report an error. package Synch_Pkg is type Synch_Interface is synchronized interface; end Synch_Pkg; with Synch_Pkg; use Synch_Pkg; package Task_Pkg is task type Task_Type is new Synch_Interface with entry Other_Prim; end Task_Type; procedure Other_Prim (Tsk : in out Task_Type); -- Legal? (No.) end Task_Pkg; Command: gcc -c -gnat05 task_pkg.ads task_pkg.ads:8:14: Other_Prim conflicts with declaration at line 5 Tested on x86_64-pc-linux-gnu, committed on trunk 2011-08-30 Javier Miranda mira...@adacore.com * sem_ch3.adb (Check_Abstract_Overriding): Code cleanup: replace code which emits an error by a call to a new routine which report the error. * exp_ch9.adb (Build_Wrapper_Spec): Build the wrapper even if the entity does not cover an existing interface. * errout.ads, errout.adb (Error_Msg_PT): New routine. Used to factorize code. * sem_ch6.adb (Check_Conformance): Add specific error for wrappers of protected procedures or entries whose mode is not conformant. (Check_Synchronized_Overriding): Code cleanup: replace code which emits an error by a call to a new routine which report the error. Index: sem_ch3.adb === --- sem_ch3.adb (revision 178305) +++ sem_ch3.adb (working copy) @@ -9162,9 +9162,6 @@ -- The controlling formal of Subp must be of mode out, -- in out or an access-to-variable to be overridden. - -- Error message below needs rewording (remember comma - -- in -gnatj mode) ??? - if Ekind (First_Formal (Subp)) = E_In_Parameter and then Ekind (Subp) /= E_Function then @@ -9172,12 +9169,7 @@ and then Is_Protected_Type (Corresponding_Concurrent_Type (T)) then -Error_Msg_NE - (first formal of must be of mode `OUT`, - `IN OUT` or access-to-variable, T, Subp); -Error_Msg_N - (\in order to be overridden by protected procedure -or entry (RM 9.4(11.9/2)), T); +Error_Msg_PT (T, Subp); end if; -- Some other kind of overriding failure Index: exp_ch9.adb === --- exp_ch9.adb (revision 178304) +++ exp_ch9.adb (working copy) @@ -2263,14 +2263,42 @@ end loop Search; end if; - -- If the subprogram to be wrapped is not overriding anything or is not - -- a primitive declared between two views, do not produce anything. This - -- avoids spurious errors involving overriding. + -- Ada 2012 (AI05-0090-1): If no interface primitive is covered by + -- this subprogram and this is not a primitive declared between two + -- views then force the generation of a wrapper. As an optimization, + -- previous versions of the frontend avoid generating the wrapper; + -- however, the wrapper facilitates locating and reporting an error + -- when a duplicate declaration is found later. See example in + -- AI05-0090-1. if No (First_Param) and then not Is_Private_Primitive_Subprogram (Subp_Id) then - return Empty; + if Is_Task_Type + (Corresponding_Concurrent_Type (Obj_Typ)) + then +First_Param := + Make_Parameter_Specification (Loc, +Defining_Identifier = + Make_Defining_Identifier (Loc, +Chars = Name_uO), +In_Present = True, +Out_Present= False, +Parameter_Type = New_Reference_To (Obj_Typ, Loc)); + + -- For entries and procedures of protected types the mode of + -- the controlling argument must be in-out. + + else +First_Param := + Make_Parameter_Specification (Loc, +Defining_Identifier = + Make_Defining_Identifier (Loc, +Chars = Name_uO), +In_Present = True, +Out_Present= (Ekind (Subp_Id) /= E_Function), +Parameter_Type = New_Reference_To (Obj_Typ, Loc)); + end if; end if; declare Index: errout.adb === ---
[Ada] Access all type not considered access-to-object in generic
This patch ensures that the full view of a designated type is available in the body of an instance when the related access type acts as an actual in another instance. Tested on x86_64-pc-linux-gnu, committed on trunk 2011-08-30 Hristian Kirtchev kirtc...@adacore.com * sem_ch12.adb (Check_Private_View): Exchange the private and full view of a designated type when the related access type is an actual in an instance. This ensures that the full view of designated type is available when inside the body of the instance. Index: sem_ch12.adb === --- sem_ch12.adb(revision 178307) +++ sem_ch12.adb(working copy) @@ -5749,12 +5749,17 @@ end if; -- For composite types with inconsistent representation exchange - -- component types accordingly. + -- component types accordingly. We exchange the private and full view + -- of a designated type when the related access type is an actual in + -- an instance. This ensures that the full view of designated type is + -- available when inside the body of the instance. + -- Is this right ??? elsif Is_Access_Type (T) and then Is_Private_Type (Designated_Type (T)) and then not Has_Private_View (N) and then Present (Full_View (Designated_Type (T))) + and then Used_As_Generic_Actual (T) then Switch_View (Designated_Type (T));
Re: [PATCH] Fix PR48571, remove (most) array-ref re-construction
On Tue, 30 Aug 2011, Richard Guenther wrote: I've run into PR48571 again, and after having fun with out data-dep analysis code I indeed believe that we should not try to re-construct ARRAY_REFs from code involving pointer arithmetic. ARRAY_REFs have constraints imposed on them that are relied on by data dependence analysis and that are indeed useful to have (the index is within bounds, otherwise undefined behavior). We can't recover from lowering that happened, much as Zdenek argued when I initially proposed to lower all ARRAY_REFs to pointer arithmetic with the original MEM_REF design. Thus, the following completes the partial removal of reference re-constructing I did when merging MEM_REFs (I removed the code re-constructing COMPONENT_REFs back then). Not much fallout, much to my surprise (I've tried it initially on the MEM_REF branch, but quickly gave up on this additional task). We've appearantly become better in handling of pointer based accesses (we've already much experience here with GFortran lowering multi-dimensional array accesses to one-dimensional ones). The patch XFAILs one -Warray-bounds testcase, the -Warray-bounds infrastructure needs some serious TLC which I didn't want to fold into this patch. The testcase in question also really asks for an 'access outside of object' warning, similar to the 'offset outside bounds of constant string' one we have. Bootstrapped and tested an earlier version on x86_64-unknown-linux-gnu, a final bootstrap and regtest cycle is currently running. (yes, there are still tree-ssa-forwprop.c:forward_propagate_addr_into_variable_array_index and fold-const.c:try_move_mult_to_index) Actually I forgot * gcc.dg/tree-ssa/ssa-ccp-25.c: Remove. * gcc.dg/tree-ssa/ssa-ccp-26.c: Likewise. which are feature tests for the reconstruction. Likewise I missed a recalculate_side_effects (*expr_p) in POINTER_PLUS_EXPR gimplification. With both fixed, bootstrapped and tested on x86_64-unknown-linxu-gnu and applied to trunk. Richard.
[Ada] Do not catch exception if _UA_FORCE_UNWIND flag is set.
Fix a non-compliance with the unwind ABI.
No pure Ada testcase.
Tested on x86_64-pc-linux-gnu, committed on trunk
2011-08-30 Tristan Gingold ging...@adacore.com
* raise-gcc.c: Never catch exception if _UA_FORCE_UNWIND flag is set,
to be compliant with the ABI.
Index: raise-gcc.c
===
--- raise-gcc.c (revision 178293)
+++ raise-gcc.c (working copy)
@@ -217,7 +217,7 @@
static void
db_phases (int phases)
{
- phase_descriptor *a = phase_descriptors;
+ const phase_descriptor *a = phase_descriptors;
if (! (db_accepted_codes() DB_PHASES))
return;
@@ -901,6 +901,7 @@
static void
get_action_description_for (_Unwind_Context *uw_context,
_Unwind_Exception *uw_exception,
+_Unwind_Action uw_phase,
region_descriptor *region,
action_descriptor *action)
{
@@ -965,17 +966,22 @@
/* Positive filters are for regular handlers. */
else if (ar_filter 0)
{
- /* See if the filter we have is for an exception which matches
-the one we are propagating. */
- _Unwind_Ptr choice = get_ttype_entry_for (region, ar_filter);
+ /* Do not catch an exception if the _UA_FORCE_UNWIND flag is
+ passed (to follow the ABI). */
+ if (!(uw_phase _UA_FORCE_UNWIND))
+{
+ /* See if the filter we have is for an exception which
+ matches the one we are propagating. */
+ _Unwind_Ptr choice = get_ttype_entry_for (region, ar_filter);
- if (is_handled_by (choice, gnat_exception))
- {
- action-kind = handler;
- action-ttype_filter = ar_filter;
- action-ttype_entry = choice;
- return;
- }
+ if (is_handled_by (choice, gnat_exception))
+{
+ action-kind = handler;
+ action-ttype_filter = ar_filter;
+ action-ttype_entry = choice;
+ return;
+}
+}
}
/* Negative filter values are for C++ exception specifications.
@@ -1128,7 +1134,8 @@
/* Search the call-site and action-record tables for the action associated
with this IP. */
- get_action_description_for (uw_context, uw_exception, region, action);
+ get_action_description_for (uw_context, uw_exception, uw_phases,
+ region, action);
db_action_for (action, uw_context);
/* Whatever the phase, if there is nothing relevant in this frame,
Re: [PATCH, i386, testsuite] FMA intrinsics
On Tue, Aug 30, 2011 at 6:55 AM, Ilya Tocar tocarip.in...@gmail.com wrote: Little fix. 2011/8/30 Ilya Tocar tocarip.in...@gmail.com: Sorry. Regenerated. 2011/8/30 H.J. Lu hjl.to...@gmail.com: On Tue, Aug 30, 2011 at 2:42 AM, Ilya Tocar tocarip.in...@gmail.com wrote: Fixed. 2011/8/26 H.J. Lu hjl.to...@gmail.com: On Fri, Aug 26, 2011 at 8:47 AM, H.J. Lu hjl.to...@gmail.com wrote: On Fri, Aug 26, 2011 at 8:06 AM, Ilya Tocar tocarip.in...@gmail.com wrote: Done. Also fixed changelog: 2011-08-26 Ilya Tocar ilya.to...@intel.com * config/i386/fmaintrin.h: New. * config.gcc: Add fmaintrin.h. * config/i386/i386.c (enum ix86_builtins) IX86_BUILTIN_VFMADDSS3: New. IX86_BUILTIN_VFMADDSD3: Likewise. * config/i386/sse.md (fmai_vmfmadd_mode): New. (*fmai_fmadd_mode): Likewise. (*fmai_fmsub_mode): Likewise. (*fmai_fnmadd_mode): Likewise. (*fmai_fnmsub_mode): Likewise. * config/i386/immintrin.h: Add fmaintrin.h. -- +++ b/gcc/config/i386/fmaintrin.h @@ -0,0 +1,229 @@ +/* Copyright (C) 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + It should be just 2011. Also lines in fmaintrin.h are too long. I prefer 72 columns. Your patch won't apply. Please merge with master first and regenerate it. I checked it in for you. Thanks. -- H.J.
[Ada] Define full expansion flag to distinguish from reduced Alfa expansion
Minor refactoring to clarify where full expansion applies wrt Alfa mode. Tested on x86_64-pc-linux-gnu, committed on trunk 2011-08-30 Yannick Moy m...@adacore.com * opt.adb, opt.ads (Full_Expander_Active): New function defines a common shorthand for (Expander_Active and not ALFA_Mode) that can be used for testing full expansion, that is active expansion not in the reduced mode for Alfa * exp_ch4.adb, exp_ch9.adb, exp_disp.adb, sem_ch10.adb, sem_ch12.adb, sem_ch6.adb, sem_ch9.adb, sem_res.adb: Use newly defined flag instead of the verbose (Expander_Active and not ALFA_Mode) Index: exp_ch9.adb === --- exp_ch9.adb (revision 178310) +++ exp_ch9.adb (working copy) @@ -4904,9 +4904,7 @@ Ldecl2 : Node_Id; begin - if Expander_Active -and then not ALFA_Mode - then + if Full_Expander_Active then -- If we have no handled statement sequence, we may need to build -- a dummy sequence consisting of a null statement. This can be -- skipped if the trivial accept optimization is permitted. @@ -5227,9 +5225,7 @@ -- barrier just as a protected function, and discard the protected -- version of it because it is never called. - if Expander_Active -and then not ALFA_Mode - then + if Full_Expander_Active then B_F := Build_Barrier_Function (N, Ent, Prot); Func := Barrier_Function (Ent); Set_Corresponding_Spec (B_F, Func); @@ -5267,8 +5263,7 @@ -- condition does not reference any of the generated renamings -- within the function. - if Expander_Active - and then not ALFA_Mode + if Full_Expander_Active and then Scope (Entity (Cond)) /= Func then Set_Declarations (B_F, Empty_List); @@ -5320,12 +5315,6 @@ Tasknm : Node_Id; begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - Aggr := Make_Aggregate (Loc, Component_Associations = New_List); Count := 0; @@ -5457,12 +5446,6 @@ -- Start of processing for Expand_N_Accept_Statement begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - -- If accept statement is not part of a list, then its parent must be -- an accept alternative, and, as described above, we do not do any -- expansion for such accept statements at this level. @@ -5913,12 +5896,6 @@ T : Entity_Id; -- Additional status flag begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - Process_Statements_For_Controlled_Objects (Trig); Process_Statements_For_Controlled_Objects (Abrt); @@ -6868,12 +6845,6 @@ S : Entity_Id; -- Primitive operation slot begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - Process_Statements_For_Controlled_Objects (N); if Ada_Version = Ada_2005 @@ -7190,12 +7161,6 @@ procedure Expand_N_Delay_Relative_Statement (N : Node_Id) is Loc : constant Source_Ptr := Sloc (N); begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - Rewrite (N, Make_Procedure_Call_Statement (Loc, Name = New_Reference_To (RTE (RO_CA_Delay_For), Loc), @@ -7215,12 +7180,6 @@ Typ : Entity_Id; begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - if Is_RTE (Base_Type (Etype (Expression (N))), RO_CA_Time) then Typ := RTE (RO_CA_Delay_Until); else @@ -7241,12 +7200,6 @@ procedure Expand_N_Entry_Body (N : Node_Id) is begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - -- Associate discriminals with the next protected operation body to be -- expanded. @@ -7268,12 +7221,6 @@ Index : Node_Id; begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - if No_Run_Time_Mode then Error_Msg_CRT (entry call, N); return; @@ -7330,12 +7277,6 @@ Acc_Ent: Entity_Id; begin - -- Do not expand tasking constructs in formal verification mode - - if ALFA_Mode then - return; - end if; - Formal := First_Formal (Entry_Ent); Last_Decl := N; @@ -7604,12 +7545,6 @@ -- Start of processing for Expand_N_Protected_Body
[Ada] Renames System.Parameter.Sec_Stack_Ratio
As this constant was a percentage, it is now renamed to Sec_Stack_Percentage. No functional change. Tested on x86_64-pc-linux-gnu, committed on trunk 2011-08-30 Tristan Gingold ging...@adacore.com * s-parame-vms-alpha.ads, s-parame-hpux.ads, s-tassta.adb, s-tarest.adb, s-parame-vms-ia64.ads, s-soflin.adb, s-secsta.adb, s-secsta.ads, s-parame.ads, s-parame-vxworks.ads: Renames Ratio to Percentage, and Sec_Stack_Ratio to Sec_Stack_Percentage. Index: s-parame-vms-alpha.ads === --- s-parame-vms-alpha.ads (revision 178293) +++ s-parame-vms-alpha.ads (working copy) @@ -6,7 +6,7 @@ -- -- -- S p e c -- -- -- --- Copyright (C) 1992-2010, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2011, Free Software Foundation, Inc. -- -- -- -- GNAT is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -62,7 +62,7 @@ Unspecified_Size : constant Size_Type := Size_Type'First; -- Value used to indicate that no size type is set - subtype Ratio is Size_Type range -1 .. 100; + subtype Percentage is Size_Type range -1 .. 100; Dynamic : constant Size_Type := -1; -- The secondary stack ratio is a constant between 0 and 100 which -- determines the percentage of the allocated task stack that is @@ -70,10 +70,10 @@ -- The special value of minus one indicates that the secondary -- stack is to be allocated from the heap instead. - Sec_Stack_Ratio : constant Ratio := Dynamic; + Sec_Stack_Percentage : constant Percentage := Dynamic; -- This constant defines the handling of the secondary stack - Sec_Stack_Dynamic : constant Boolean := Sec_Stack_Ratio = Dynamic; + Sec_Stack_Dynamic : constant Boolean := Sec_Stack_Percentage = Dynamic; -- Convenient Boolean for testing for dynamic secondary stack function Default_Stack_Size return Size_Type; Index: s-parame-hpux.ads === --- s-parame-hpux.ads (revision 178293) +++ s-parame-hpux.ads (working copy) @@ -6,7 +6,7 @@ -- -- -- S p e c -- -- -- --- Copyright (C) 1992-2010, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2011, Free Software Foundation, Inc. -- -- -- -- GNAT is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -62,7 +62,7 @@ Unspecified_Size : constant Size_Type := Size_Type'First; -- Value used to indicate that no size type is set - subtype Ratio is Size_Type range -1 .. 100; + subtype Percentage is Size_Type range -1 .. 100; Dynamic : constant Size_Type := -1; -- The secondary stack ratio is a constant between 0 and 100 which -- determines the percentage of the allocated task stack that is @@ -70,10 +70,10 @@ -- The special value of minus one indicates that the secondary -- stack is to be allocated from the heap instead. - Sec_Stack_Ratio : constant Ratio := Dynamic; + Sec_Stack_Percentage : constant Percentage := Dynamic; -- This constant defines the handling of the secondary stack - Sec_Stack_Dynamic : constant Boolean := Sec_Stack_Ratio = Dynamic; + Sec_Stack_Dynamic : constant Boolean := Sec_Stack_Percentage = Dynamic; -- Convenient Boolean for testing for dynamic secondary stack function Default_Stack_Size return Size_Type; Index: s-tassta.adb === --- s-tassta.adb(revision 178293) +++ s-tassta.adb(working copy) @@ -1023,7 +1023,7 @@ Secondary_Stack_Size : constant SSE.Storage_Offset := Self_ID.Common.Compiler_Data.Pri_Stack_Info.Size * - SSE.Storage_Offset (Parameters.Sec_Stack_Ratio) / 100; + SSE.Storage_Offset (Parameters.Sec_Stack_Percentage) / 100; Secondary_Stack : aliased SSE.Storage_Array (1 .. Secondary_Stack_Size); Index: s-tarest.adb === --- s-tarest.adb(revision 178293) +++ s-tarest.adb(working copy) @@ -6,7 +6,7 @@ -- -- --
[Ada] Define a light expansion mode for formal verification (2)
Following up on the previous change, we now move all the formal verification expansion in a separate exp_alfa.ad? file. Previous exp_*_light change is reverted/canceled at the same time (not shown here for convenience). Instead of the full expansion targetting code generation, a light expansion now used in formal verification mode. Light expansion has three main objectives: 1. Perform limited expansion to explicit some Ada rules and constructs 2. Facilitate treatment for the formal verification back-end 3. Avoid the introduction of low-level code that is difficult to analyze formally, as typically done in the full expansion for high-level constructs (tasking, dispatching) Also remove special exits from full expansion that were previously needed. Tested on x86_64-pc-linux-gnu, committed on trunk 2011-08-30 Yannick Moy m...@adacore.com * exp_aggr.adb, exp_ch11.adb, exp_prag.adb: Remove early exit during expansion in Alfa mode. * exp_ch6.adb, exp_ch6.ads (Expand_Actuals): Make subprogram public * exp_alfa.adb, exp_alfa.ads: New package defining light expansion for Alfa mode. * gnat1drv.adb (Adjust_Global_Switches): Update Comment. * sem_res.adb: Ditto. Index: exp_prag.adb === --- exp_prag.adb(revision 178316) +++ exp_prag.adb(working copy) @@ -321,15 +321,6 @@ -- be an explicit conditional in the source, not an implicit if, so we -- do not call Make_Implicit_If_Statement. - -- In formal verification mode, we keep the pragma check in the code, - -- and its enclosed expression is not expanded. This requires that no - -- transient scope is introduced for pragma check in this mode in - -- Exp_Ch7.Establish_Transient_Scope. - - if ALFA_Mode then - return; - end if; - -- Case where we generate a direct raise if ((Debug_Flag_Dot_G Index: exp_alfa.adb === --- exp_alfa.adb(revision 0) +++ exp_alfa.adb(revision 0) @@ -0,0 +1,270 @@ +-- +-- -- +-- GNAT COMPILER COMPONENTS -- +-- -- +-- E X P _ A L F A -- +-- -- +-- B o d y -- +-- -- +-- Copyright (C) 2011, Free Software Foundation, Inc. -- +-- -- +-- GNAT is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- +-- for more details. You should have received a copy of the GNU General -- +-- Public License distributed with GNAT; see file COPYING3. If not, go to -- +-- http://www.gnu.org/licenses for a complete copy of the license. -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +-- + +with Atree;use Atree; +with Einfo;use Einfo; +with Exp_Attr; use Exp_Attr; +with Exp_Ch6; use Exp_Ch6; +with Exp_Dbug; use Exp_Dbug; +with Rtsfind; use Rtsfind; +with Sem_Aux; use Sem_Aux; +with Sem_Res; use Sem_Res; +with Sinfo;use Sinfo; +with Snames; use Snames; +with Stand;use Stand; +with Tbuild; use Tbuild; + +package body Exp_Alfa is + + --- + -- Local Subprograms -- + --- + + procedure Expand_Alfa_Call (N : Node_Id); + -- This procedure contains common processing for function and procedure + -- calls: + -- * expansion of actuals to introduce necessary temporaries + -- * replacement of renaming by subprogram renamed + + procedure Expand_Alfa_N_Attribute_Reference (N : Node_Id); + -- Expand attributes 'Old and 'Result only + + procedure Expand_Alfa_N_Package_Declaration (N : Node_Id); + -- Fully qualify
Re: [PATCH][ARM] Thumb2 replicated constants
On 26/08/11 11:03, Andrew Stubbs wrote:
There was a bug I found in final testing, so this has been delayed
somewhat.
I've just committed this version. There are a few minor changes to the
way negative/inverted constants are generated.
Bernd found another bug whist testing for arm. Apparently there was a
bug that didn't show up in my thumb tests, although I have no clue why?
Anyway, fixed thusly and committed as obvious (and urgent).
Andrew
2011-08-30 Andrew Stubbs a...@codesourcery.com
gcc/
* config/arm/arm.c (arm_gen_constant): Set can_negate correctly
when code is SET.
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3367,8 +3367,8 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
if (code == SET)
{
+ can_negate = can_invert;
can_invert = 0;
- can_negate = 1;
code = PLUS;
}
else if (code == MINUS)
Re: [C++0x] contiguous bitfields race implementation
[I'm going to respond to this piece-meal, to make sure I don't drop
anything. My apologies for the long thread, but I'm pretty sure it's in
everybody's kill file by now.]
+ /* Be as conservative as possible on variable offsets. */
+ if (TREE_OPERAND (exp, 2)
+ !host_integerp (TREE_OPERAND (exp, 2), 1))
+{
+ *byte_offset = TREE_OPERAND (exp, 2);
+ *maxbits = BITS_PER_UNIT;
+ return;
+}
shouldn't this be at the very beginning of the function? Because
you've set *bit_offset to an offset that was _not_ calculated relative
Sure. I assume in this case, *bit_offset would be 0, right?
Re: [PATCH][ARM] Thumb2 replicated constants
On 30/08/11 15:32, Andrew Stubbs wrote:
On 26/08/11 11:03, Andrew Stubbs wrote:
There was a bug I found in final testing, so this has been delayed
somewhat.
I've just committed this version. There are a few minor changes to the
way negative/inverted constants are generated.
Bernd found another bug whist testing for arm. Apparently there was a
bug that didn't show up in my thumb tests, although I have no clue why?
Anyway, fixed thusly and committed as obvious (and urgent).
And also there was an issue build with -Werror ... I'm not having much
luck at the moment. :(
Anyway, likewise fixed and committed as obvious.
Andrew
2011-08-30 Andrew Stubbs a...@codesourcery.com
gcc/
* config/arm/arm.c (optimal_immediate_sequence_1): Make b1, b2,
b3 and b4 unsigned.
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2624,7 +2624,7 @@ optimal_immediate_sequence_1 (enum rtx_code code, unsigned HOST_WIDE_INT val,
do
{
int end;
- int b1, b2, b3, b4;
+ unsigned int b1, b2, b3, b4;
unsigned HOST_WIDE_INT result;
int loc;
C++ PATCH for c++/50220 (ICE with capture by copy of reference)
In this testcase, we weren't instantiating Foobarvoid until fairly
late, so the field and proxy variable didn't have a size, leading to
madness.
Tested x86_64-pc-linux-gnu, applying to trunk and 4.6.
commit 7082532a480501ab8f8f99bc62589a9045da303a
Author: Jason Merrill ja...@redhat.com
Date: Tue Aug 30 10:38:52 2011 -0400
PR c++/50220
* semantics.c (add_capture): Call complete_type for copy.
diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c
index 1ad991f..dd7c013 100644
--- a/gcc/cp/semantics.c
+++ b/gcc/cp/semantics.c
@@ -8651,6 +8651,9 @@ add_capture (tree lambda, tree id, tree initializer, bool by_reference_p,
if (!real_lvalue_p (initializer))
error (cannot capture %qE by reference, initializer);
}
+ else
+/* Capture by copy requires a complete type. */
+type = complete_type (type);
/* Add __ to the beginning of the field name so that user code
won't find the field with name lookup. We can't just leave the name
diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-50220.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-50220.C
new file mode 100644
index 000..240143c
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-50220.C
@@ -0,0 +1,9 @@
+// PR c++/50220
+// { dg-options -std=c++0x }
+
+templatetypename Foo struct Foobar {};
+
+void foobar(const Foobarvoid obj)
+{
+ [obj](){}();
+}
C++ PATCH for c++/50234 (ICE with constexpr and empty init-list)
This is basically the same as c++/49924, but for classes instead of
arrays: if there is no explicit initializer written in the init-list,
the member is value-initialized.
Tested x86_64-pc-linux-gnu, applying to trunk and 4.6.
commit eccc1f7f9987a394dcf9856d43244a95c51bc880
Author: Jason Merrill ja...@redhat.com
Date: Tue Aug 30 10:28:05 2011 -0400
PR c++/50234
* semantics.c (cxx_eval_component_reference): Handle
value-initialization for omitted initializers.
diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c
index 07f53b5..1ad991f 100644
--- a/gcc/cp/semantics.c
+++ b/gcc/cp/semantics.c
@@ -6518,7 +6518,8 @@ cxx_eval_component_reference (const constexpr_call *call, tree t,
if (field == part)
return value;
}
- if (TREE_CODE (TREE_TYPE (whole)) == UNION_TYPE)
+ if (TREE_CODE (TREE_TYPE (whole)) == UNION_TYPE
+ CONSTRUCTOR_NELTS (whole) 0)
{
/* DR 1188 says we don't have to deal with this. */
if (!allow_non_constant)
@@ -6527,8 +6528,12 @@ cxx_eval_component_reference (const constexpr_call *call, tree t,
*non_constant_p = true;
return t;
}
- gcc_unreachable();
- return error_mark_node;
+
+ /* If there's no explicit init for this field, it's value-initialized. */
+ value = build_value_init (TREE_TYPE (t), tf_warning_or_error);
+ return cxx_eval_constant_expression (call, value,
+ allow_non_constant, addr,
+ non_constant_p);
}
/* Subroutine of cxx_eval_constant_expression.
diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-value3.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-value3.C
new file mode 100644
index 000..38d8993
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-value3.C
@@ -0,0 +1,10 @@
+// PR c++/50234
+// { dg-options -std=c++0x }
+
+#define SA(X) static_assert((X),#X)
+
+struct A { int i; };
+
+constexpr int f(A a) { return a.i; }
+
+SA(f({}) == 0);
Re: [PATCH, PR fortran/45170] -- properly translates substring reference
On Sun, Aug 28, 2011 at 11:36:42PM +0200, Mikael Morin wrote: On Saturday 27 August 2011 02:34:24 Steve Kargl wrote: The attached patch allows gfortran to compile the attached testcase. The resulting executable runs as expected. Short story: character(len=20) :: string = 'some text here' character(len=:), allocatable :: s n = 5 allocate(s, source=string(:n)) The length of s is determined from the expression in the source= argument. If this expression is a lonely substring reference as in the above, then gfortran does set the correct length. This patch fixes this. ... does *not* set the correct length, I suppose? OK for trunk? It is OK. Rather obvious. Thanks Thanks. Committed revision 178329. -- Steve
[v3] Implement DR 2061 (Ready in Bloomington)
Hi,
tested x86_64-linux, committed.
Paolo.
///
2011-08-30 Paolo Carlini paolo.carl...@oracle.com
* include/bits/stl_iterator.h (make_move_iterator): Implement DR2061.
* testsuite/24_iterators/move_iterator/dr2061.cc: New.
* testsuite/20_util/weak_ptr/comparison/cmp_neg.cc: Adjust dg-warning
line numbers.
Index: include/bits/stl_iterator.h
===
--- include/bits/stl_iterator.h (revision 178320)
+++ include/bits/stl_iterator.h (working copy)
@@ -1,6 +1,7 @@
// Iterators -*- C++ -*-
-// Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+// Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
+// 2010, 2011
// Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
@@ -1115,7 +1116,7 @@
templatetypename _Iterator
inline move_iterator_Iterator
-make_move_iterator(const _Iterator __i)
+make_move_iterator(_Iterator __i)
{ return move_iterator_Iterator(__i); }
templatetypename _Iterator, typename _ReturnType
Index: testsuite/24_iterators/move_iterator/dr2061.cc
===
--- testsuite/24_iterators/move_iterator/dr2061.cc (revision 0)
+++ testsuite/24_iterators/move_iterator/dr2061.cc (revision 0)
@@ -0,0 +1,29 @@
+// { dg-options -std=gnu++0x }
+// { dg-do compile }
+
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// http://www.gnu.org/licenses/.
+
+#include iterator
+
+// DR 2061
+void test01()
+{
+ int a[] = { 1, 2, 3, 4 };
+ std::make_move_iterator(a + 4);
+ std::make_move_iterator(a);
+}
Index: testsuite/20_util/weak_ptr/comparison/cmp_neg.cc
===
--- testsuite/20_util/weak_ptr/comparison/cmp_neg.cc(revision 178320)
+++ testsuite/20_util/weak_ptr/comparison/cmp_neg.cc(working copy)
@@ -52,8 +52,8 @@
// { dg-warning note { target *-*-* } 479 }
// { dg-warning note { target *-*-* } 468 }
// { dg-warning note { target *-*-* } 829 }
-// { dg-warning note { target *-*-* } 1055 }
-// { dg-warning note { target *-*-* } 1049 }
-// { dg-warning note { target *-*-* } 341 }
-// { dg-warning note { target *-*-* } 291 }
+// { dg-warning note { target *-*-* } 1056 }
+// { dg-warning note { target *-*-* } 1050 }
+// { dg-warning note { target *-*-* } 342 }
+// { dg-warning note { target *-*-* } 292 }
// { dg-warning note { target *-*-* } 224 }
Re: options generation and language count
On Mon, 29 Aug 2011, Gary Funck wrote: 1) The sanity check should probably read: gcc_assert ((1U cl_lang_count) = CL_MIN_OPTION_CLASS); In other words, it is off-by-one. Please send a patch. 2) The fixed shift counts starting at CL_PARAMS probably need to be adjusted upwards to allow for more languages. Plese send a patch. I moved lots of flags to bit-fields so there is now plenty of room to move flags up. A third problem, is that this sort of error would be better detected at build time rather than waiting to run a DejaGNU test to find it. Please send a patch. Making optc-gen.awk or opth-gen.awk output #if conditions surrounding a #error would be the usual approach. Also, the use of fixed masks is problematic. Perhaps the AWK script could be changed to also generate values for CL_PARAMS, etc., ensuring that will not conflict with the language mask values? That sounds riskier (and does everywhere using opts.h actually need the generated options.h as well?), although in principle it ought to be possible to assign this automatically (and actually only CL_DRIVER, CL_TARGET and CL_COMMON should really need bits assigned, though avoiding the others would require a --help rework). -- Joseph S. Myers jos...@codesourcery.com
Re: options generation and language count
On 08/30/11 15:52:12, Joseph S. Myers wrote: Please send a patch. [... on points 1, 2, and 3]0 OK, will do. GF: Also, the use of fixed masks is problematic. Perhaps the AWK script GF: could be changed to also generate values for CL_PARAMS, etc., ensuring GF: that will not conflict with the language mask values? That sounds riskier (and does everywhere using opts.h actually need the generated options.h as well?) It looks like many files include opts.h, but do not include options.h. although in principle it ought to be possible to assign this automatically (and actually only CL_DRIVER, CL_TARGET and CL_COMMON should really need bits assigned, though avoiding the others would require a --help rework). An alternative might be to move the fixed assignments (CL_DRIVER, CL_TARGET, CL_COMMON ...) down to start at the beginning of the range, (leaving room for a few more) and to start the auto-generated language mask bits above that? - Gary
Re: [C++0x] contiguous bitfields race implementation
*bit_offset is supposed to be relative to *byte_offset then it should be easy to calculate it without another get_inner_reference. Since, as you suggested, we will terminate early on variable length offsets, we can assume both DECL_FIELD_OFFSET and DECL_FIELD_BIT_OFFSET will be constants by now. So, I assume we can calculate the bit offset like this: *bit_offset = (TREE_INT_CST_LOW (DECL_FIELD_OFFSET (fld)) * BITS_PER_UNIT + TREE_INT_CST_LOW (DECL_FIELD_BIT_OFFSET (fld))) - (TREE_INT_CST_LOW (DECL_FIELD_OFFSET (bitregion_start)) * BITS_PER_UNIT + TREE_INT_CST_LOW (DECL_FIELD_BIT_OFFSET (bitregion_start))); (Yes, I know we can factor out the BITS_PER_UNIT and only do one multiplication, it's just easier to read this way.) Is this what you had in mind?
[Ada] Fix ICE on initialization with discriminated aggregate
The compiler aborts on the initialization of an object with an aggregate, if
its nominal subtype is a discriminated record type with a variant part for
which the variants all have the same size and one of the variants contains a
component whose type is tagged or controlled.
Tested on x86_64-suse-linux, applied on the mainline.
2011-08-30 Eric Botcazou ebotca...@adacore.com
* gcc-interface/decl.c (gnat_to_gnu_entity) object: Do not convert
the expression to the nominal type if the latter is a record type with
a variant part and the type of the former is a record type without one.
2011-08-30 Eric Botcazou ebotca...@adacore.com
* gnat.dg/specs/aggr3.ads: New test.
* gnat.dg/specs/aggr3_pkg.ads: New helper.
--
Eric Botcazou
Index: gcc-interface/decl.c
===
--- gcc-interface/decl.c (revision 178287)
+++ gcc-interface/decl.c (working copy)
@@ -1124,13 +1124,19 @@ gnat_to_gnu_entity (Entity_Id gnat_entit
is a padded record whose field is of self-referential size. In
the former case, converting will generate unnecessary evaluations
of the CONSTRUCTOR to compute the size and in the latter case, we
- want to only copy the actual data. */
+ want to only copy the actual data. Also don't convert to a record
+ type with a variant part from a record type without one, to keep
+ the object simpler. */
if (gnu_expr
TREE_CODE (gnu_type) != UNCONSTRAINED_ARRAY_TYPE
!CONTAINS_PLACEHOLDER_P (TYPE_SIZE (gnu_type))
!(TYPE_IS_PADDING_P (gnu_type)
CONTAINS_PLACEHOLDER_P
- (TYPE_SIZE (TREE_TYPE (TYPE_FIELDS (gnu_type))
+ (TYPE_SIZE (TREE_TYPE (TYPE_FIELDS (gnu_type)
+ !(TREE_CODE (gnu_type) == RECORD_TYPE
+ TREE_CODE (TREE_TYPE (gnu_expr)) == RECORD_TYPE
+ get_variant_part (gnu_type) != NULL_TREE
+ get_variant_part (TREE_TYPE (gnu_expr)) == NULL_TREE))
gnu_expr = convert (gnu_type, gnu_expr);
/* If this is a pointer that doesn't have an initializing expression,
@@ -1350,13 +1356,19 @@ gnat_to_gnu_entity (Entity_Id gnat_entit
is a padded record whose field is of self-referential size. In
the former case, converting will generate unnecessary evaluations
of the CONSTRUCTOR to compute the size and in the latter case, we
- want to only copy the actual data. */
+ want to only copy the actual data. Also don't convert to a record
+ type with a variant part from a record type without one, to keep
+ the object simpler. */
if (gnu_expr
TREE_CODE (gnu_type) != UNCONSTRAINED_ARRAY_TYPE
!CONTAINS_PLACEHOLDER_P (TYPE_SIZE (gnu_type))
!(TYPE_IS_PADDING_P (gnu_type)
CONTAINS_PLACEHOLDER_P
- (TYPE_SIZE (TREE_TYPE (TYPE_FIELDS (gnu_type))
+ (TYPE_SIZE (TREE_TYPE (TYPE_FIELDS (gnu_type)
+ !(TREE_CODE (gnu_type) == RECORD_TYPE
+ TREE_CODE (TREE_TYPE (gnu_expr)) == RECORD_TYPE
+ get_variant_part (gnu_type) != NULL_TREE
+ get_variant_part (TREE_TYPE (gnu_expr)) == NULL_TREE))
gnu_expr = convert (gnu_type, gnu_expr);
/* If this name is external or there was a name specified, use it,
-- { dg-do compile }
with Aggr3_Pkg; use Aggr3_Pkg;
package Aggr3 is
type Enum is (One);
type R (D : Enum := One) is
record
case D is
when One = The_T : T;
end case;
end record;
My_R : R := (D = One, The_T = My_T);
end Aggr3;
package Aggr3_Pkg is
type Root is abstract tagged null record;
type T is new Root with null record;
My_T : T;
end Aggr3_Pkg;
Re: [PATCH, committed] Change default for powerpc -msave-toc-indirect
On Tue, Aug 30, 2011 at 09:16:40AM +0200, Richard Guenther wrote: On Mon, Aug 29, 2011 at 11:32 PM, Michael Meissner meiss...@linux.vnet.ibm.com wrote: David asked me to reverse the default for the -msave-toc-indirect option, since it is buggy in a few cases, and in other places causes slowdowns if the function has an early exit before calling the indrect function. I also documented the switch. I did the usual bootstrap and make check with no regressions, and committed the patch. Was this switch available in 4.6.x? If so please document the change of the default in gcc-4.7/changes.html. No, the switch is not in the FSF 4.6 branch. When I first added it, I made the switch undocumented as a debugging switch, and I'm now documenting it. I will look to see if I need to update the 4.7 changes document. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
[Ada] Clean up and document use of IN_GCC outside the compiler
This cleans up and documents the use of IN_GCC in the GNAT build system.
No functional change. Tested on x86_64-suse-linux, applied on the mainline.
2011-08-30 Eric Botcazou ebotca...@adacore.com
* raise-gcc.c: Do not include coretypes.h and tm.h.
(setup_to_install): Remove test for compiler macro.
* targext.c: Document use for the library.
* gcc-interface/Makefile.in: Fix comment on the use of IN_GCC.
--
Eric Botcazou
Index: raise-gcc.c
===
--- raise-gcc.c (revision 178331)
+++ raise-gcc.c (working copy)
@@ -35,14 +35,6 @@
#ifdef IN_RTS
#include tconfig.h
#include tsystem.h
-/* In the top-of-tree GCC, tconfig does not include tm.h, but in GCC 3.2
- it does. To avoid branching raise.c just for that purpose, we kludge by
- looking for a symbol always defined by tm.h and if it's not defined,
- we include it. */
-#ifndef FIRST_PSEUDO_REGISTER
-#include coretypes.h
-#include tm.h
-#endif
#include sys/stat.h
#include stdarg.h
typedef char bool;
@@ -1007,11 +999,6 @@ setup_to_install (_Unwind_Context *uw_co
_Unwind_Ptr uw_landing_pad,
int uw_filter)
{
-#ifndef EH_RETURN_DATA_REGNO
- /* We should not be called if the appropriate underlying support is not
- there. */
- abort ();
-#else
/* 1/ exception object pointer, which might be provided back to
_Unwind_Resume (and thus to this personality routine) if we are jumping
to a cleanup. */
@@ -1026,7 +1013,6 @@ setup_to_install (_Unwind_Context *uw_co
/* Setup the address we should jump at to reach the code where there is the
something we found. */
_Unwind_SetIP (uw_context, uw_landing_pad);
-#endif
}
/* The following is defined from a-except.adb. Its purpose is to enable
Index: targext.c
===
--- targext.c (revision 178331)
+++ targext.c (working copy)
@@ -31,7 +31,9 @@
/* This file contains target-specific parameters describing the file
extension for object and executable files. It is used by the compiler,
-binder and tools. */
+binder, library and tools.
+Note that, in order to have access to the TARGET_* macros used below,
+the file must be compiled with IN_GCC defined, even for the library. */
#ifdef __cplusplus
extern C {
Index: gcc-interface/Makefile.in
===
--- gcc-interface/Makefile.in (revision 178331)
+++ gcc-interface/Makefile.in (working copy)
@@ -223,8 +223,9 @@ endif
all.indirect: Makefile ../gnat1$(exeext)
-# IN_GCC distinguishes between code compiled into GCC itself and other
-# programs built during a bootstrap.
+# IN_GCC is meant to distinguish between code compiled into GCC itself, i.e.
+# for the host, and the rest. But we also use it for the tools (link.c) and
+# even break the host/target wall by using it for the library (targext.c).
# autoconf inserts -DCROSS_DIRECTORY_STRUCTURE if we are building a cross
# compiler which does not use the native libraries and headers.
INTERNAL_CFLAGS = @CROSS@ -DIN_GCC
[Ada] Housekeeping work in gigi (32/n)
Tested on x86_64-suse-linux, applied on the mainline.
2011-08-30 Eric Botcazou ebotca...@adacore.com
* gcc-interface/ada-tree.h (TYPE_EXTRA_SUBTYPE_P): Add internal check.
* gcc-interface/utils2.c (build_binary_op): Tighten condition.
(build_unary_op): Likewise.
--
Eric Botcazou
Index: gcc-interface/utils2.c
===
--- gcc-interface/utils2.c (revision 178331)
+++ gcc-interface/utils2.c (working copy)
@@ -544,7 +544,7 @@ build_binary_op (enum tree_code op_code,
operation_type = TREE_TYPE (TYPE_FIELDS (operation_type));
if (operation_type
- !AGGREGATE_TYPE_P (operation_type)
+ TREE_CODE (operation_type) == INTEGER_TYPE
TYPE_EXTRA_SUBTYPE_P (operation_type))
operation_type = get_base_type (operation_type);
@@ -1002,7 +1002,7 @@ build_unary_op (enum tree_code op_code,
operation_type = TREE_TYPE (TYPE_FIELDS (operation_type));
if (operation_type
- !AGGREGATE_TYPE_P (operation_type)
+ TREE_CODE (operation_type) == INTEGER_TYPE
TYPE_EXTRA_SUBTYPE_P (operation_type))
operation_type = get_base_type (operation_type);
Index: gcc-interface/ada-tree.h
===
--- gcc-interface/ada-tree.h (revision 178331)
+++ gcc-interface/ada-tree.h (working copy)
@@ -106,7 +106,7 @@ do { \
/* Nonzero in an arithmetic subtype if this is a subtype not known to the
front-end. */
-#define TYPE_EXTRA_SUBTYPE_P(NODE) TYPE_LANG_FLAG_2 (NODE)
+#define TYPE_EXTRA_SUBTYPE_P(NODE) TYPE_LANG_FLAG_2 (INTEGER_TYPE_CHECK (NODE))
/* For RECORD_TYPE, UNION_TYPE, and QUAL_UNION_TYPE, nonzero if this is the
type for an object whose type includes its template in addition to
Re: [PATCH, PR 49886] Prevent fnsplit from changing signature when there are type attributes
Ping. Re-bootstrapped and re-tested yesterday on x86_64-linux.
THanks,
Martin
On Fri, Jul 29, 2011 at 10:55:31PM +0200, Martin Jambor wrote:
Hi,
On Thu, Jul 28, 2011 at 06:52:05PM +0200, Martin Jambor wrote:
pass_split_functions is happy to split functions which have type
attributes but cannot update them if the new clone has in any way
different parameters than the original. This can lead to
miscompilations in cases like the testcase.
This patch solves it by 1) making the inliner set the
can_change_signature flag to false for them because their signature
cannot be changed (this step is also necessary to make IPA-CP operate
on them and handle them correctly), and 2) make the splitting pass
keep all parameters if the flag is set. The second step might involve
inventing some default definitions if the parameters did not really
have any.
I spoke about this with Honza and he claimed that the new function is
really an entirely different thing and that the parameters may
correspond only very loosely and thus the type attributes should be
cleared. I'm not sure I agree, but in any case I needed this to work
to allow me continue with promised IPA-CP polishing and so I decided
to do this because it was easier. (My own opinion is that the current
representation of parameter-describing function type attributes is
evil and will cause harm no matter hat we do.)
Actually, I'd like to commit the patch below which also clears
can_change_signature for BUILT_IN_VA_START. It is not really
necessary for this fix but fixes some problems in a followup patch and
is also the correct thing to do because if we clone a function calling
it and pass non-NULL for args_to_skip, the new clone would not have a
stdarg_p type and fold_builtin_next_arg could error when dealing with
it.
Also bootstrapped and tested on x86_64-linux. OK for trunk?
Thanks,
Martin
2011-07-29 Martin Jambor mjam...@suse.cz
PR middle-end/49886
* ipa-inline-analysis.c (compute_inline_parameters): Set
can_change_signature of noes with typde attributes.
* ipa-split.c (split_function): Do not skip any arguments if
can_change_signature is set.
* testsuite/gcc.c-torture/execute/pr49886.c: New testcase.
Index: src/gcc/ipa-inline-analysis.c
===
--- src.orig/gcc/ipa-inline-analysis.c
+++ src/gcc/ipa-inline-analysis.c
@@ -1658,18 +1658,28 @@ compute_inline_parameters (struct cgraph
/* Can this function be inlined at all? */
info-inlinable = tree_inlinable_function_p (node-decl);
- /* Inlinable functions always can change signature. */
- if (info-inlinable)
-node-local.can_change_signature = true;
+ /* Type attributes can use parameter indices to describe them. */
+ if (TYPE_ATTRIBUTES (TREE_TYPE (node-decl)))
+node-local.can_change_signature = false;
else
{
- /* Functions calling builtin_apply can not change signature. */
- for (e = node-callees; e; e = e-next_callee)
- if (DECL_BUILT_IN (e-callee-decl)
- DECL_BUILT_IN_CLASS (e-callee-decl) == BUILT_IN_NORMAL
- DECL_FUNCTION_CODE (e-callee-decl) == BUILT_IN_APPLY_ARGS)
- break;
- node-local.can_change_signature = !e;
+ /* Otherwise, inlinable functions always can change signature. */
+ if (info-inlinable)
+ node-local.can_change_signature = true;
+ else
+ {
+ /* Functions calling builtin_apply can not change signature. */
+ for (e = node-callees; e; e = e-next_callee)
+ {
+ tree cdecl = e-callee-decl;
+ if (DECL_BUILT_IN (cdecl)
+DECL_BUILT_IN_CLASS (cdecl) == BUILT_IN_NORMAL
+(DECL_FUNCTION_CODE (cdecl) == BUILT_IN_APPLY_ARGS
+ || DECL_FUNCTION_CODE (cdecl) == BUILT_IN_VA_START))
+ break;
+ }
+ node-local.can_change_signature = !e;
+ }
}
estimate_function_body_sizes (node, early);
Index: src/gcc/ipa-split.c
===
--- src.orig/gcc/ipa-split.c
+++ src/gcc/ipa-split.c
@@ -945,10 +945,10 @@ static void
split_function (struct split_point *split_point)
{
VEC (tree, heap) *args_to_pass = NULL;
- bitmap args_to_skip = BITMAP_ALLOC (NULL);
+ bitmap args_to_skip;
tree parm;
int num = 0;
- struct cgraph_node *node;
+ struct cgraph_node *node, *cur_node = cgraph_get_node
(current_function_decl);
basic_block return_bb = find_return_bb ();
basic_block call_bb;
gimple_stmt_iterator gsi;
@@ -968,17 +968,30 @@ split_function (struct split_point *spli
dump_split_point (dump_file, split_point);
}
+ if (cur_node-local.can_change_signature)
+args_to_skip = BITMAP_ALLOC (NULL);
+ else
+args_to_skip = NULL;
+
/* Collect the parameters of new
Re: Vector shuffling
On Tue, 30 Aug 2011, Richard Guenther wrote: oh, hum - now I remember ;) Eventually the C frontend should handle this not via the function call mechanism but similar to how Joseph added __builtin_complex support with 2011-08-19 Joseph Myers jos...@codesourcery.com * c-parser.c (c_parser_postfix_expression): Handle RID_BUILTIN_COMPLEX. * doc/extend.texi (__builtin_complex): Document. and then emit VEC_SHUFFLE_EXPRs directly from the frontend. Joseph? It's probably time to refactor the parsing code before adding yet another pseudo-builtin. Considering just those all of whose operands are expressions (there are more where types are involved), we have __builtin_complex (two operands) and __builtin_choose_expr (three operands). How about a helper that parses a parenthesized list of expressions (using c_parser_expr_list, disabling all folding and conversions), gives an error if the number of expressions is wrong, then returns an error status and the list? Pass the keyword to this function and it can give a wrong number of arguments error that says which pseudo-builtin is involved, rather than less friendly parse errors - so these things would act a bit more like built-in functions while still being purely front-end syntax for GENERIC and GIMPLE operations. Then c_parser_postfix_expression would only have the code that deals with semantics, without duplicating the generic code for parsing lists. -- Joseph S. Myers jos...@codesourcery.com
Re: options generation and language count
On Tue, 30 Aug 2011, Gary Funck wrote: On 08/30/11 15:52:12, Joseph S. Myers wrote: Please send a patch. [... on points 1, 2, and 3]0 OK, will do. GF: Also, the use of fixed masks is problematic. Perhaps the AWK script GF: could be changed to also generate values for CL_PARAMS, etc., ensuring GF: that will not conflict with the language mask values? That sounds riskier (and does everywhere using opts.h actually need the generated options.h as well?) It looks like many files include opts.h, but do not include options.h. options.h is also included via flags.h or tm.h. (The dependencies between these headers are rather a mess.) although in principle it ought to be possible to assign this automatically (and actually only CL_DRIVER, CL_TARGET and CL_COMMON should really need bits assigned, though avoiding the others would require a --help rework). An alternative might be to move the fixed assignments (CL_DRIVER, CL_TARGET, CL_COMMON ...) down to start at the beginning of the range, (leaving room for a few more) and to start the auto-generated language mask bits above that? You could do that - again, you'd need to watch for existing dependencies on the ordering. -- Joseph S. Myers jos...@codesourcery.com
Re: Vector shuffling
On Tue, Aug 30, 2011 at 2:03 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Tue, Aug 30, 2011 at 4:31 AM, Artem Shinkarov
artyom.shinkar...@gmail.com wrote:
Hi
This is a patch for the explicit vector shuffling we have discussed a
long time ago here:
http://gcc.gnu.org/ml/gcc-patches/2010-08/msg01092.html
The new patch introduces the new tree code, as we agreed, and expands
this code by checking the vshuffle pattern in the backend.
The patch at the moment lacks of some examples, but mainly it works
fine for me. It would be nice if i386 gurus could look into the way I
am doing the expansion.
Middle-end parts seems to be more or less fine, they have not changed
much from the previous time.
+@code{__builtin_shuffle (vec, mask)} and
+@code{__builtin_shuffle (vec0, vec1, mask)}. Both functions construct
the latter would be __builtin_shuffle2.
Why??
That was the syntax we agreed on that elegantly handles both cases in one place.
+bool
+expand_vec_shuffle_expr_p (enum machine_mode mode, tree v0,
+ tree v1, tree mask)
+{
+#define inner_type_size(vec) \
+ GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (TREE_TYPE (vec
missing comment. No #defines like this please, just initialize
two temporary variables.
+
+rtx
+expand_vec_shuffle_expr (tree type, tree v0, tree v1, tree mask, rtx target)
+{
comment.
+vshuffle:
+ gcc_assert (v1 == v0);
+
+ icode = direct_optab_handler (vshuffle_optab, mode);
hmm, so we don't have a vshuffle2 optab but always go via the
builtin function, but only for constant masks there? I wonder
if we should arrange for targets to only support a vshuffle
optab (thus, transition away from the builtin) and so
unconditionally have a vshuffle2 optab only (with possibly
equivalent v1 and v0?)
I have only implemented the case with non-constant mask that supports
only one argument. I think that it would be enough for the first
version. Later we can introduce vshuffle2 pattern and reuse the code
that expands vshuffle at the moment.
I suppose Richard might remember what he had in mind back
when we discussed this.
Index: gcc/c-typeck.c
===
--- gcc/c-typeck.c (revision 177758)
+++ gcc/c-typeck.c (working copy)
@@ -2815,6 +2815,68 @@ build_function_call_vec (location_t loc,
!check_builtin_function_arguments (fundecl, nargs, argarray))
return error_mark_node;
+ /* Typecheck a builtin function which is declared with variable
+ argument list. */
+ if (fundecl DECL_BUILT_IN (fundecl)
+ DECL_BUILT_IN_CLASS (fundecl) == BUILT_IN_NORMAL)
just add to check_builtin_function_arguments which is called right
in front of your added code.
+ /* Here we change the return type of the builtin function
+ from int f(...) -- t f(...) where t is a type of the
+ first argument. */
+ fundecl = copy_node (fundecl);
+ TREE_TYPE (fundecl) = build_function_type (TREE_TYPE (firstarg),
+ TYPE_ARG_TYPES (TREE_TYPE
(fundecl)));
+ function = build_fold_addr_expr (fundecl);
oh, hum - now I remember ;) Eventually the C frontend should handle
this not via the function call mechanism but similar to how Joseph
added __builtin_complex support with
2011-08-19 Joseph Myers jos...@codesourcery.com
* c-parser.c (c_parser_postfix_expression): Handle RID_BUILTIN_COMPLEX.
* doc/extend.texi (__builtin_complex): Document.
and then emit VEC_SHUFFLE_EXPRs directly from the frontend. Joseph?
FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (inside_init), ix,
value)
- if (!CONSTANT_CLASS_P (value))
+ if (!CONSTANT_CLASS_P (value))
watch out for spurious whitespace changes.
Index: gcc/gimplify.c
===
--- gcc/gimplify.c (revision 177758)
+++ gcc/gimplify.c (working copy)
@@ -7050,6 +7050,7 @@ gimplify_expr (tree *expr_p, gimple_seq
break;
case BIT_FIELD_REF:
+ case VEC_SHUFFLE_EXPR:
I don't think that's quite the right place given the is_gimple_lvalue
predicate on the first operand. More like
case VEC_SHUFFLE_EXPR:
goto expr_3;
+/* Vector shuffle expression. A = VEC_SHUFFLE_EXPRv0, v1, maks
typo, mask
+ means
+
+ freach i in length (mask):
+ A = mask[i] length (v0) ? v0[mask[i]] : v1[mask[i]]
+*/
+DEFTREECODE (VEC_SHUFFLE_EXPR, vec_shuffle_expr, tcc_expression, 3)
what is the (is there any?) constraint on the operand types, especially
the mask type?
Index: gcc/gimple.c
===
--- gcc/gimple.c (revision 177758)
+++ gcc/gimple.c (working copy)
@@ -2623,6 +2623,7 @@ get_gimple_rhs_num_ops (enum tree_code c
|| (SYM) == ADDR_EXPR
Re: [Ada] Clean up and document use of IN_GCC outside the compiler
On Tue, 30 Aug 2011, Eric Botcazou wrote: This cleans up and documents the use of IN_GCC in the GNAT build system. The mess of IN_GCC isn't at all GNAT-specific. See what I said in http://gcc.gnu.org/ml/gcc-patches/2010-10/msg00947.html. Beyond that, include/ansidecl.h tests IN_GCC to avoid defining some macros (which should be removed completely and unconditionally, but that may require fixing some users in the src repository). -- Joseph S. Myers jos...@codesourcery.com
[PATCH, i386]: Fix FMA fallout
Hello!
The gcc.target/i386/fma-compile.c test did not escape [ and ]
correctly. Unfortunately, this problem terminated dejagnu testing
early, hiding the problem with -mfma target attribute handling.
Attached patch fixes both problems.
2011-08-30 Uros Bizjak ubiz...@gmail.com
* config/i386/i386.c (ix86_valid_target_attribute_inner_p):
Handle FMA option.
testsuite/ChangeLog:
2011-08-30 Uros Bizjak ubiz...@gmail.com
* gcc.target/i386/fma-compile.c: Escape [ and ] correctly.
Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline.
Index: config/i386/i386.c
===
--- config/i386/i386.c (revision 178319)
+++ config/i386/i386.c (working copy)
@@ -4076,6 +4076,7 @@ ix86_valid_target_attribute_inner_p (tree args, ch
IX86_ATTR_ISA (sse4a,OPT_msse4a),
IX86_ATTR_ISA (ssse3,OPT_mssse3),
IX86_ATTR_ISA (fma4, OPT_mfma4),
+IX86_ATTR_ISA (fma, OPT_mfma),
IX86_ATTR_ISA (xop, OPT_mxop),
IX86_ATTR_ISA (lwp, OPT_mlwp),
IX86_ATTR_ISA (fsgsbase, OPT_mfsgsbase),
Index: testsuite/gcc.target/i386/fma-compile.c
===
--- testsuite/gcc.target/i386/fma-compile.c (revision 178319)
+++ testsuite/gcc.target/i386/fma-compile.c (working copy)
@@ -199,23 +199,23 @@ check_mm256_fmsubadd_ps (__m256 a, __m256 b, __m25
}
-/* { dg-final { scan-assembler-times vfmadd[^s]..ps 2 } } */
-/* { dg-final { scan-assembler-times vfmsub[^s]..ps 2 } } */
+/* { dg-final { scan-assembler-times vfmadd\[^s\]..ps 2 } } */
+/* { dg-final { scan-assembler-times vfmsub\[^s\]..ps 2 } } */
/* { dg-final { scan-assembler-times vfnmadd...ps 2 } } */
/* { dg-final { scan-assembler-times vfnmsub...ps 2 } } */
/* { dg-final { scan-assembler-times vfmaddsub...ps 2 } } */
/* { dg-final { scan-assembler-times vfmsubadd...ps 2 } } */
-/* { dg-final { scan-assembler-times vfmadd[^s]..pd 2 } } */
-/* { dg-final { scan-assembler-times vfmsub[^s]..pd 2 } } */
+/* { dg-final { scan-assembler-times vfmadd\[^s\]..pd 2 } } */
+/* { dg-final { scan-assembler-times vfmsub\[^s\]..pd 2 } } */
/* { dg-final { scan-assembler-times vfnmadd...pd 2 } } */
/* { dg-final { scan-assembler-times vfnmsub...pd 2 } } */
/* { dg-final { scan-assembler-times vfmaddsub...pd 2 } } */
/* { dg-final { scan-assembler-times vfmsubadd...pd 2 } } */
-/* { dg-final { scan-assembler-times vfmadd[^s]..ss 1 } } */
-/* { dg-final { scan-assembler-times vfmsub[^s]..ss 1 } } */
+/* { dg-final { scan-assembler-times vfmadd\[^s\]..ss 1 } } */
+/* { dg-final { scan-assembler-times vfmsub\[^s\]..ss 1 } } */
/* { dg-final { scan-assembler-times vfnmadd...ss 1 } } */
/* { dg-final { scan-assembler-times vfnmsub...ss 1 } } */
-/* { dg-final { scan-assembler-times vfmadd[^s]..sd 1 } } */
-/* { dg-final { scan-assembler-times vfmsub[^s]..sd 1 } } */
+/* { dg-final { scan-assembler-times vfmadd\[^s\]..sd 1 } } */
+/* { dg-final { scan-assembler-times vfmsub\[^s\]..sd 1 } } */
/* { dg-final { scan-assembler-times vfnmadd...sd 1 } } */
/* { dg-final { scan-assembler-times vfnmsub...sd 1 } } */
Re: [PATCH, i386]: Fix FMA fallout
On Tue, Aug 30, 2011 at 10:46 AM, Uros Bizjak ubiz...@gmail.com wrote:
Hello!
The gcc.target/i386/fma-compile.c test did not escape [ and ]
correctly. Unfortunately, this problem terminated dejagnu testing
early, hiding the problem with -mfma target attribute handling.
Attached patch fixes both problems.
2011-08-30 Uros Bizjak ubiz...@gmail.com
* config/i386/i386.c (ix86_valid_target_attribute_inner_p):
Handle FMA option.
testsuite/ChangeLog:
2011-08-30 Uros Bizjak ubiz...@gmail.com
* gcc.target/i386/fma-compile.c: Escape [ and ] correctly.
Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline.
It is
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50240
Thanks.
--
H.J.
Re: [Patch][Cilkplus Branch] Updates and Bug fixes
On Mon, Aug 29, 2011 at 7:41 PM, Andi Kleen a...@firstfloor.org wrote: H.J. Lu hjl.to...@gmail.com writes: On Mon, Aug 29, 2011 at 12:44 PM, Iyer, Balaji V balaji.v.i...@intel.com wrote: Hello Everyone, Here is a link for a new patch (http://software.intel.com/file/38290). This patch is for the cilkplus branch and includes the following modifications: 1) Merges changes in the gcc master (SHA1: f326eb816922bc183133c09b25564d550ab9a282). 2) Adds functionality to allow _Cilk_spawn inside constructors and destructors. 3) The original code was storing the cilk_for scope as a tree_chain. This patch modifies it so that it is stored in the same location as FOR_SCOPE(). 4) The presence of a label inside a cilk_for loop was causing an ICE. This patch fixes that. 5) Spawning a spawned function also was causing an ICE. This patch fixes that also. 6) Adds the __cilk macro and sets it to 200. 7) Adds test cases for all the fixes mentioned above. 8) Fixes a bug in the libcilkrts runtime during initialization when the number of workers is greater than 3x the number of cores on the system. I suggest you use separate steps to merge with trunk and fix the bugs. Their order isn't important. You should send the bug fixes directly to gcc-patches mailing list. Also it would be good if you cleaned up your original patch a bit. I noticed that it has a lot of white space changes to unrelated code, which makes it hard to figure out what it actually changes. Bajaji, Please cleanup the formatting issues on cilkplus branch and please follow GCC coding standard. -- H.J.
Re: [C++0x] contiguous bitfields race implementation
Btw, *byte_offset is still not relative to the containing object as
documented, but relative to the base object of the exp reference
tree (thus, to a in a.i.j.k.l instead of to a.i.j.k). If it were supposed
to be relative to a.i.j.k get_inner_reference would be not needed
either. Can you clarify what containing object means in the
overall comment please?
I'm thoroughly confused here. Originally I had inner decl, then we
changed the nomenclature to containing object, and now there's this
innermost reference.
What I mean to say is the a in a.i.j.k.l. How would you like me to
call that? The innermost reference? The inner decl? Would this
comment be acceptable:
Given a COMPONENT_REF, this function calculates the byte offset
from the innermost reference (a in a.i.j.k.l) to the start of the
contiguous bit region containing the field in question.
If it is really relative to the innermost reference of exp you can
CSE the offset of TREE_OPERAND (exp, 0) and do relative
adjustments for all the other get_inner_reference calls. For
example the
+ /* If we found the end of the bit field sequence, include the
+ padding up to the next field... */
if (fld)
{
...
+ /* Calculate bitpos and offset of the next field. */
+ get_inner_reference (build3 (COMPONENT_REF,
+ TREE_TYPE (exp),
+ TREE_OPERAND (exp, 0),
+ fld, NULL_TREE),
+ tbitsize,end_bitpos,end_offset,
+ tmode,tunsignedp,tvolatilep, true);
case is not correct anyway, fld may have variable position
(non-INTEGER_CST DECL_FIELD_OFFSET), you can't
assume
Innermost here means a in a.i.j.k.l? If so, this is what we're
currently doing, *byte_offset is the start of the bit region, and
*bit_offset is the offset from that.
First, I thought we couldn't get a variable position here because we are
now handling that case at the beginning of the function with:
/* Be as conservative as possible on variable offsets. */
if (TREE_OPERAND (exp, 2)
!host_integerp (TREE_OPERAND (exp, 2), 1))
{
*byte_offset = TREE_OPERAND (exp, 2);
*maxbits = BITS_PER_UNIT;
*bit_offset = 0;
return;
}
And even if we do get a variable position, I have so far being able to
get away with this...
+ *maxbits = TREE_INT_CST_LOW (maxbits_tree);
this thus.
...because the call to fold_build2 immediately preceding this will fold
away the variable offset.
Is what you want, that we call get_inner_reference once, and then use
DECL_FIELD_OFFSET+DECL_FIELD_BIT_OFFSET to calculate any subsequent bit
offset? I found this to be quite tricky with padding, and such, but am
willing to give it a whirl again.
However, could I beg you to reconsider this, and get something working
first, only later concentrating on removing the get_inner_reference()
calls, and performing any other tweaks/optimizations?
Aldy
Re: [PATCH][ARM] -m{cpu,tune,arch}=native
On Tue, Aug 30, 2011 at 10:47 PM, Stubbs, Andrew andrew_stu...@mentor.com wrote: On 29/08/11 04:29, Michael Hope wrote: On Sat, Aug 27, 2011 at 3:19 AM, Andrew Stubbsa...@codesourcery.com wrote: Hi all, This patch adds support for -mcpu=native, -mtune=native, and -march=native for ARM Linux hosts. So far, it only recognises Cortex-A8 and Cortex-A9, so I really need to find out what the magic part numbers are for other cpus before this patch is complete. I couldn't just find this information listed anywhere. I think there are a lot of clues in the kernel code, but it's hard to mine and it mostly only goes as far the architecture version, not the individual cpu. Could you send linaro-dev@ an email and ask them where this API is documented? API? It reads /proc/cpuinfo, and that just spits out the magic numbers from the processor registers. Linaro-dev might know more magic numbers though. Yip, most (all?) of the files under /proc are an API between user space and the kernel and have the usual requirements of usability and compatibility. -- Michael
Re: [Patch][Cilkplus Branch] Updates and Bug fixes
Please cleanup the formatting issues on cilkplus branch and please follow GCC coding standard. I'm not sure if following the coding standard is required for the library. After all it's essentially a third party library and I assume shared with other cilkplus implementations. It may make more sense to leave that in the original coding standard. There's already precedent for that: e.g. libdecnumber. -Andi
Re: [DOC] CP_TYPE_QUALS - cp_type_quals
Hi, apparently the doc wasn't updated 10 years ago when the macro CP_TYPE_QUALS was replaced with the function cp_type_quals. I assume the behavior didn't change, so the documentation change should be minor. Or are functions documented differently? 2011-08-08 Marc Glisse marc.gli...@inria.fr * doc/generic.texi: CP_TYPE_QUALS - cp_type_quals Jason, can you have a look to this doc patchlet? I can take care of committing it, in case. Thanks, Paolo.
C++ PATCH for c++/50084 (ICE with decltype and unnamed local class)
In this testcase the compiler was incorrectly treating the typedef as
giving a name to the class for linkage purposes, and then getting
confused by that. While looking at this I noticed that nothing was
actually looking at the user_defined_type_p bitfield, so I repurposed it.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit bd3f1ed177f5ce0961f6482a3ea8a3dd1f9df336
Author: Jason Merrill ja...@redhat.com
Date: Tue Aug 30 16:46:14 2011 -0400
PR c++/50084
* cp-tree.h (cp_decl_specifier_seq): Rename user_defined_type_p
to type_definition_p.
* parser.c (cp_parser_set_decl_spec_type): Likewise.
* decl.c (grokdeclarator): Check it.
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index d125642..d18599b 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -4551,8 +4551,8 @@ typedef struct cp_decl_specifier_seq {
/* The storage class specified -- or sc_none if no storage class was
explicitly specified. */
cp_storage_class storage_class;
- /* True iff TYPE_SPEC indicates a user-defined type. */
- BOOL_BITFIELD user_defined_type_p : 1;
+ /* True iff TYPE_SPEC defines a class or enum. */
+ BOOL_BITFIELD type_definition_p : 1;
/* True iff multiple types were (erroneously) specified for this
decl-specifier-seq. */
BOOL_BITFIELD multiple_types_p : 1;
diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index 9090b11..39a0b0e 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -9643,6 +9643,7 @@ grokdeclarator (const cp_declarator *declarator,
TYPE_NAME (type)
TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
TYPE_ANONYMOUS_P (type)
+ declspecs-type_definition_p
cp_type_quals (type) == TYPE_UNQUALIFIED)
{
tree t;
diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index c862a7d..7d766d1 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -12577,7 +12577,7 @@ cp_parser_type_specifier (cp_parser* parser,
cp_parser_set_decl_spec_type (decl_specs,
type_spec,
token-location,
- /*user_defined_p=*/true);
+ /*type_definition_p=*/true);
return type_spec;
}
else
@@ -12606,7 +12606,7 @@ cp_parser_type_specifier (cp_parser* parser,
cp_parser_set_decl_spec_type (decl_specs,
type_spec,
token-location,
- /*user_defined_p=*/true);
+ /*type_definition_p=*/true);
return type_spec;
}
@@ -12628,7 +12628,7 @@ cp_parser_type_specifier (cp_parser* parser,
cp_parser_set_decl_spec_type (decl_specs,
type_spec,
token-location,
- /*user_defined_p=*/true);
+ /*type_definition_p=*/false);
return type_spec;
case RID_CONST:
@@ -12821,7 +12821,7 @@ cp_parser_simple_type_specifier (cp_parser* parser,
if (decl_specs)
cp_parser_set_decl_spec_type (decl_specs, type,
token-location,
- /*user_defined_p=*/true);
+ /*type_definition_p=*/false);
return type;
@@ -12831,7 +12831,7 @@ cp_parser_simple_type_specifier (cp_parser* parser,
if (decl_specs)
cp_parser_set_decl_spec_type (decl_specs, type,
token-location,
- /*user_defined_p=*/true);
+ /*type_definition_p=*/false);
return type;
@@ -12848,7 +12848,7 @@ cp_parser_simple_type_specifier (cp_parser* parser,
if (decl_specs)
cp_parser_set_decl_spec_type (decl_specs, type,
token-location,
- /*user_defined_p=*/true);
+ /*type_definition_p=*/false);
cp_lexer_consume_token (parser-lexer);
return type;
}
@@ -12865,7 +12865,7 @@ cp_parser_simple_type_specifier (cp_parser* parser,
cp_parser_set_decl_spec_type (decl_specs,
type,
token-location,
- /*user_defined=*/false);
+ /*type_definition_p=*/false);
if (decl_specs)
decl_specs-any_specifiers_p = true;
@@ -12940,7 +12940,7 @@ cp_parser_simple_type_specifier (cp_parser* parser,
if (type decl_specs)
cp_parser_set_decl_spec_type (decl_specs, type,
token-location,
- /*user_defined=*/true);
+ /*type_definition_p=*/false);
}
/* If we didn't get a type-name, issue an error message. */
@@ -21004,15 +21004,14 @@ cp_parser_set_storage_class (cp_parser *parser,
decl_specs-conflicting_specifiers_p = true;
}
-/* Update the DECL_SPECS to reflect the TYPE_SPEC. If USER_DEFINED_P
- is true, the type is a user-defined type; otherwise it is a
- built-in type specified by a keyword. */
+/* Update the DECL_SPECS to reflect the TYPE_SPEC. If TYPE_DEFINITION_P
+ is true, the type is a class or enum definition. */
static void
cp_parser_set_decl_spec_type (cp_decl_specifier_seq *decl_specs,
tree type_spec,
location_t location,
- bool user_defined_p)
+ bool type_definition_p)
{
decl_specs-any_specifiers_p = true;
@@ -21022,7 +21021,7 @@ cp_parser_set_decl_spec_type (cp_decl_specifier_seq *decl_specs,
declarations so that G++ can work with system headers
C++ PATCH for c++/50089 (ICE with qualified-id call in lambda)
Just needed to correct current_class_type to current_nonlambda_class
type here.
Tested x86_64-pc-linux-gnu, applying to trunk and 4.6.
commit 159563fe81e80fd23ff6252e17c86012a20b169b
Author: Jason Merrill ja...@redhat.com
Date: Tue Aug 30 15:46:31 2011 -0400
PR c++/50089
* semantics.c (finish_id_expression): Use
current_nonlambda_class_type for qualified-ids.
diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c
index dd7c013..ce84062 100644
--- a/gcc/cp/semantics.c
+++ b/gcc/cp/semantics.c
@@ -3251,7 +3251,7 @@ finish_id_expression (tree id_expression,
if (scope)
{
decl = (adjust_result_of_qualified_name_lookup
- (decl, scope, current_class_type));
+ (decl, scope, current_nonlambda_class_type()));
if (TREE_CODE (decl) == FUNCTION_DECL)
mark_used (decl);
diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-qualified.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-qualified.C
new file mode 100644
index 000..ef041c2
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-qualified.C
@@ -0,0 +1,17 @@
+// PR c++/50089
+// { dg-options -std=c++0x }
+
+struct TestBase
+{
+ void foo() {}
+};
+
+struct Test : TestBase
+{
+ void foo()
+ {
+[this]{
+ /*this-*/TestBase::foo(); // ICE without this-
+}();
+ }
+};
C++ PATCH for c++/50114 (ICE with for-loop and lambda)
We play funny games with binding levels to support backward
compatibility with the ARM-era rules for for-loop scoping, and we play
funny games with binding levels to support lambdas, and the games didn't
play well with each other. It seems unlikely that people will still be
relying on ancient for scope rules in C++11 code, so we can just disable
those games in C++11 mode.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit 03b745415d2109312c4449479c2f94e65bd770b4
Author: Jason Merrill ja...@redhat.com
Date: Tue Aug 30 14:32:54 2011 -0400
PR c++/50114
* decl.c (poplevel): Disable for scope compatibility hack
in C++11 mode.
diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index c375cf7..9090b11 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -643,6 +643,9 @@ poplevel (int keep, int reverse, int functionbody)
for (link = decls; link; link = TREE_CHAIN (link))
{
if (leaving_for_scope TREE_CODE (link) == VAR_DECL
+ /* It's hard to make this ARM compatibility hack play nicely with
+ lambdas, and it really isn't necessary in C++11 mode. */
+ cxx_dialect cxx0x
DECL_NAME (link))
{
tree name = DECL_NAME (link);
diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-for.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-for.C
new file mode 100644
index 000..f161da8
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-for.C
@@ -0,0 +1,12 @@
+// PR c++/50114
+// { dg-options -std=c++0x -w }
+
+int open()
+{
+ int *x2feed_i = 0;
+ auto insert_feed = [](unsigned char venue, int* newfeed)
+ {
+ for(int x2feed_i = 1; 0; ) ;
+ x2feed_i = newfeed;
+ };
+}
diff --git a/gcc/testsuite/g++.dg/ext/forscope2.C b/gcc/testsuite/g++.dg/ext/forscope2.C
index b883eff..4c63bab 100644
--- a/gcc/testsuite/g++.dg/ext/forscope2.C
+++ b/gcc/testsuite/g++.dg/ext/forscope2.C
@@ -1,5 +1,5 @@
// { dg-do compile }
-// { dg-options -fpermissive }
+// { dg-options -fpermissive -std=c++98 }
// Copyright (C) 2001 Free Software Foundation, Inc.
// Contributed by Nathan Sidwell 4 Sept 2001 nat...@codesourcery.com
Re: [Patch, Fortran] PR 45044 - Named common: Different size diagnostics
On Tue, Aug 30, 2011 at 11:31:38PM +0200, Tobias Burnus wrote: Named common blocks are required to have the same size in all files and scopes. gfortran was warning before when the size was extended, but not when a smaller common block followed a larger common block with the same name. This patch adds now a non-equal check and also mentions the byte size. I was thinking of adding another ref to point to the first common block, but my approach did not work (cf. PR comment 4) - besides, I find error messages with two loci harder to read. Build and regtested on x86-64-linux. OK for the trunk? Looks ok to me. -- Steve
Re: Vector shuffling
On Aug 30, 2011, at 10:01 AM, Artem Shinkarov wrote:
The patch at the moment lacks of some examples, but mainly it works
fine for me. It would be nice if i386 gurus could look into the way I
am doing the expansion.
Middle-end parts seems to be more or less fine, they have not changed
much from the previous time.
+@code{__builtin_shuffle (vec, mask)} and
+@code{__builtin_shuffle (vec0, vec1, mask)}. Both functions construct
the latter would be __builtin_shuffle2.
Why??
That was the syntax we agreed on that elegantly handles both cases in one
place.
If you're going to add vector shuffling builtins, you might consider adding the
same builtin that clang has for compatibility:
http://clang.llvm.org/docs/LanguageExtensions.html#__builtin_shufflevector
It should be straight-forward to map it into the same IR.
-Chris
Re: tree hash maps and 'discards qualifiers' warnings?
On 08/17/11 08:38:44, Gary Funck wrote: I have been looking at changing UPC's method of recording the blocking factor so that it uses less space in the tree type node. The suggested method for achieving this space reduction is to use a hash table to map pointers to type nodes into UPC blocking factors (for less commonly used blocking factor values). [...] The issue that I'm running into, however, is that the re-implementation of UPC_TYPE_BLOCK_FACTOR() is not plug-and-play with its previous version that used a tree pointer in the node to record the blocking factor. [...] As a follow up, I wasn't able to find an alternative method that preserved the const'ness of the API's involved in the change, so ended up reverting them back to regular tree pointers. The following change was committed to the GUPC branch. 2011-08-30 Gary Funck g...@intrepid.com * tree.h (check_qualified_type): Change 'const_tree' argument types back to 'tree' to avoid complaints of assignment drops qualifiers for invocations of the newly implemented TYPE_BLOCK_FACTOR() macro, which invokes hash functions with 'tree' pointer values that are not const qualified. * tree.c (check_qualified_type, check_aligned_type): Ditto. * c-typeck.c (comptypes_internal): Ditto.
Re: C++ PATCH for c++/50207 (ICE on bogus decimal::decimal32)
Sure, the patch is safe enough. Done. Peter Bergner berg...@vnet.ibm.com wrote: On Tue, 2011-08-30 at 00:27 -0400, Jason Merrill wrote: The DFP classes are treated as transparent aggregates, so they get mangled and passed like their first field. In the testcase it is defined to have a base class, so the first field is an artificial base field, which doesn't make any sense. Tested x86_64-pc-linux-gnu, applying to trunk. Thanks for fixing this Jason! The same error also occurs on 4.6. Do you plan on fixing it there too? Peter
