Re: update acc routines in fortran

On Thu, Nov 19, 2015 at 08:26:45AM -0800, Cesar Philippidis wrote: > (gfc_oacc_routine_name): New struct; Full stop instead of semicolon. > diff --git a/gcc/tree-nested.c b/gcc/tree-nested.c > index 1f6311c..e321072 100644 > --- a/gcc/tree-nested.c > +++ b/gcc/tree-nested.c > @@ -1106,6

Re: [PATCH] Add clang-format config to contrib folder

On 11/20/2015 11:33 AM, Martin Liška wrote: > Hi Pedro. Hi Martin. > Fully agree with you, there's suggested patch. > Hope I can install the patch for trunk? I'd call it obvious. :-) Thanks, Pedro Alves

Re: [PATCH, VECTOR ABI] Add __attribute__((__simd__)) to GCC.

Hi Kirill, On 18/11/15 14:11, Kirill Yukhin wrote: Hello Andreas, Devid. On 18 Nov 10:45, Andreas Schwab wrote: Kirill Yukhin writes: diff --git a/gcc/testsuite/c-c++-common/attr-simd.c b/gcc/testsuite/c-c++-common/attr-simd.c new file mode 100644 index

Go patch committed: add receiver type to specific type function name

This patch to the Go frontend fixes the case where two different methods on different types with the same method name both define a type internally with the same name where the type requires a specific type hash or equality function. Before this patch those functions would get the same, causing a

Re: [PATCH, 10/16] Add pass_oacc_kernels pass group in passes.def

On 20/11/15 11:37, Richard Biener wrote: I'd rather make loop_optimizer_init do nothing if requested flags are already set and no fixup is needed Thus sth like Index: gcc/loop-init.c === --- gcc/loop-init.c (revision

Re: [PATCH, VECTOR ABI] Add __attribute__((__simd__)) to GCC.

Hello Kyrill, On 20 Nov 12:15, Kyrill Tkachov wrote: > >gcc/tessuite/ > > * c-c++-common/attr-simd-3.c: Put xfail (PR68158) on dg-error. > > This test fails on bare-metal targets that don't support -fcilkplus or > -pthread. > Would you consider moving them to the cilkplus testing directory

Re: Remove noce_mem_write_may_trap_or_fault_p in ifcvt

On 11/19/2015 12:49 AM, Jeff Law wrote: On 11/18/2015 12:16 PM, Bernd Schmidt wrote: I don't think so, actually. One safe option would be to rip it out and just stop transforming this case, but let's start by looking at the code just a bit further down, calling noce_can_store_speculate. This

Re: [PATCH][ARM] Do not expand movmisalign pattern if not in 32-bit mode

On 11/11/15 16:10, Kyrill Tkachov wrote: > Hi all, > > The attached testcase ICEs when compiled with -march=armv6k -mthumb -Os or > any march > for which -mthumb gives Thumb1: > error: unrecognizable insn: > } > ^ > (insn 13 12 14 5 (set (reg:SI 116 [ x ]) > (unspec:SI [ >

[Patch] sync top level configure with binutils-gdb

This patch was pushed on binutils-gdb repo, so I also commit it on gcc. Tristan. 2015-11-20 Tristan Gingold Sync with binutils-gdb: 2015-11-20 Tristan Gingold * configure.ac: Add aarch64-*-darwin* and arm-*-darwin*.

Re: [PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

On Fri, Nov 20, 2015 at 1:33 PM, Alan Hayward wrote: > > > On 20/11/2015 11:00, "Richard Biener" wrote: > >>On Fri, Nov 20, 2015 at 10:24 AM, Alan Hayward >>wrote: >>> When vectorising a integer induction condition

Re: [PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

On 20/11/2015 13:47, "Richard Biener" wrote: >On Fri, Nov 20, 2015 at 1:33 PM, Alan Hayward >wrote: >> >> >>On 20/11/2015 11:00, "Richard Biener" wrote: >> >>>On Fri, Nov 20, 2015 at 10:24 AM, Alan Hayward

[Patch, fortran] PRs 68237 & 66762 - submodule problems

Dear All, I have committed as 'obvious' revision 230661 to fix 2/3 submodule problems. In the case of the third, PR68243, I believe gfortran is behaving correctly and I am awaiting confirmation from the reporter. Thanks to Dominique for regtesting the part of the patch that fixes PR66762. I

Re: [PATCH, 10/16] Add pass_oacc_kernels pass group in passes.def

On Fri, 20 Nov 2015, Tom de Vries wrote: > On 20/11/15 11:37, Richard Biener wrote: > >I'd rather make loop_optimizer_init do nothing > > if requested flags are already set and no fixup is needed > > > Thus sth like > > > > Index: gcc/loop-init.c > >

Re: [PATCH, PR68337] Don't fold memcpy/memmove we want to instrument

On Fri, Nov 20, 2015 at 2:08 PM, Ilya Enkovich wrote: > On 19 Nov 18:19, Richard Biener wrote: >> On November 19, 2015 6:12:30 PM GMT+01:00, Bernd Schmidt >> wrote: >> >On 11/19/2015 05:31 PM, Ilya Enkovich wrote: >> >> Currently we fold all

Re: [PATCH][ARM] PR 68149 Fix ICE in unaligned_loaddi split

On 10/11/15 17:32, Kyrill Tkachov wrote: > Hi all, > > This ICE in this PR occurs when we're trying to split unaligned_loaddi into > two SImode unaligned loads. > The problem is in the addressing mode. When reload was picking the > addressing mode we accepted an offset of > -256 because the

Re: [PATCH, PR68337] Don't fold memcpy/memmove we want to instrument

On 20 Nov 14:54, Richard Biener wrote: > On Fri, Nov 20, 2015 at 2:08 PM, Ilya Enkovich wrote: > > On 19 Nov 18:19, Richard Biener wrote: > >> On November 19, 2015 6:12:30 PM GMT+01:00, Bernd Schmidt > >> wrote: > >> >On 11/19/2015 05:31 PM, Ilya

[ptx] overrride anchor hook

Jim discovered that he needed to override the anchoring hook when using a PPC host-side compiler, but didn't figure out why this was needed. Digging into it, I discovered that flag_section_anchors is cleared in toplev.c by the command line option machinery, if there are no anchor target hooks.

Re: [PATCH 3a/4][AArch64] Add attribute for compatibility with ARM pipeline models

On 20/11/15 12:27, James Greenhalgh wrote: On Thu, Nov 12, 2015 at 11:32:36AM -0600, Evandro Menezes wrote: On 11/12/2015 09:39 AM, Evandro Menezes wrote: 2015-11-12 Evandro Menezes [AArch64] Add attribute for compatibility with ARM pipeline models gcc/

Re: [Committed] S/390: Add bswaphi2 pattern

On 11/20/2015 01:23 PM, Richard Henderson wrote: > On 11/20/2015 12:52 PM, Andreas Krebbel wrote: >> +(define_insn "bswaphi2" >> + [(set (match_operand:HI 0 "register_operand" "=d") >> +(bswap:HI (match_operand:HI 1 "memory_operand" "RT")))] >> + "TARGET_CPU_ZARCH" >> +

Re: [PATCH, PR tree-optimization/68327] Compute vectype for live phi nodes when copmputing VF

On 20 Nov 14:31, Ilya Enkovich wrote: > 2015-11-20 14:28 GMT+03:00 Richard Biener : > > On Wed, Nov 18, 2015 at 2:53 PM, Ilya Enkovich > > wrote: > >> 2015-11-18 16:44 GMT+03:00 Richard Biener : > >>> On Wed, Nov 18,

Re: [PATCH] fix vectorizer performance problem on cygwin hosted cross compiler

On Fri, Nov 20, 2015 at 8:21 AM, Jim Wilson wrote: > A cygwin hosted cross compiler to aarch64-linux, compiling a C version > of linpack with -Ofast, produces code that runs 17% slower than a > linux hosted compiler. The problem shows up in the vect dump, where > some

Re: Add uaddv4_optab, usubv4_optab

> Eric has just submitted a documentation path that documented the > {add,sub,mul,umul}v4 and negv3 patterns, so this should be > applied on top of that. OK, I'm going to apply it, thanks. Note that the comment at the beginning of expand_addsub_overflow describing the overall strategy ought to

[committed, trivial] Fix typo and trailing whitespace in dump-file strings in parloops

[ was: Re: [PATCH, 10/16] Add pass_oacc_kernels pass group in passes.def ] On 18/11/15 17:22, Bernhard Reutner-Fischer wrote: Bonus points for fixing the dump_file to parse in: >Parloops will fail because: >... >phi is n_2 = PHI >arg of phi to exit: value n_4(D) used outside loop

Add uaddv4_optab, usubv4_optab

Toward fixing PR68385. I'm just starting a full round of testing, but extern void underflow(void) __attribute__((noreturn)); unsigned sub1(unsigned a, unsigned b) { unsigned r = a - b; if (r > a) underflow(); return r; } unsigned sub2(unsigned a, unsigned b) { unsigned r;

Re: [PATCH, 10/16] Add pass_oacc_kernels pass group in passes.def

On Thu, 19 Nov 2015, Tom de Vries wrote: > On 17/11/15 15:53, Tom de Vries wrote: > > > And the above LIM example > > > is none for why you need two LIM passes... > > > > Indeed. I'm planning a separate reply to explain in more detail the need > > for the two pass_lims. > > I. > > I managed to

Re: Add uaddv4_optab, usubv4_optab

On Fri, Nov 20, 2015 at 11:27:48AM +0100, Richard Henderson wrote: > Toward fixing PR68385. I'm just starting a full round of testing, but > > extern void underflow(void) __attribute__((noreturn)); > unsigned sub1(unsigned a, unsigned b) > { > unsigned r = a - b; > if (r > a)

Re: [PATCH, PR tree-optimization/68327] Compute vectype for live phi nodes when copmputing VF

2015-11-20 14:28 GMT+03:00 Richard Biener : > On Wed, Nov 18, 2015 at 2:53 PM, Ilya Enkovich wrote: >> 2015-11-18 16:44 GMT+03:00 Richard Biener : >>> On Wed, Nov 18, 2015 at 12:34 PM, Ilya Enkovich

Re: [PATCH 02/15] Add selftests to bitmap.c

On Thu, Nov 19, 2015 at 6:04 PM, David Malcolm wrote: > Jeff pre-approved the plugin version of this (as a new > file unittests/test-bitmap.c): > https://gcc.gnu.org/ml/gcc-patches/2015-10/msg03284.html > with: >> OK if/when prereqs are approved. Minor twiddling if we end

Re: [PATCH 2/4][AArch64] Increase the loop peeling limit

On Thu, Nov 19, 2015 at 04:04:41PM -0600, Evandro Menezes wrote: > On 11/05/2015 02:51 PM, Evandro Menezes wrote: > >2015-11-05 Evandro Menezes > > > > gcc/ > > > > * config/aarch64/aarch64.c (aarch64_override_options_internal): > > Increase loop peeling

Re: [PATCH, PR68373 ] Call scev_const_prop in pass_parallelize_loops::execute

On Thu, 19 Nov 2015, Tom de Vries wrote: > On 17/11/15 23:20, Tom de Vries wrote: > > [ was: Re: [PATCH, 10/16] Add pass_oacc_kernels pass group in passes.def ] > > > > Hi, > > > > Consider test-case test.c, with a use of the final value of the > > iteration variable (return i): > > ... > >

Re: [patch] Document new overflow arithmetics patterns

On Fri, Nov 20, 2015 at 11:12:06AM +0100, Eric Botcazou wrote: > Hi, > > this documents the new overflow arithmetics patterns added recently (addv4, > subv4, mulv4, umulv4, negv3) and only them, i.e. the old ones are still not. > This also fixes the description of the cbranch and jump patterns,

Re: Add uaddv4_optab, usubv4_optab

> Toward fixing PR68385. I'm just starting a full round of testing, but Do you mind if I install my doc patch? It's slightly more thorough. -- Eric Botcazou

Re: [PATCH 2/5] [AARCH64] Change IMP and PART over to integers from strings.

Hi Andrew, On 17/11/15 22:10, Andrew Pinski wrote: Because the imp and parts are really integer rather than strings, this patch moves the comparisons to be integer. Also allows saving around integers are easier than doing string comparisons. This allows for the next change. The way I store

Re: [PATCH, PR tree-optimization/68327] Compute vectype for live phi nodes when copmputing VF

On Wed, Nov 18, 2015 at 2:53 PM, Ilya Enkovich wrote: > 2015-11-18 16:44 GMT+03:00 Richard Biener : >> On Wed, Nov 18, 2015 at 12:34 PM, Ilya Enkovich >> wrote: >>> Hi, >>> >>> When we compute vectypes we skip

[patch] Document new overflow arithmetics patterns

Hi, this documents the new overflow arithmetics patterns added recently (addv4, subv4, mulv4, umulv4, negv3) and only them, i.e. the old ones are still not. This also fixes the description of the cbranch and jump patterns, which were referring to a label_ref instead of a code_label. Tested

Re: OpenACC declare directive updates

On Thu, Nov 19, 2015 at 10:22:16AM -0600, James Norris wrote: > 2015-XX-XX James Norris > Cesar Philippidis > > gcc/fortran/ > * dump-parse-tree.c (show_namespace): Handle declares. > * gfortran.h (struct

Re: [PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

On Fri, Nov 20, 2015 at 10:24 AM, Alan Hayward wrote: > When vectorising a integer induction condition reduction, > is_nonwrapping_integer_induction ends up with different values for base > during the analysis and build phases. In the first it is an INTEGER_CST, > in the

Re: [PATCH, PR68337] Don't fold memcpy/memmove we want to instrument

On 19 Nov 18:19, Richard Biener wrote: > On November 19, 2015 6:12:30 PM GMT+01:00, Bernd Schmidt > wrote: > >On 11/19/2015 05:31 PM, Ilya Enkovich wrote: > >> Currently we fold all memcpy/memmove calls with a known data size. > >> It causes two problems when used with

Re: [PATCH, 10/16] Add pass_oacc_kernels pass group in passes.def

On Thu, 19 Nov 2015, Tom de Vries wrote: > On 16/11/15 13:45, Richard Biener wrote: > > > I've eliminated all the uses for pass_tree_loop_init/pass_tree_loop_done > > > in > > > >the pass group. Instead, I've added conditional loop optimizer setup in: > > > >- pass_lim and pass_scev_cprop (added

Re: Add uaddv4_optab, usubv4_optab

On 11/20/2015 11:56 AM, Eric Botcazou wrote: Eric has just submitted a documentation path that documented the {add,sub,mul,umul}v4 and negv3 patterns, so this should be applied on top of that. OK, I'm going to apply it, thanks. Thanks. Note that the comment at the beginning of

Re: Add uaddv4_optab, usubv4_optab

On 11/20/2015 11:43 AM, Jakub Jelinek wrote: +(define_expand "uaddv4" + [(parallel [(set (reg:CCC FLAGS_REG) + (compare:CCC +(plus:SWI (match_dup 1) (match_dup 2)) +(match_dup 1))) + (set (match_dup 0) +

Re: [PATCH][GCC][ARM] Disable neon testing for armv7-m

Hi Andre, On 18/11/15 09:44, Andre Vieira wrote: On 17/11/15 10:10, James Greenhalgh wrote: On Mon, Nov 16, 2015 at 01:15:32PM +, Andre Vieira wrote: On 16/11/15 12:07, James Greenhalgh wrote: On Mon, Nov 16, 2015 at 10:49:11AM +, Andre Vieira wrote: Hi, This patch changes the

[RFC] [Patch] PR67326 - relax trap assumption by looking at similar DRS

Hi Richard, As per Jakub suggestion in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67326, the below patch fixes the regression in tree if conversion. Basically allowing if conversion to happen for a candidate DR, if we find similar DR with same dimensions and that DR will not trap. To find

Re: [PATCH 3a/4][AArch64] Add attribute for compatibility with ARM pipeline models

On Thu, Nov 12, 2015 at 11:32:36AM -0600, Evandro Menezes wrote: > On 11/12/2015 09:39 AM, Evandro Menezes wrote: >2015-11-12 Evandro Menezes > >[AArch64] Add attribute for compatibility with ARM pipeline models > >gcc/ > >* config/aarch64/aarch64.md

Re: [PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

On 20/11/2015 11:00, "Richard Biener" wrote: >On Fri, Nov 20, 2015 at 10:24 AM, Alan Hayward >wrote: >> When vectorising a integer induction condition reduction, >> is_nonwrapping_integer_induction ends up with different values for base >>

Re: GCC 5.3 Status Report (2015-11-20)

On Fri, Nov 20, 2015 at 7:53 AM, Richard Biener wrote: > > Status > == > > We plan to do a GCC 5.3 release candidate at the end of next week > followed by the actual release a week after that. > > So now is the time to look at your regression bugs in bugzilla and > do some

[PATCH][ARM] Enable fusion of AES instructions

Enable instruction fusion of AES instructions on ARM for Cortex-A53 and Cortex-A57. OK for commit? ChangeLog: 2015-11-20 Wilco Dijkstra * gcc/config/arm/arm.c (arm_cortex_a53_tune): Add AES fusion. (arm_cortex_a57_tune): Likewise.

Re: [PATCH] Fix memory leaks in tree-ssa-uninit.c

On 11/20/2015 03:14 AM, Bernd Schmidt wrote: > BTW, I'm with whoever said absolutely no way to the idea of making automatic > changes like this as part of a commit hook. > > I think the whitespace change can go in if it hasn't already, but I think the > other one still has enough problems that

Re: [PATCH] Add clang-format config to contrib folder

On 11/19/2015 06:43 PM, Pedro Alves wrote: > On 11/19/2015 12:54 PM, Martin Liška wrote: >> ContinuationIndentWidth: 2 >> -ForEachMacros: >>

[Committed] S/390: Add bswaphi2 pattern

Hi, the 16 bit bswap instruction support was missing in the back-end so far. Added with the attached patch. Bootstrapped on s390 and s390x. No regressions. Bye, -Andreas- gcc/testsuite/ChangeLog: 2015-11-20 Andreas Krebbel * gcc.target/s390/bswap-1.c:

Re: [RFC] [Patch] PR67326 - relax trap assumption by looking at similar DRS

On Fri, Nov 20, 2015 at 12:02:07PM +, Kumar, Venkataramanan wrote: > Also. > (1) I guard these checks for -ftree-loop-if-convert-stores and -fno-common. > Sometimes vectorization flags also triggers if conversion. > (2) Also hashing base DRs for writes only. Let me comment just on

Re: [Committed] S/390: Add bswaphi2 pattern

On 11/20/2015 12:52 PM, Andreas Krebbel wrote: +(define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (bswap:HI (match_operand:HI 1 "memory_operand" "RT")))] + "TARGET_CPU_ZARCH" + "lrvh\t%0,%1" + [(set_attr "type" "load") + (set_attr "op_type"

GCC 5.3 Status Report (2015-11-20)

Status == We plan to do a GCC 5.3 release candidate at the end of next week followed by the actual release a week after that. So now is the time to look at your regression bugs in bugzilla and do some backporting for things already fixed on trunk. Quality Data Priority

Re: [PATCH 3a/4][AArch64] Add attribute for compatibility with ARM pipeline models

On 11/20/2015 08:34 AM, Kyrill Tkachov wrote: On 20/11/15 12:27, James Greenhalgh wrote: On Thu, Nov 12, 2015 at 11:32:36AM -0600, Evandro Menezes wrote: On 11/12/2015 09:39 AM, Evandro Menezes wrote: 2015-11-12 Evandro Menezes [AArch64] Add attribute for

[PATCH, PR68460] Always call free_stmt_vec_info_vec in gather_scalar_reductions

[ was: Re: [PATCH] Fix parloops gimple_uid usage ] On 09/10/15 23:09, Tom de Vries wrote: @@ -2392,6 +2397,9 @@ gather_scalar_reductions (loop_p loop, reduction_info_table_type *reduction_list loop_vec_info simple_inner_loop_info = NULL; bool allow_double_reduc = true; + if

Re: [PATCH, 10/16] Add pass_oacc_kernels pass group in passes.def

On 20/11/15 14:29, Richard Biener wrote: I agree it's somewhat of an odd behavior but all passes should either be placed in a sub-pipeline with an outer loop_optimizer_init()/finalize () call or call both themselves. Hmm, but adding loop_optimizer_finalize at the end of pass_lim breaks the

Re: [PATCH][GCC][ARM] Disable neon testing for armv7-m

Hi Kyrill On 20/11/15 11:51, Kyrill Tkachov wrote: Hi Andre, On 18/11/15 09:44, Andre Vieira wrote: On 17/11/15 10:10, James Greenhalgh wrote: On Mon, Nov 16, 2015 at 01:15:32PM +, Andre Vieira wrote: On 16/11/15 12:07, James Greenhalgh wrote: On Mon, Nov 16, 2015 at 10:49:11AM +,

Re: [PATCH 3a/4][AArch64] Add attribute for compatibility with ARM pipeline models

On 11/20/2015 06:27 AM, James Greenhalgh wrote: On Thu, Nov 12, 2015 at 11:32:36AM -0600, Evandro Menezes wrote: On 11/12/2015 09:39 AM, Evandro Menezes wrote: 2015-11-12 Evandro Menezes [AArch64] Add attribute for compatibility with ARM pipeline models

Re: [PATCH 3a/4][AArch64] Add attribute for compatibility with ARM pipeline models

On Fri, Nov 20, 2015 at 09:55:29AM -0600, Evandro Menezes wrote: > On 11/20/2015 06:27 AM, James Greenhalgh wrote: > >On Thu, Nov 12, 2015 at 11:32:36AM -0600, Evandro Menezes wrote: > >>On 11/12/2015 09:39 AM, Evandro Menezes wrote: > >>2015-11-12 Evandro Menezes > >>

Re: PATCH to shorten_compare -Wtype-limits handling

Hmm, it looks like using expansion_point_if_in_system_header might avoid the first issue you mention. Thus. Great, thanks! (I'll have to remember the trick for my own use!) Martin

Re: [Patch, vrp] Allow VRP type conversion folding only for widenings upto word mode

On Thu, Nov 19, 2015 at 10:31:41AM -0700, Jeff Law wrote: > On 11/18/2015 11:20 PM, Senthil Kumar Selvaraj wrote: > >On Wed, Nov 18, 2015 at 09:36:21AM +0100, Richard Biener wrote: > >> > >>Otherwise ok. > > > >See modified patch below. If you think vrp98.c is unnecessary, feel free > >to dump it

Re: PATCH to shorten_compare -Wtype-limits handling

On 11/19/2015 05:16 PM, Jason Merrill wrote: On 11/19/2015 02:44 PM, Martin Sebor wrote: On 11/18/2015 09:26 PM, Jason Merrill wrote: The rs6000 target was hitting a bootstrap failure due to -Werror=type-limits. Since warn_tautological_cmp and other warnings avoid warning if one of the

Re: [PATCH] Fix PR68067

On 6 November 2015 at 10:39, Richard Biener wrote: >> ../spec2000/benchspec/CINT2000/254.gap/src/polynom.c:358:11: error: location >> references block not in block tree >> l1_279 = PHI <1(28), l1_299(33)> > > ^^^ > > this is the error to look at! It means that the GC heap will

Re: [Patch, vrp] Allow VRP type conversion folding only for widenings upto word mode

On 11/20/2015 10:04 AM, Senthil Kumar Selvaraj wrote: On Thu, Nov 19, 2015 at 10:31:41AM -0700, Jeff Law wrote: On 11/18/2015 11:20 PM, Senthil Kumar Selvaraj wrote: On Wed, Nov 18, 2015 at 09:36:21AM +0100, Richard Biener wrote: Otherwise ok. See modified patch below. If you think vrp98.c

Re: PATCH to shorten_compare -Wtype-limits handling

On 11/19/2015 12:02 PM, Manuel López-Ibáñez wrote: On 19 November 2015 at 17:54, Jeff Law wrote: But there were a couple of patches from you some time ago, for example: http://permalink.gmane.org/gmane.comp.gcc.patches/343476 What happened with those? On hold pending fixing

Re: PATCH to shorten_compare -Wtype-limits handling

On 20 November 2015 at 17:42, Jeff Law wrote: > So we have to detangle the operand shortening from warning detection. Kai's > idea was to first make the shortening code "pure" in the sense that it would > have no side effects other than to generate the warnings. Canonicalization

Merge from trunk to gccgo branch

I merged trunk revision 230657 to the gccgo branch. Ian

Re: [PATCH 3b/4][AArch64] Add scheduling model for Exynos M1

On Tue, Nov 10, 2015 at 11:54:00AM -0600, Evandro Menezes wrote: >2015-11-10 Evandro Menezes > >gcc/ > >* config/aarch64/aarch64-cores.def: Use the Exynos M1 sched model. >* config/aarch64/aarch64.md: Include "exynos-m1.md". >*

Re: [patch] Python Pretty Printers get disabled on libstdc++ reload by GDB (PR libstdc++/68448)

On 20/11/15 18:28 +0100, Jan Kratochvil wrote: On Thu, 19 Nov 2015 21:21:51 +0100, Jan Kratochvil wrote: * python/hook.in: Call register_libstdcxx_printers. * python/libstdcxx/v6/__init__.py: Wrap it to register_libstdcxx_printers. [...] -import libstdcxx.v6 +# Call a

Re: PATCH to shorten_compare -Wtype-limits handling

On 20 November 2015 at 16:10, Martin Sebor wrote: >>> Hmm, it looks like using expansion_point_if_in_system_header might avoid >>> the first issue you mention. >> >> >> Thus. > > > Great, thanks! (I'll have to remember the trick for my own use!) I added this to

Re: [patch] Python Pretty Printers get disabled on libstdc++ reload by GDB (PR libstdc++/68448)

On Thu, 19 Nov 2015 21:21:51 +0100, Jan Kratochvil wrote: > * python/hook.in: Call register_libstdcxx_printers. > * python/libstdcxx/v6/__init__.py: Wrap it to > register_libstdcxx_printers. [...] > -import libstdcxx.v6 > +# Call a function as a plain import would not execute

Re: [PATCH AArch64]Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address

On 20/11/15 08:31, Bin.Cheng wrote: > On Thu, Nov 19, 2015 at 10:32 AM, Bin.Cheng wrote: >> On Tue, Nov 17, 2015 at 6:08 PM, James Greenhalgh >> wrote: >>> On Tue, Nov 17, 2015 at 05:21:01PM +0800, Bin Cheng wrote: Hi, GIMPLE IVO needs

Re: [PATCH] Add clang-format config to contrib folder

On 11/20/2015 04:33 AM, Martin Liška wrote: On 11/19/2015 06:43 PM, Pedro Alves wrote: On 11/19/2015 12:54 PM, Martin Liška wrote: ContinuationIndentWidth: 2 -ForEachMacros:

Re: [PATCH 4/4][AArch64] Add cost model for Exynos M1

On Thu, Nov 19, 2015 at 04:06:17PM -0600, Evandro Menezes wrote: > On 11/05/2015 06:09 PM, Evandro Menezes wrote: > >2015-10-25 Evandro Menezes > > > > gcc/ > > > > * config/aarch64/aarch64-cores.def: Use the Exynos M1 cost model. > > *

Re: RFC/RFA: Fix bug with REE optimization corrupting extended registers

On 11/20/2015 02:19 AM, Nick Clifton wrote: Hi Jeff, The code there would solve this problem, but the approach is is overly cautious, since it disables the optimization for all extensions that increase the number of hard registers used. Some of these will be viable candidates, provided that

Re: [PATCH] Add LANG_HOOKS_EMPTY_RECORD_P for C++ empty class

On Tue, Nov 17, 2015 at 4:22 AM, Richard Biener wrote: > On Tue, Nov 17, 2015 at 12:01 PM, H.J. Lu wrote: >> Empty record should be returned and passed the same way in C and C++. >> This patch adds LANG_HOOKS_EMPTY_RECORD_P for C++ empty class,

Re: [PATCH 6/n] OpenMP 4.0 offloading infrastructure: option handling

On Wed, Dec 10, 2014 at 01:48:21 +0300, Ilya Verbin wrote: > On 09 Dec 14:59, Richard Biener wrote: > > On Mon, 8 Dec 2014, Ilya Verbin wrote: > > > Unfortunately, this fix was not general enough. > > > There might be cases when mixed object files get into lto-wrapper, ie > > > some of > > > them

Re: [PATCH, VECTOR ABI] Add __attribute__((__simd__)) to GCC.

On 11/20/2015 05:15 AM, Kyrill Tkachov wrote: Hi Kirill, On 18/11/15 14:11, Kirill Yukhin wrote: Hello Andreas, Devid. On 18 Nov 10:45, Andreas Schwab wrote: Kirill Yukhin writes: diff --git a/gcc/testsuite/c-c++-common/attr-simd.c

RFA: PATCH to match.pd for c++/68385

In this bug, we hit the (A & sign-bit) != 0 -> A < 0 transformation. Because of delayed folding, the operands aren't fully folded yet, so we have NOP_EXPRs around INTEGER_CSTs, and so calling wi::only_sign_bit_p ICEs. We've been seeing several similar bugs, where code calls integer_zerop and

Re: [PATCH] (Partial) Implementation of simplificaiton of CSHIFT

On Thu, Nov 19, 2015 at 04:58:36PM -0800, Steve Kargl wrote: > > 2015-11-19 Steven G. Kargl > > * intrinsic.h: Prototype for gfc_simplify_cshift > * intrinsic.c (add_functions): Use gfc_simplify_cshift. > * simplify.c (gfc_simplify_cshift): Implement

Re: RFA: PATCH to match.pd for c++/68385

On 11/20/2015 02:58 PM, Jason Merrill wrote: OK if testing passes? Which it did. Jason

[PATCH] Fix up reduction-1{1,2} testcases (PR middle-end/68221)

Hi! If C/C++ array section reductions have non-zero (positive) bias, it is implemented by declaring a smaller private array and subtracting the bias from the start of the private array (because valid code may only dereference elements from bias onwards). But, this isn't something that is kosher

[PATCH] Fix debug info related ICE when inlining back fnsplit function (PR debug/66432)

Hi! This patch fixes ICE where a parameter mentioned in a debug source bind has its VLA type mistakenly remapped and that leads to inconsistent type between the PARM_DECL and SSA_NAMEs derived from it. The patch Tom posted for this can't work, because we assume that the s=> value as well as

[PATCH] Fix GC ICE during simd clone creation (PR middle-end/68339)

Hi! node->get_body () can run various IPA passes and ggc_collect in them, so it is undesirable to hold pointers to GC memory in automatic vars over it. While I could store those vars (clone_info, clone and id) into special GTY vars just to avoid collecting them, it seems easier to call

[PATCH] Fix PR objc/68438 (uninitialized source ranges)

The attached patch fixes some more places in c/c-parser.c where the src_range field of a c_expr was being left uninitialized, this time for various Objective C constructs. The source ranges are verified using the same unit-testing plugin used for C expressions. This leads to a wart, which is

Re: Remove noce_mem_write_may_trap_or_fault_p in ifcvt

On 11/20/2015 07:08 AM, Bernd Schmidt wrote: BZ27313 is marked as fixed by the introduction of the tree cselim pass, thus the problem won't even be seen at RTL level. Cool. I'm undecided on whether cs-elim is safe wrt the store speculation vs locks concerns raised in the thread discussing

[commit] [patch] Python Pretty Printers get disabled on libstdc++ reload by GDB (PR libstdc++/68448)

On Fri, 20 Nov 2015 18:40:46 +0100, Jonathan Wakely wrote: > The patch is OK for trunk and gcc-5-branch. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68448 trunk: https://gcc.gnu.org/viewcvs/gcc?view=revision=230669 5.x: https://gcc.gnu.org/viewcvs/gcc?view=revision=230670 Jan

libgo patch committed: use correct tool dir with gccgo

This patch from Lynn Boger fixes the go tool shipped with gccgo to use the correct tool directory. It also fixes the 'go tool' output to only list known tools. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline and GCC 5 branch. Ian Index: gcc/go/gofrontend/MERGE

Re: [PATCH 3b/4][AArch64] Add scheduling model for Exynos M1

On 11/20/2015 11:17 AM, James Greenhalgh wrote: On Tue, Nov 10, 2015 at 11:54:00AM -0600, Evandro Menezes wrote: 2015-11-10 Evandro Menezes gcc/ * config/aarch64/aarch64-cores.def: Use the Exynos M1 sched model. * config/aarch64/aarch64.md:

[SPARC] Minor cleanup

This just moves the VIS3 mulx patterns to a more appropriate place. Tested on SPARC/Solaris, applied on the mainline. 2015-11-20 Eric Botcazou * config/sparc/sparc.md (umulxhi_vis): Move around. (*umulxhi_sp64): Likewise. (umulxhi_v8plus):

Re: [PATCH] Add LANG_HOOKS_EMPTY_RECORD_P for C++ empty class

On 11/20/2015 01:52 PM, H.J. Lu wrote: On Tue, Nov 17, 2015 at 4:22 AM, Richard Biener wrote: On Tue, Nov 17, 2015 at 12:01 PM, H.J. Lu wrote: Empty record should be returned and passed the same way in C and C++. This patch adds

Re: RFC/RFA: Fix bug with REE optimization corrupting extended registers

On 11/20/2015 02:19 AM, Nick Clifton wrote: Hi Jeff, The code there would solve this problem, but the approach is is overly cautious, since it disables the optimization for all extensions that increase the number of hard registers used. Some of these will be viable candidates, provided that

Re: RFC/RFA: Fix bug with REE optimization corrupting extended registers

> I would hazard a guess that the authors simply didn't consider the > multi-hard reg case. Essentially if the original set reached an > extension, then obviously the original set got there unharmed and the > extended destination should reach as well -- except that doesn't apply > to multi-word

Re: [PATCH] g++.dg/init/vbase1.C and g++.dg/cpp/ucn-1.C

On Nov 16, 2015, at 6:02 AM, Renlin Li wrote: > On 14/11/15 00:33, David Edelsohn wrote: >> No RISC architecture can store directly to MEM, so the expected RTL in >> g++.dg/init/vbase1.C is wrong. I am adding XFAIL for PowerPC. This >> probably should be disabled for ARM and

Re: [PATCH PR52272]Be smart when adding iv candidates

On Wed, Nov 18, 2015 at 11:50 PM, Bernd Schmidt wrote: > On 11/10/2015 11:19 AM, Bin.Cheng wrote: >> >> On Tue, Nov 10, 2015 at 6:06 PM, Bernd Schmidt >> wrote: >>> >>> >>> Multi-line expressions should be wrapped in parentheses so that >>> emacs/indent

Re: [PATCH][RTL-ree] PR rtl-optimization/68194: Restrict copy instruction in presence of conditional moves

On 20/11/15 01:41, Bernd Schmidt wrote: I1 is def_insn, I3 is cand->insn. tmp_reg is 'ax'. What we want to do is reject this transformation because the destination of def_insn (aka I1), that is 'ax', is not the operand of the extend operation in cand->insn (aka I3). As you said, rtx_equal won't

Re: RFC/RFA: Fix bug with REE optimization corrupting extended registers

Hi Jeff, The code there would solve this problem, but the approach is is overly cautious, since it disables the optimization for all extensions that increase the number of hard registers used. Some of these will be viable candidates, provided that the extra hard registers are no used. (This is

[PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

When vectorising a integer induction condition reduction, is_nonwrapping_integer_induction ends up with different values for base during the analysis and build phases. In the first it is an INTEGER_CST, in the second the loop has been vectorised out and the base is now a variable. This results in

libgo patch committed: Handle DW_AT_specification in cgo

The earlydebug work has caused https://gcc.gnu.org/PR68072 when using the cgo tool. The patch to fix this in the master sources is https://golang.org/cl/17151 . This patch fixes the problem in the gccgo sources. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline

Re: [PATCH] Fix PR objc/68438 (uninitialized source ranges)

On Fri, 20 Nov 2015, David Malcolm wrote: > The source ranges are verified using the same unit-testing plugin used > for C expressions. This leads to a wart, which is that it means having > a .m test file lurking below gcc.dg/plugin. A workaround would be to > create an objc.dg/plugin

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