[PATCH][GCC][AArch64] Restrict lrint inlining on ILP32.

Hi All, The inlining of lrint isn't valid in all cases on ILP32 when -fno-math-errno is used because an inexact exception is raised in certain circumstances. Instead the restriction is placed such that the integer mode has to be larger or equal to the float mode in addition to either inexacts

Re: [ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated

Hi, On 12 October 2016 at 11:22, Christophe Lyon wrote: > On 12 October 2016 at 11:14, Kyrill Tkachov > wrote: >> >> On 12/10/16 09:59, Christophe Lyon wrote: >>> >>> Hi Kyrill, >>> >>> On 7 October 2016 at 17:00, Kyrill Tkachov

[PATCH] Fix libstdc++ tests using invalid effective-target

The c++11 effective-target isn't supported on gcc-5-branch, so these tests need to use dg-options instead. (I'll be glad when we close gcc-5-branch and I don't have to remember this!) One of the tests FAILed when this was fixed, because it was also using a constructor of

Re: [PATCH] Factor out division by squares and remove division around comparisons (0/2)

On 09/13/2017 04:45 PM, Jeff Law wrote: On 09/06/2017 03:54 AM, Jackson Woodruff wrote: Hi all, This patch is split from part (1/2). It includes the patterns that have been moved out of fold-const.c It also removes an (almost entirely) redundant pattern: (A / C1) +- (A / C2) -> A *

[PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension

This is a patch for PR target/77729 on aarch64.  The code is doing an unneeded zero extend ('uxtb' in the original report, 'and' in the ToT sources). The patch looks a bit odd, it is a specialized define_insn for the combine pass.  At some point in combine (I never did find out where), the

Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension

Hi Steve, On 13/09/17 17:50, Steve Ellcey wrote: This is a patch for PR target/77729 on aarch64. The code is doing an unneeded zero extend ('uxtb' in the original report, 'and' in the ToT sources). The patch looks a bit odd, it is a specialized define_insn for the combine pass. At some

Re: [PATCH] PR libstdc++/81468 constrain std::chrono::time_point constructor

On 13/09/17 15:09 +0100, Jonathan Wakely wrote: Howard reported this bug, caused by a missing SFINAE constraint on a std::chrono::time_point constructor. I've also done a bit of simplification using alias templates. Here's the backport for the branches, which just adds the constraint (and

Re: C PATCH to fix ICE with -Wsizeof-array-argument (PR c/82167)

On 09/13/2017 05:00 AM, Marek Polacek wrote: > This fixes a segv, where -Wsizeof-array-argument crashed because > expr.original_type was null. It was null because for sizeof (*) > we go to c_parser_unary_expression's case CPP_AND: and case CPP_MULT:, > and that removes the original_type. But we

Re: [AArch64, PATCH] Improve Neon store of zero

On Wed, Sep 13, 2017 at 05:34:56PM +0100, Jackson Woodruff wrote: > Hi, > > I have addressed the issues you raised below. > > Is the amended patch OK for trunk? Yes, thanks. Committed as revision 252387. Cheers, James

Re: [PATCH, rs6000] [v2] Folding of vector loads in GIMPLE

On Sep 13, 2017, at 7:23 AM, Richard Biener wrote: > > On Tue, Sep 12, 2017 at 11:08 PM, Will Schmidt > wrote: >> Hi, >> >> [PATCH, rs6000] [v2] Folding of vector loads in GIMPLE >> >> Folding of vector loads in GIMPLE. >> >> Add code to

Re: C/C++ PATCH to add __remove_qualifiers (PR c/65455, c/39985)

On Sat, 9 Sep 2017, Jason Merrill wrote: > > +@code{__remove_qualifiers} takes a typename as an argument: > > I think it would be better to use the term "type-id" here, to avoid > confusion with "type-name", which is only a single identifier. There's no such thing as a type-id in C, and

RE: 0001-Part-1.-Add-generic-part-for-Intel-CET-enabling

> -Original Message- > From: Tsimbalist, Igor V > Sent: Tuesday, September 12, 2017 5:59 PM > To: 'Jeff Law' ; 'gcc-patches@gcc.gnu.org' patc...@gcc.gnu.org> > Cc: Tsimbalist, Igor V > Subject: RE:

Re: [AArch64, PATCH] Improve Neon store of zero

Hi, I have addressed the issues you raised below. Is the amended patch OK for trunk? Thanks, Jackson. On 09/12/2017 05:28 PM, James Greenhalgh wrote: On Wed, Sep 06, 2017 at 10:02:52AM +0100, Jackson Woodruff wrote: Hi all, I've attached a new patch that addresses some of the issues

Re: [PATCH] Add a -Wcast-align=strict warning

What does this warning do in cases where a type has different alignments inside and outside structs? I'm thinking of something like struct s { long long x; } *p; /* ... */ (long long *)p on 32-bit x86 - where long long's preferred alignment is 8 bytes, but in structures it's 4 bytes.

Re: [PATCH] Factor out division by squares and remove division around comparisons (0/2)

On 09/13/2017 03:22 AM, Jackson Woodruff wrote: > On 09/12/2017 11:43 PM, Jeff Law wrote: >> On 09/06/2017 03:54 AM, Jackson Woodruff wrote: >>> Hi all, >>> >>> This patch is split from part (1/2). It includes the patterns that have >>> been moved out of fold-const.c >>> >>> >>> It also removes an

[PATCH][Aarch64] Improve int<->FP conversions

Resending this patch as I did not have the correct subject line. This patch improves the latency of code by eliminating two FP <-> integer register transfers. An example: float f1(float x) { int y = x; return (float)y; } Trunk generates: f1: fcvtzs w0, s0 scvtf s0, w0

Re: Fwd: Undeliverable: Re: [doc,libgomp] Updates for www.openacc.org URLs

Hi! On Fri, 8 Sep 2017 10:25:06 -0700, Mike Stump wrote: > Do you know if James wants to remain on the MAINTAINERS list? If so, the > email address should be updated. Jim has left the company, and I'm afraid I don't know about another email address. So I committed the

Re: C/C++ PATCH to add __remove_qualifiers (PR c/65455, c/39985)

This patch (for C) is setting c_inhibit_evaluation_warnings and in_remove_qualifiers and doing corresponding use of pop_maybe_used, but I don't see the need for that. Expressions within the argument to __remove_qualifiers are evaluated exactly if they would be evaluated in the containing

Re: [PATCH] Factor out division by squares and remove division around comparisons (1/2)

On 09/06/2017 03:55 AM, Jackson Woodruff wrote: > On 08/30/2017 01:46 PM, Richard Biener wrote: >> On Wed, Aug 30, 2017 at 11:46 AM, Jackson Woodruff >> wrote: >>> On 08/29/2017 01:13 PM, Richard Biener wrote: On Tue, Aug 29, 2017 at 1:35 PM, Jackson

Turn CANNOT_CHANGE_MODE_CLASS into a hook

This also seemed like a good opportunity to reverse the sense of the hook to "can", to avoid the awkward double negative in !CANNOT. Tested on aarch64-linux-gnu, x86_64-linux-gnu and powerpc64le-linux-gnu. Also tested by comparing the testsuite assembly output on at least one target per CPU

Re: Add option for whether ceil etc. can raise "inexact", adjust x86 conditions

On Wed, 13 Sep 2017, Martin Jambor wrote: > I was just surprised by the glibc check, what would you consider a > recent-enough glibc? Or is the check mainly necessary to ensure we > are indeed using glibc and not some other libc (and thus something > like we do for TARGET_LIBC_PROVIDES_SSP would

Re: 0001-Part-1.-Add-generic-part-for-Intel-CET-enabling

On 09/12/2017 09:40 AM, Tsimbalist, Igor V wrote: > >> -Original Message- >> From: Jeff Law [mailto:l...@redhat.com] >> Sent: Friday, August 25, 2017 10:32 PM >> To: Richard Biener ; Tsimbalist, Igor V >> >> Cc:

Turn TRULY_NOOP_TRUNCATION into a hook

I'm not sure the documentation is correct that outprec is always less than inprec, and each non-default implementation tested for the case in which it wasn't, but the patch leaves it as-is. The SH port had a couple of TRULY_NOOP_TRUNCATION tests that were left over from the old shmedia port.

Re: [PATCH] [ARC] Check the assembler for gdwarf2 support.

On 09/12/2017 05:06 AM, Claudiu Zissulescu wrote: > From: claziss > > This small patch enables the gcc driver to pass dwarf related options to the > assembler. > > Ok to apply? > Claudiu > > gcc/ > 2017-06-21 Claudiu Zissulescu > > *

Re: [PATCH] Fix emission of exception dispatch (PR middle-end/82154).

On 09/13/2017 08:41 PM, Jeff Law wrote: On 09/13/2017 12:09 PM, Martin Liška wrote: On 09/13/2017 04:22 PM, Jeff Law wrote: On 09/13/2017 07:42 AM, Martin Liška wrote: On 09/13/2017 03:08 PM, Martin Liška wrote: On 09/12/2017 05:21 PM, Jeff Law wrote: On 09/12/2017 01:43 AM, Martin Liška

Turn FUNCTION_ARG_OFFSET into a hook

Nice and easy, one definition and one use :-) Tested on aarch64-linux-gnu, x86_64-linux-gnu and powerpc64le-linux-gnu. Also tested by comparing the testsuite assembly output on at least one target per CPU directory. OK to install? Richard 2017-09-13 Richard Sandiford

Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension

Hi! On Wed, Sep 13, 2017 at 06:13:50PM +0100, Kyrill Tkachov wrote: > +;; Specialized OR instruction for combiner. The AND is masking out bits > +;; not needed in the OR (doing a zero_extend). The zero_extend is not > +;; needed because we know from the subreg that the upper part of the reg >

Re: 0001-Part-1.-Add-generic-part-for-Intel-CET-enabling

On 09/13/2017 11:07 AM, Tsimbalist, Igor V wrote: >> -Original Message- >> From: Tsimbalist, Igor V >> Sent: Tuesday, September 12, 2017 5:59 PM >> To: 'Jeff Law' ; 'gcc-patches@gcc.gnu.org' > patc...@gcc.gnu.org> >> Cc: Tsimbalist, Igor V >>

Re: Add option for whether ceil etc. can raise "inexact", adjust x86 conditions

Hello, I apologize for not coming back to this, I keep on getting distracted. Anyway... On Tue, Aug 15, 2017 at 02:20:55PM +, Joseph Myers wrote: > On Tue, 15 Aug 2017, Martin Jambor wrote: > > > I am not sure what to do about this, to me it seems that the > > -ffp-int-builtin-inexact

[PATCH] Fix PR target/82066 - target pragma and attribute documentation for ARM, AArch64, and S/390

This patch fixes the documentation issues pointed out in PR target/82066. It may be considered obvious enough to just check in but I'd rather have someone look it over to make sure I didn't mess something up. Steve Ellcey sell...@cavium.com 2017-09-13  Steve Ellcey  

Re: [PATCH] Fix emission of exception dispatch (PR middle-end/82154).

On 09/13/2017 04:22 PM, Jeff Law wrote: On 09/13/2017 07:42 AM, Martin Liška wrote: On 09/13/2017 03:08 PM, Martin Liška wrote: On 09/12/2017 05:21 PM, Jeff Law wrote: On 09/12/2017 01:43 AM, Martin Liška wrote: Hello. In transition to simple_case_node, I forgot to initialize m_high to

Re: 0001-Part-1.-Add-generic-part-for-Intel-CET-enabling

On 09/12/2017 09:59 AM, Tsimbalist, Igor V wrote: > >> Q. Do we need to do anything with ICF (identical code folding) and CFE? >> Given two functions which have the same implementation in gimple, except >> that one has a notrack indirect call and the other has a tracked indirect >> call, >>

Re: [PATCH] Fix emission of exception dispatch (PR middle-end/82154).

On 09/13/2017 12:09 PM, Martin Liška wrote: > On 09/13/2017 04:22 PM, Jeff Law wrote: >> On 09/13/2017 07:42 AM, Martin Liška wrote: >>> On 09/13/2017 03:08 PM, Martin Liška wrote: On 09/12/2017 05:21 PM, Jeff Law wrote: > On 09/12/2017 01:43 AM, Martin Liška wrote: >> Hello. >>

Re: [PATCH] Add a -Wcast-align=strict warning

On 09/13/17 22:03, Joseph Myers wrote: > On Wed, 13 Sep 2017, Bernd Edlinger wrote: > >> On 09/13/17 19:06, Joseph Myers wrote: >>> What does this warning do in cases where a type has different alignments >>> inside and outside structs? I'm thinking of something like >>> >>> struct s { long long

Re: [PATCH] Add a -Wcast-align=strict warning

On 09/13/17 19:06, Joseph Myers wrote: > What does this warning do in cases where a type has different alignments > inside and outside structs? I'm thinking of something like > > struct s { long long x; } *p; > /* ... */ > (long long *)p > > on 32-bit x86 - where long long's preferred alignment

Re: [PATCH] Add a -Wcast-align=strict warning

On Wed, 13 Sep 2017, Bernd Edlinger wrote: > On 09/13/17 19:06, Joseph Myers wrote: > > What does this warning do in cases where a type has different alignments > > inside and outside structs? I'm thinking of something like > > > > struct s { long long x; } *p; > > /* ... */ > > (long long *)p

Re: [PATCH, rs6000] [v2] Folding of vector loads in GIMPLE

On Sep 13, 2017, at 10:40 AM, Bill Schmidt wrote: > > On Sep 13, 2017, at 7:23 AM, Richard Biener > wrote: >> >> On Tue, Sep 12, 2017 at 11:08 PM, Will Schmidt >> wrote: >>> Hi, >>> >>> [PATCH, rs6000] [v2]

Re: [PATCH] Factor out division by squares and remove division around comparisons (1/2)

Jeff Law wrote: > On 09/06/2017 03:55 AM, Jackson Woodruff wrote: > > On 08/30/2017 01:46 PM, Richard Biener wrote: >>>   rdivtmp = 1 / (y*C); >>>   tem = x *rdivtmp; >>>   tem2= z * rdivtmp; >>> >>> instead of >>> >>>   rdivtmp = 1/y; >>>   tem = x * 1/C * rdivtmp; >>>   tem2 = z * 1/C *

Re: Rb_tree constructor optimization

On 08/09/2017 17:50, Jonathan Wakely wrote: Since we know __a == __x.get_allocator() we could just do: _Rb_tree(_Rb_tree&& __x, _Node_allocator&&, true_type) noexcept(is_nothrow_move_constructible<_Rb_tree_impl<_Compare>>::value) : _M_impl(std::move(__x._M_impl)) { } This means

Re: [PATCH] Factor out division by squares and remove division around comparisons (0/2)

On 09/13/2017 10:25 AM, Jackson Woodruff wrote: > > > On 09/13/2017 04:45 PM, Jeff Law wrote: >> On 09/06/2017 03:54 AM, Jackson Woodruff wrote: >>> Hi all, >>> >>> This patch is split from part (1/2). It includes the patterns that have >>> been moved out of fold-const.c >>> >>> >>> It also

[PATCH] Fallout from -static-pie to GCC driver to create static PIE

On Wed, Sep 13, 2017 at 05:18:00AM -0700, H.J. Lu wrote: > > In LINK_EH_SPEC you use %{!static|static-pie:--eh-frame-hdr}, what > > exactly do you mean by that? The way that works is if -static > > isn't present on the command line OR if -static -static-pie OR > > -static-pie -static is present,

Re: [PATCH] Add a -Wcast-align=strict warning

On Wed, 13 Sep 2017, Bernd Edlinger wrote: > So you suggest to use min_align_of_type instead of TYPE_ALIGN. > > That would also make sense for the traditional -Wcast-align on > strict-alignment targets, right? Yes, and yes (though I'm not sure if any strict-alignment targets have this

[PATCH], Add support for __builtin_{sqrt,fma}f128 on PowerPC ISA 3.0

This patch adds support on PowerPC ISA 3.0 for the built-in function __builtin_sqrtf128 generating the XSSQRTQP hardware square root instruction and the built-in function __builtin_fmaf128 generating XSMADDQP, XSMSUBQP, XSNMADDQP, and XSNMSUBQP fused multiply-add instructions. While I was at it,

Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension

On Wed, 2017-09-13 at 14:46 -0500, Segher Boessenkool wrote: > On Wed, Sep 13, 2017 at 06:13:50PM +0100, Kyrill Tkachov wrote: > >  > > We are usually hesitant to add explicit subreg matching in the MD pattern > > (though I don't remember if there's a hard rule against it). > > In this case this

Re: [PATCH], Add support for __builtin_{sqrt,fma}f128 on PowerPC ISA 3.0

On Wed, 13 Sep 2017, Michael Meissner wrote: > This patch adds support on PowerPC ISA 3.0 for the built-in function > __builtin_sqrtf128 generating the XSSQRTQP hardware square root instruction > and > the built-in function __builtin_fmaf128 generating XSMADDQP, XSMSUBQP, > XSNMADDQP, and

[OpenACC] Enable SIMD vectorization on vector loops

This patch enables SIMD vectorization on non-SIMT targets in acc vector loops. It does does so by setting the force_vectorization flag in a similar manner to OpenMP SIMD loops. Unlike OpenMP, OpenACC provides the compiler with the flexibility to assign gang, worker and vector parallelism to

Re: [PATCH] Factor out division by squares and remove division around comparisons (0/2)

On 09/06/2017 03:54 AM, Jackson Woodruff wrote: > Hi all, > > This patch is split from part (1/2). It includes the patterns that have > been moved out of fold-const.c > > > It also removes an (almost entirely) redundant pattern: > > (A / C1) +- (A / C2) -> A * (1 / C1 +- 1 / C2) > > which

Re: [doc,libgomp] Updates for www.openacc.org URLs

Hi Gerald! On Fri, 8 Sep 2017 14:27:30 +0200, Gerald Pfeifer wrote: > We were nearly down to around a dozen of problematic links on > gcc.gnu.org and our online docs, when the following popped up: > www.openacc.org switched to https I can't tell what is "problematic" here,

Re: [ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated

Hi Christophe, On 13/09/17 16:23, Christophe Lyon wrote: Hi, On 12 October 2016 at 11:22, Christophe Lyon wrote: On 12 October 2016 at 11:14, Kyrill Tkachov wrote: On 12/10/16 09:59, Christophe Lyon wrote: Hi Kyrill, On 7 October

Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension

On Wed, 2017-09-13 at 22:39 +, Wilco Dijkstra wrote: > Steve Ellcey wrote: > > > And in aarch64 rtl expansion I see: > > > > (insn 10 9 11 (set (reg:QI 81) > > (mem:QI (reg/v/f:DI 80 [ string ]) [0 *string_9(D)+0 S1 > A8])) "pr77729.c":3 -1 > > (nil)) > > Yes using QI/HI mode

Go patch committed: fix check for notinheap conversion

In the Go frontend, a normal pointer may not be converted to a notinheap pointer. The frontend was erroneously permitting a conversion from a normal pointer to a notinheap unsafe.Pointer, which is useless since unsafe.Pointer is not marked notinheap. This patch corrects the test to permit a

Go patch committed: Fix struct field names for embedded aliases

This patch to the Go frontend adds much of https://golang.org/cl/35731 and https://golang.org/cl/35732, patches to the gc toolchain, to the gofrontend code. This is a step toward updating libgo to the 1.9 release. The gofrontend already supports type aliases, and this is required for correct

[PATCH] [i386, libgcc] PR 82196 -mcall-ms2sysv-xlogues emits wrong AVX/SSE MOV

I made a silly mistake in libgcc by testing the cpp macro __AVX__ to determine rather to use movaps or vmovaps in the stubs. This resulted in the stubs choice of instruction being decided by the machine flags when the compiler was built rather than those being supplied at the command line. This

Re: [PATCH] Fix PR 81096 (ttest failures)

On Tue, Sep 12, 2017 at 9:49 AM, Steve Ellcey wrote: > On Tue, 2017-09-12 at 09:39 -0700, Ian Lance Taylor wrote: >> On Tue, Sep 12, 2017 at 3:59 AM, Wilco Dijkstra > om> wrote: >> > >> > Steve Ellcey wrote: >> > > >> > > This patch fixes the ttest

Re: [PATCH] PR libstdc++/81468 constrain std::chrono::time_point constructor

On Wed, Sep 13, 2017 at 10:55 AM, Jonathan Wakely wrote: > > +// DR 1177 > +static_assert(is_constructible{}, > +"can convert duration with one floating point rep to another"); > +static_assert(is_constructible{}, > +"can convert

Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension

On Wed, Sep 13, 2017 at 10:41:33PM +, Wilco Dijkstra wrote: > Steve Ellcey wrote: > > > And in aarch64 rtl expansion I see: > > > > (insn 10 9 11 (set (reg:QI 81) > > (mem:QI (reg/v/f:DI 80 [ string ]) [0 *string_9(D)+0 S1 A8])) > > "pr77729.c":3 -1 > > (nil))​ > > Yes using

Go patch committed: emit type specific functions for aliases

When the Go frontend has an alias for a struct or array that requires a type-specific function, don't emit the function with the alias name. Emit it with the struct/array as usual. The test case is for this is https://golang.org/cl/62531. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu.

Go patch committed: avoid compiler crash on invalid programs

This minor patch to the Go frontend avoids crashing the compiler on some invalid programs. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === ---

Go patch committed: simplify select and channel operations

In preparation for upgrading libgo to the 1.9 release, this patch to the Go frontend approximately incorporates https://golang.org/cl/37661 and https://golang.org/cl/38351 from the gc toolchain. CL 37661 changed the gc compiler such that the select statement simply returns an integer which is

Re: [PATCH] Fallout from -static-pie to GCC driver to create static PIE

On Wed, Sep 13, 2017 at 10:19:50PM +0200, Jakub Jelinek wrote: > On Wed, Sep 13, 2017 at 05:18:00AM -0700, H.J. Lu wrote: > > > In LINK_EH_SPEC you use %{!static|static-pie:--eh-frame-hdr}, what > > > exactly do you mean by that? The way that works is if -static > > > isn't present on the command

Re: [PATCH] Fallout from -static-pie to GCC driver to create static PIE

On Wed, 13 Sep 2017, Jakub Jelinek wrote: > Ok. > > So here is an updated patch (also fixed whitespace in i386/gnu-user.h > because the indentation there didn't match the nesting). > > Bootstrapped/regtested on {x86_64,i686,powerpc64,powerpc64le}-linux, > ok for trunk? > At least the rs6000

Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension

Steve Ellcey wrote: > And in aarch64 rtl expansion I see: > > (insn 10 9 11 (set (reg:QI 81) > (mem:QI (reg/v/f:DI 80 [ string ]) [0 *string_9(D)+0 S1 A8])) > "pr77729.c":3 -1 > (nil))​ Yes using QI/HI mode anywhere in the RTL seems perverse and incorrect given AArch64 doesn't

Re: [PATCH version 2, rs6000] Add builtins to convert from float/double to int/long using current rounding mode

On Tue, Sep 12, 2017 at 07:17:07PM -0400, Michael Meissner wrote: > On Tue, Sep 12, 2017 at 05:41:34PM -0500, Segher Boessenkool wrote: > > This needs "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" I think? Which > > is the same as "TARGET_DF_FPR". "lrintdi2" also has "TARGET_FPRND" > > but that is

Re: [PATCH version 3, rs6000] Add builtins to convert from float/double to int/long using current rounding mode

GCC maintainers: The following patch has been updated to address Segher's comments. -- rename define insn "fctiw" to define_insn "lrintsfsi2" to match the fctid implementation -- add "TARGET_SF_FPR && TARGET_FPRND" to the define_insn "lrintsfsi2" as mentioned it was missing on the original

Re: [HSA, PR 82119] Make HSA resilient to side-effects of split_edge

On Mon, Sep 11, 2017 at 12:11 PM, Richard Biener wrote: > On September 11, 2017 11:03:39 AM GMT+02:00, Martin Jambor > wrote: >>Hi, >> >>in r251264 the code of split_edge was changed not to reallocate PHI >>vectors, but it reorders them along with

Re: [PATCH 2/3] [ARM] Refactor costs calculation for MEM.

Hi Charles, On 12/09/17 09:34, charles.bay...@linaro.org wrote: From: Charles Baylis This patch moves the calculation of costs for MEM into a separate function, and reforms the calculation into two parts. Firstly any additional cost of the addressing mode is

Re: [PATCH] Fix PR82128

On Tue, 12 Sep 2017, Richard Biener wrote: > > This is the one with the folding fix... And it didn't work out (the comment before the changed line even explains...). Thus I'll do the following. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2017-09-13 Richard Biener

Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params

Hi Charles, On 12/09/17 09:34, charles.bay...@linaro.org wrote: From: Charles Baylis Add bus widths. These use the approximation that v7 and later cores have 64bit data bus width, and earlier cores have 32 bit bus width, with the exception of v7m. Given the way

Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing modes.

Hi Charles, On 12/09/17 09:34, charles.bay...@linaro.org wrote: From: Charles Baylis This patch adds support for modelling the varying costs of different addressing modes. The generic cost table treats all addressing modes as having equal cost. gcc/ChangeLog:

Re: [PATCH] Factor out division by squares and remove division around comparisons (0/2)

On 09/12/2017 11:43 PM, Jeff Law wrote: On 09/06/2017 03:54 AM, Jackson Woodruff wrote: Hi all, This patch is split from part (1/2). It includes the patterns that have been moved out of fold-const.c It also removes an (almost entirely) redundant pattern: (A / C1) +- (A / C2) -> A * (1

[PATCH] Add GIMPLE verification for a few codes

This fills in some gaps in GIMPLE verification. It shows that for AVX vector boolean we use VEC_PACK_TRUNC_EXPR to essentially concat two vectors -- I think we shouldn't have done that but instead used { x, y } for this. But even the target got patterns for this so I let this bypass

Re: [PATCH] Add -static-pie to GCC driver to create static PIE

On Wed, Sep 13, 2017 at 08:57:39AM +0200, Markus Trippelsdorf wrote: > On 2017.09.12 at 13:48 -0500, Aaron Sawdey wrote: > > On Tue, 2017-09-12 at 16:20 +, Joseph Myers wrote: > > > On Mon, 28 Aug 2017, H.J. Lu wrote: > > > > > > > Here is the updated patch.   OK for trunk? > > > > > > OK. >

Re: [patch] Fix wrong code with small structure return on PowerPC

On Mon, Sep 11, 2017 at 9:59 PM, Eric Botcazou wrote: >> I think the issue is that we set SUBREG_PROMOTED_* on something that is >> possibly not so (aka uninitialized in this case). > > Yes, that's what I called inherent weakness of the promoted subregs mechanism. > >> We

Re: [PATCH, GCC/testsuite/ARM, ping3] Fix coprocessor intrinsic test failures on ARMv8-A

On 05/09/17 10:04, Thomas Preudhomme wrote: Ping? Best regards, Thomas On 23/08/17 11:59, Thomas Preudhomme wrote: Ping? Best regards, Thomas On 17/07/17 09:51, Thomas Preudhomme wrote: Ping? Best regards, Thomas On 12/07/17 14:31, Thomas Preudhomme wrote: Coprocessor intrinsic

Re: [PATCH] Add -static-pie to GCC driver to create static PIE

On 2017.09.12 at 13:48 -0500, Aaron Sawdey wrote: > On Tue, 2017-09-12 at 16:20 +, Joseph Myers wrote: > > On Mon, 28 Aug 2017, H.J. Lu wrote: > > > > > Here is the updated patch.   OK for trunk? > > > > OK. > > This seems to be causing an issue for me on powerpc: > >

[PATCH] Define std::__to_address helper

As discussed a few weeks ago, this adds a helper to get a raw pointer from any pointer-like type, and usees that helper where appropriate. * include/bits/allocated_ptr.h (__allocated_ptr::get): Use __to_address. (__allocated_ptr::_S_raw_ptr): Remove. *

[C++ PATCH] don't put conv-op names in identifier hash

This patch changes the conv-op identifier node creation. Conv-ops are never looked up by name, and there's no need for them to be in the identifier table. Which also means there's no need for them to have distinct names. This patch implements that. conv-op names are directly cloned from

Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params

Hi Charlie, I can't see any use for adding a bus width to tune params. There are many different buses in a modern CPU, so there is no such thing as a single "bus width". What we need is to add separate costs for the different kinds of loads and stores. The timings for these depend mostly on the

[PATCH][store-merging] Use store order as tie-breaker in sort_by_bitpos

Hi all, As Alexander pointed out in the thread starting at [1] the sort_by_bitpos sorting function was behaving badly when we had multiple stores at the same position. He fixed that (thanks!) but we can do better by not returning zero when the bitpositions are equal but by falling back to

Re: [PATCH] Fix -fcompare-debug issues in find_many_sub_basic_blocks (PR target/81325)

On Wed, 13 Sep 2017, Jakub Jelinek wrote: > Hi! > > The following testcase fails on powerpc64le with -fcompare-debug. > The problem is that find_many_sub_basic_blocks is called during > expansion on a basic block where originally two __atomic_fetch_add > calls have some debug stmts in between.

Re: [PATCH][GCC][ARM] Dot Product NEON patterns [Patch (2/8)]

Hi Tamar, On 01/09/17 14:33, Tamar Christina wrote: Hi All, This patch adds the instructions for Dot Product to ARM along with the intrinsics and vectorizer pattern. Armv8.2-a dot product supports 8-bit element values both signed and unsigned. Dot product is available from Armv8.2-a and

new Ada merger

This is a heads up that I am working with Pierre-Marie (in cc:) to transition my work as "AdaCore merger" - aka the person who submits most of AdaCore front-end changes in GCC - over to him. Pierre-Marie has already write-after-approval and has submitted and committed many patches already in the

Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]

Hi Tamar, On 01/09/17 14:19, Tamar Christina wrote: Hi All, This patch adds support for the +dotprod extension to ARM. Dot Product requires Adv.SIMD to work and so enables this option by default when enabled. It is available from ARMv8.2-a and onwards and is enabled by default on Cortex-A55

[wwwdocs] Tweak a link in gcc-4.3/porting_to.html

Just another server moving to https, this time crustytoothpaste.ath.cx. Applied. Gerald Index: gcc-4.3/porting_to.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.3/porting_to.html,v retrieving revision 1.14 diff -u -r1.14

[PATCH] Fix -fcompare-debug issues in find_many_sub_basic_blocks (PR target/81325)

Hi! The following testcase fails on powerpc64le with -fcompare-debug. The problem is that find_many_sub_basic_blocks is called during expansion on a basic block where originally two __atomic_fetch_add calls have some debug stmts in between. The rs6000 backend expands those atomic calls into a

[Ada] Review dependency tracking for Ada sources without -gnatd.n support

This patch will fix build glitches for parallelized Ada builds, which started to appear after the Makefile changes that came with the recent libgnat/libgnarl reorganization. Specifically, it fixes the detection of dependencies between Ada units for builds based on Ada compilers that don’t

Re: [PATCH][store-merging] Use store order as tie-breaker in sort_by_bitpos

On Wed, Sep 13, 2017 at 3:02 PM, Kyrill Tkachov wrote: > Hi all, > > As Alexander pointed out in the thread starting at [1] the sort_by_bitpos > sorting function > was behaving badly when we had multiple stores at the same position. He > fixed that (thanks!) > but

Re: [PATCH] Fix emission of exception dispatch (PR middle-end/82154).

On 09/12/2017 05:21 PM, Jeff Law wrote: > On 09/12/2017 01:43 AM, Martin Liška wrote: >> Hello. >> >> In transition to simple_case_node, I forgot to initialize m_high to m_low if >> a case >> does not have CASE_HIGH. >> >> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests.

Re: [AArch64, patch] Refactor of aarch64-ldpstp.md

Hi, Since I rebased the patch that this is based on, I have also rebased this patch. Jackson. On 09/12/2017 07:15 PM, Jackson Woodruff wrote: Hi all, This patch removes a lot of duplicated code in aarch64-ldpstp.md. The patterns that did not previously generate a base register now do not

Re: [AArch64] Merge stores of D register values of different modes

On 09/12/2017 07:32 PM, Richard Sandiford wrote: Thanks for doing this, looks good to me FWIW. I was just wondering: Jackson Woodruff writes: @@ -14712,6 +14712,11 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, if (!rtx_equal_p (base_1,

Re: [PATCH] Fix emission of exception dispatch (PR middle-end/82154).

On 09/13/2017 03:08 PM, Martin Liška wrote: > On 09/12/2017 05:21 PM, Jeff Law wrote: >> On 09/12/2017 01:43 AM, Martin Liška wrote: >>> Hello. >>> >>> In transition to simple_case_node, I forgot to initialize m_high to m_low >>> if a case >>> does not have CASE_HIGH. >>> >>> Patch can bootstrap

[Aarch64, Patch] Update failing testcase pr62178.c

Hi all, This patch changes pr62178.c so that it now scans for two `ldr`s, one into an `s` register, instead of a `ld1r` as before. Also add a scan for an mla instruction. The `ld1r` was needed when this should have generated a mla by vector. Now that we can generate an mla by element

[C++ PATCH] rename METHOD_VEC to MEMBER_VEC

Now that we hold all members on the sorted METHOD_VEC, that's no longer a suitable name. This patch renames the macro and all associated functions from method_vec_foo to member_vec_foo. Applied to trunk. This wraps up my current effort of class member lookup cleaning. nathan -- Nathan

Re: [PATCH][AArch64] Remove '*' from movsi/di/ti patterns

Andrew Pinski wrote: > > Note this caused a few testsuite failures: Confirmed. The diffs show the new sequence is always better. I've committed this: Update vmov_n_1.c now we are generating better code for dup: ldr s0, [x0] dup v0.2s, v0.s[0] ret Instead of:

Re: [PATCH, rs6000] [v2] Folding of vector loads in GIMPLE

On Tue, Sep 12, 2017 at 11:08 PM, Will Schmidt wrote: > Hi, > > [PATCH, rs6000] [v2] Folding of vector loads in GIMPLE > > Folding of vector loads in GIMPLE. > > Add code to handle gimple folding for the vec_ld builtins. > Remove the now obsoleted folding code for

[Ada] vxworks: auto-registration of foreign threads

To make Ada tasks and C threads interoperate better, we have added some functionality to Self. Suppose a C main program (with threads) calls an Ada procedure and the Ada procedure calls the tasking runtime system. Eventually, a call will be made to self. Since the call is not coming from an Ada

[Ada] Ineffective pragma Suppress (Alignment_Check) on warning

On platforms that require strict alignment of memory accesses, the per-object form of pragma Suppress (Alignment_Check) also disables the alignment warning associated with the check. That's not the case for the global form and this change fixes the inconsistency. Here's an example on a small

Re: [PATCH][ARM] Remove Thumb-2 iordi_not patterns

Hi Wilco, On 04/09/17 20:56, Wilco Dijkstra wrote: Kyrill Tkachov wrote: After Bernd's change almost all DI mode instructions are split before register allocation. So instructions using DI mode no longer exist and thus these extend variants can never be matched and are thus redundant.

[Ada] Undefined symbol at link time due to Disable_Controlled

This patch reimplements aspect Disable_Controlled to plug the following holes in its original implementation: * The aspect may appear without an expression in which case the aspect defaults to True, however the compiler would crash due to the lack of expression. * If the

[PATCH] PR libstdc++/81835 fix broken URLs in libstdc++ docs

PR libstdc++/81835 * doc/xml/manual/extensions.xml: Replace unstable URL. * doc/html/manual/ext_demangling.html: Regenerate. * libsupc++/cxxabi.h (__cxa_demangle): Fix broken URL. Committed to trunk, will backport too. commit

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