Yang Yujie writes:
> @@ -5171,25 +5213,21 @@ case "${target}" in
> # ${with_multilib_list} should not contain whitespaces,
> # consecutive commas or slashes.
> if echo "${with_multilib_list}" \
> - | grep -E -e "[[:space:]]" -e '[,/][,/]' -e
On Wed, Sep 06, 2023 at 07:43:26AM +0100, Richard Sandiford wrote:
> Yang Yujie writes:
> > @@ -5171,25 +5213,21 @@ case "${target}" in
> > # ${with_multilib_list} should not contain whitespaces,
> > # consecutive commas or slashes.
> > if echo
On Tue, Sep 05, 2023 at 03:07:15PM -0700, Andrew Pinski wrote:
> Note I notice another all to build_nonstandard_integer_type in this
> match pattern which might also need to be fixed:
> /* For (x << c) >> c, optimize into x & ((unsigned)-1 >> c) for
>unsigned x OR truncate into the
According to the doc, take“Mask(VECTOR_ELEN_32)
Var(riscv_vector_elen_flags)”as example,
it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate
MASK_VECTOR_ELEN_32
and TARGET_VECTOR_ELEN_32.
Do you want to use "MASK(name) Var(other_flags)" to generate the MASK and
TARGET
I saw RVC has MASK_RVC and TARGET_RVC in options.h?
On Wed, Sep 6, 2023 at 2:39 PM Feng Wang wrote:
>
> According to the doc, take“Mask(VECTOR_ELEN_32)
> Var(riscv_vector_elen_flags)”as example,
> it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate
> MASK_VECTOR_ELEN_32
>
Yang Yujie writes:
> gcc/ChangeLog:
>
> * config.gcc: remove non-POSIX syntax "<<<".
OK. Thanks for the quick fix.
Richard.
> ---
> gcc/config.gcc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index b2fe7c7ceef..6d4c8becd28
Committed, thanks Robin.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Robin Dapp via Gcc-patches
Sent: Wednesday, September 6, 2023 9:39 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Remove
Committed, thanks Robin.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Robin Dapp via Gcc-patches
Sent: Wednesday, September 6, 2023 9:38 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS
Fix bugzilla: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295
PR target/111295
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (insert_vsetvl):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr111295.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc
From: Pan Li
Put the test file to the incorrect folder, this patch would like to
fix it.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: Moved to...
* gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c: ...here.
Signed-off-by: Pan Li
---
Committed, thanks Juzhe and sorry for my silly mistake.
Pan
From: juzhe.zhong
Sent: Wednesday, September 6, 2023 8:53 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case
Hi Juzhe,
general remark upfront: Please add function-level comments for all
functions. This makes reading and reviewing much easier. I had to sweep
back and forth quite a bit.
> +
> +static int
> +get_last_live_range (const vec _ranges, tree var)
> +{
> + unsigned int ix;
> +
Hi Lehua,
> May I ask if the compiler options "-march=rv64gcv_zvfh -mabi=lp64d"
> should be removed? Because we don't specify -march and -mabi when we
> run testcase (so but why we need to specify the -march and -mabi in
> this target check?), we run it with the default values. Assuming that
>
OK.
Regards
Robin
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-3740-gb51cde34d4e750.
gcc/analyzer/ChangeLog:
PR analyzer/105899
* kf.cc (class kf_strncpy): New.
(kf_strncpy::impl_call_post): New.
(register_known_functions): Register it.
I noticed that region_model's fill_region/zero_fill_region member
functions weren't checking that the write to the region was valid.
Fixed thusly.
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-3739-gb923978a6ec447.
gcc/analyzer/ChangeLog:
* kf.cc
Hi David,
Thanks for the review.
On Tue, Sep 5, 2023 at 1:53 PM David Malcolm wrote:
> On Mon, 2023-09-04 at 20:00 +0200, priour...@gmail.com wrote:
>
>
[...snip...]
> All of these "new" tests (apart from the "-noexcept" ones) look like
> they're meant to be existing tests that were moved,
Hi.
I'll do another test to make sure this is enough since I tested with a
few more finalize functions.
Thanks a lot for finding this!
On Wed, 2023-09-06 at 09:40 -0400, David Malcolm via Jit wrote:
> As part of Antoyo's work on supporting LTO in rustc_codegen_gcc, he
> noticed an ICE inside
On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote:
> From: David Malcolm
I guess I can review this patch :)
Needs a ChangeLog entry, so here's one:
gcc/ChangeLog
* diagnostic-core.h (error_meta): New decl.
* diagnostic.cc (error_meta): New.
Also, needs a signed-off-by, so
This patch implements noncontiguous "target update" for Fortran.
The existing middle end/runtime bits relating to C and C++ support are
reused, with some small adjustments, e.g.:
1. The node used to map the OMP "array descriptor" (from omp-low.cc
onwards) now uses the OMP_CLAUSE_SIZE field
At present, map/to/from clauses on OpenMP "target" directives may be
expanded into several mapping nodes if they describe array sections with
pointer or reference bases, or similar. This patch allows the original
clause to be replaced during that expansion, mostly by passing the list
pointer to
gcc/ChangeLog:
* config.gcc: remove non-POSIX syntax "<<<".
---
gcc/config.gcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index b2fe7c7ceef..6d4c8becd28 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5189,7 +5189,7 @@ case
From: Christoph Müllner
The test was introduced recently and tests a RV64-only feature.
However, when testing an RV32 compiler, the test gets executed as well
and fails with "cc1: error: ABI requires '-march=rv32'".
This patch fixes this by adding '-mabi=lp64' (like it is done for
other
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x, 1)
> and (x
Forgot to mention: I've bootstrapped and regtested this patch on
loongarch64-linux-gnu (with PR110939 patch applied to unbreak the
bootstrapping). Ok for trunk?
On Wed, 2023-09-06 at 18:46 +0800, Xi Ruoyao wrote:
> If mask is a constant with value ((1 << N) - 1) << M we can perform this
>
Committed, thanks Kito.
--
Best,
Lehua
Previously, I add TARGET_64BIT condtion to block VLS modes with size = 64bit
in RV32 system
E.g. V8QI
Since I realized such modes may cause inferior codegen for some situations in
RV32 system.
However, this is really quite ugly and it cause ICE for some cases in RV32:
FAIL:
This patch covers signed and unsigned additions. The generated code
would be something along these lines:
signed:
add.f r0, r1, r2
b.v @label
unsigned:
add.f r0, r1, r2
b.c @label
gcc/ChangeLog:
* config/arc/arc-modes.def: Add CC_V mode.
*
This patch covers signed and unsigned subtractions. The generated code
would be something along these lines:
signed:
sub.f r0, r1, r2
b.v @label
unsigned:
sub.f r0, r1, r2
b.c @label
gcc/ChangeLog:
* config/arc/arc.md (subsi3_v): New insn.
(subvsi4): New
From: David Malcolm
---
gcc/diagnostic-core.h | 3 +++
gcc/diagnostic.cc | 15 +++
2 files changed, 18 insertions(+)
diff --git a/gcc/diagnostic-core.h b/gcc/diagnostic-core.h
index 7334c79e8e6..c9e27fd2e6e 100644
--- a/gcc/diagnostic-core.h
+++ b/gcc/diagnostic-core.h
@@
From: David Malcolm
---
gcc/rust/rust-diagnostics.cc | 11 +++
gcc/rust/rust-diagnostics.h | 18 ++
gcc/rust/rust-gcc-diagnostics.cc | 33 +++
gcc/rust/typecheck/rust-casts.cc | 2 +-
This short patchset from David Malcolm enables errors to contain extra
metadata - this is particularly useful for the Rust frontend, which will
rely on that implementation to emit standard Rust error codes [1].
This series of patches is necessary for much of our more recent
additions to the
On 9/6/23 03:47, Juzhe-Zhong wrote:
This patch fix incorrect mode tieable between DI and V2SI which cause ICE
in RA.
PR target/111296
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug.
gcc/testsuite/ChangeLog:
*
LGTM.
Regards
Robin
As part of Antoyo's work on supporting LTO in rustc_codegen_gcc, he
noticed an ICE inside libgccjit when compiling certain rust files.
Debugging libgccjit showed that outdated information from a previous
in-memory compile was referring to ad-hoc locations in the previous
compile's line_table.
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-3741-gf2d7a4001a3388.
gcc/analyzer/ChangeLog:
PR analyzer/105899
* kf.cc (class kf_strstr): New.
(kf_strstr::impl_call_post): New.
(register_known_functions): Register it.
On 9/5/23 23:47, Tsukasa OI wrote:
From: Tsukasa OI
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.
And most notably (for historical reasons), 'XVentanaCondOps' and the
Thanks for explaining, LGTM :)
On Mon, Sep 4, 2023 at 11:39 PM Lehua Ding wrote:
>
> Hi Kito,
>
> > Can those intermediate patterns be used for intrinsic? I would prefer
> > to keep those stuff *IF* possible used for intrinsics.
>
> I think we don't need those patterns for intrinisc. First, the
reminder: ready for commit?
- Javier
On Wed 23. Aug 2023 at 15:02, Javier Martinez <
javier.martinez.bugzi...@gmail.com> wrote:
> On Tue, Aug 22, 2023 at 7:50 PM Jason Merrill wrote:
> > You still need an update to doc/extend.texi for this additional use of
> > the attribute. Sorry I didn't
On Wed, 2023-09-06 at 18:06 +0800, Yang Yujie wrote:
> When multilib is enabled, the c++ header directory of the default multilib
> variant needs to be linked to the toplevel since g++ does not search the
> toplevel in this case.
>
> libstdc++-v3/ChangeLog:
>
> * configure.host: Register
In order to better test the function of the vector instruction, the 128 and 256
bit test cases are further split according to the function of the instruction.
Xiaolong Chen (4):
LoongArch: Add tests of -mstrict-align option.
LoongArch: Add testsuite framework for Loongson SX/ASX.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/strict-align.c: New test.
---
gcc/testsuite/gcc.target/loongarch/strict-align.c | 13 +
1 file changed, 13 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
diff --git
This patch series provides support for the OpenMP 5.0+ array-shaping
operator and for strided/rectangular updates for 'target update'
directives. Each of C, C++ and Fortran is supported (using existing
base language syntax for the last).
This series applies on top of the "infrastructure" support
This patch works around behaviour of the 2D and 3D memcpy operations in
the CUDA driver runtime. Particularly in Fortran, the "base pointer"
of an array (used for either source or destination of a host/device copy)
may lie outside of data that is actually stored on the device. The fix
is to make
This patch enables use of 'declare mapper' for 'target update' directives,
for each of C, C++ and Fortran.
There are some implementation choices here and some
"read-between-the-lines" consequences regarding this functionality,
as follows:
* It is possible to invoke a mapper which contains
Committed as "obvious" to master.
--Philipp.
On Wed, 6 Sept 2023 at 12:04, Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> The test was introduced recently and tests a RV64-only feature.
> However, when testing an RV32 compiler, the test gets executed as
On Tue, Sep 5, 2023 at 9:24 PM Takayuki 'January June' Suwa
wrote:
> On 2023/09/06 8:01, Max Filippov wrote:
> > On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
> > wrote:
> >> ;; after (prereq. TARGET_MINMAX)
> >> test0:
> >> movi.n a9, 1
> >> minua2,
Hello folks,
Here's v3 of the top part of the security policy. Hopefully this
addresses all concerns raised so far.
Thanks,
Sid
What is a GCC security bug?
===
A security bug is one that threatens the security of a system or
network, or might compromise the
Okay, I'll take a look at it right away. Thanks reporting.
On 2023/9/6 16:17, Kito Cheng via Gcc-patches wrote:
Got failed on the trunk, could you take a look?
=== gcc: Unexpected fails for rv32imafdc ilp32d medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
This patch fix incorrect mode tieable between DI and V2SI which cause ICE
in RA.
PR target/111296
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr111296.C: New test.
---
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test.
---
.../loongarch/vector/lsx/lsx-builtin.c| 1461 +
1 file changed, 1461 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
diff --git
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/loongarch-vector.exp: New test.
* gcc.target/loongarch/vector/simd_correctness_check.h: New test.
---
.../loongarch/vector/loongarch-vector.exp | 42 +++
.../loongarch/vector/simd_correctness_check.h | 39
On Wed, 2023-09-06 at 18:43 +0800, Xiaolong Chen wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.target/loongarch/strict-align.c: New test.
A question: is there really a CPU model with LSX/LASX but without
unaligned access support? If not I think we'd just reject -mstrict-
align -mlsx.
Hi Richard,
I did some testing with the attached v2 that does not restrict to UNARY
anymore. As feared ;) there is some more fallout that I'm detailing below.
On Power there is one guality fail (pr43051-1.c) that I would take
the liberty of ignoring for now.
On x86 there are four fails:
-
On Wed, Sep 6, 2023 at 9:47 AM Fei Gao wrote:
>
> On 2023-09-05 20:02 Kito Cheng wrote:
> >
> >> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct
> >> riscv_frame_info *frame)
> >> {
> >>if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed
> >>||
Pushed to trunk with few testcase modifications, e.g. adding { target
{ riscv_vector } } to dg-run and adding -march / -mabi for compile
tests.
On Tue, Sep 5, 2023 at 4:18 PM Kito Cheng wrote:
>
> Thanks for fixing the issue! I guess I could find time tonight to do
> the final round review and
Following the similar support for C++, here is the C implementation for
the OpenMP 5.0 array-shaping operator, and for strided and rectangular
updates for "target update".
Much of the implementation is shared with the C++ support added by the
previous patch. Some details of parsing necessarily
When multilib is enabled, the c++ header directory of the default multilib
variant needs to be linked to the toplevel since g++ does not search the
toplevel in this case.
libstdc++-v3/ChangeLog:
* configure.host: Register t-loongarch in tmake_file.
*
If mask is a constant with value ((1 << N) - 1) << M we can perform this
optimization.
gcc/ChangeLog:
PR target/111252
* config/loongarch/loongarch-protos.h
(loongarch_pre_reload_split): Declare new function.
(loongarch_use_bstrins_for_ior_with_mask): Likewise.
On Wed, 2023-09-06 at 18:45 +0800, Xiaolong Chen wrote:
> + *((int*)& __m128_op0[3]) = 0x004200a0;
> + *((int*)& __m128_op0[2]) = 0x;
> + *((int*)& __m128_op0[1]) = 0x004200a0;
> + *((int*)& __m128_op0[0]) = 0x0021;
These are aliasing rule violation and they will suddenly blow up
Yang Yujie writes:
> gcc/ChangeLog:
>
> * config.gcc: remove non-POSIX syntax "<<<".
> ---
Thanks, I was just about to report this.
> gcc/config.gcc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index
Got failed on the trunk, could you take a look?
=== gcc: Unexpected fails for rv32imafdc ilp32d medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL:
No functional changes but restructure and expose use_shrink_wrapping_separate
to the TARGETs.
gcc/ChangeLog:
* shrink-wrap.cc (try_shrink_wrapping_separate):call
use_shrink_wrapping_separate.
(use_shrink_wrapping_separate): wrap the condition
check in
Enable muti push and pop for Zcmp when shrink-wrap-separate is ineffective.
Fei Gao (2):
allow targets to check shrink-wrap-separate enabled or not
[V2][RISC-V] enable muti push and pop for Zcmp when shrink-wrap-separate is
ineffective
gcc/config/riscv/riscv.cc | 21
So that zcmp can be enabled in -Os where
shrink-wrap-separate is not effective.
To force enabling zcmp multi push/pop in speed perfered case,
fno-shrink-wrap-separate has to be explictly given.
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_avoid_shrink_wrapping_separate): wrap
Hi Robin,
+# Return 1 if the we can build a vector example with proper -march flags
+# and the current target can execute it, 0 otherwise. Cache the result.
+
+proc check_effective_target_riscv_vector_hw { } {
+
+return [check_runtime riscv_vector_hw32 {
+int main (void)
+{
LGTM
Edwin Lu 於 2023年9月7日 週四 01:53 寫道：
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu
> ---
>
LGTM
Edwin Lu 於 2023年9月7日 週四 01:52 寫道：
> This patch adds types to riscv instructions that were added or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Update types
>
> Signed-off-by:
On 2023/09/07 2:50, Edwin Lu wrote:
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu
> ---
>
在 2023/9/6 下午7:10, Xi Ruoyao 写道:
On Wed, 2023-09-06 at 18:43 +0800, Xiaolong Chen wrote:
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/strict-align.c: New test.
A question: is there really a CPU model with LSX/LASX but without
unaligned access support? If not I think we'd just
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
generation" and add the new explanation in the options.texi.
gcc/ChangeLog:
* config/riscv/riscv-opts.h (MASK_ZICSR):
(MASK_ZIFENCEI): Delete;
(MASK_ZIHINTNTL):Ditto;
在 2023-09-06三的 18:56 +0800，Xi Ruoyao写道：
> On Wed, 2023-09-06 at 18:45 +0800, Xiaolong Chen wrote:
> > + *((int*)& __m128_op0[3]) = 0x004200a0;
> > + *((int*)& __m128_op0[2]) = 0x;
> > + *((int*)& __m128_op0[1]) = 0x004200a0;
> > + *((int*)& __m128_op0[0]) = 0x0021;
>
> These are
Tested x86_64-linux and x86_64-elf. Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
* acinclude.m4 (GLIBCXX_ENABLE_BACKTRACE): Disable by default
for freestanding.
* configure: Regenerate.
---
libstdc++-v3/acinclude.m4 | 2 +-
libstdc++-v3/configure| 2 +-
2 files
This patch to godump.cc adds support for BITINT_TYPE. Bootstrapped
and ran godump and Go tests on x86_64-pc-linux-gnu. Committed to
mainline.
Ian
gcc/
PR go/111310
* godump.cc (go_format_type): Handle BITINT_TYPE.
gcc/testsuite/
PR go/111310
*
csr is kind of confusing, I would suggest something like `pushpop` and
`mvpair`.
Edwin Lu 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to the untyped zc instructions. Creates a new
> type "csr" for these instructions for now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "csr"
From: Tsukasa OI
For bit manipulation operations, inputs and the manipulated output are
better to be unsigned like other target-independent builtins like
__builtin_bswap32 and __builtin_popcount.
Although this is not completely compatible as before (as the type changes),
most code will run
From: Tsukasa OI
This commit replaces the type of the builtin used in the testsuite.
Even without this commit, it won't cause any test failures but changed so
that no confusion occurs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbc32.c: Make signed type to unsigned.
*
Hello,
Many RISC-V builtins operate in signed integer types but in many cases,
they are better to be unsigned.
There are a few reasons to do that:
1. Being more natural
For bit manipulation operations, the direct input and the result should
have an unsigned type.
e.g.
On Mon, 28 Aug 2023, Jason Merrill wrote:
> On 8/24/23 09:31, Patrick Palka wrote:
> > On Wed, 23 Aug 2023, Jason Merrill wrote:
> >
> > > On 8/21/23 21:51, Patrick Palka wrote:
> > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look like
> > > > a reasonable approach? I
LGTM
Edwin Lu 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to vector instructions that were added after or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Update types
>
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.
gcc/ChangeLog:
* config/i386/sse.md
(_vpermt2var3): New define_insn.
(VHFBF_AVX512VL): New mode iterator.
(VI2HFBF_AVX512VL): New mode iterator.
---
gcc/config/i386/sse.md | 32
在 2023/9/6 下午6:58, Xi Ruoyao 写道:
Forgot to mention: I've bootstrapped and regtested this patch on
loongarch64-linux-gnu (with PR110939 patch applied to unbreak the
bootstrapping). Ok for trunk?
LGTM!
Thanks!
On Wed, 2023-09-06 at 18:46 +0800, Xi Ruoyao wrote:
If mask is a constant
LGTM
Juzhe-Zhong 於 2023年9月7日 週四 11:36 寫道：
> This patch removes the incorrect earliest poset vsetvl optimization,
> such bug was found in vect-double-reduc-5.c which is runtime(execution
> fail) and also in PR111313.
>
> For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl
>
On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote:
>
> On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++
> wrote:
> >
> > > Date: Fri, 1 Sep 2023 12:16:40 +0100
> > > Reply-To: Jonathan Wakely
> > >
> > > On Wed, 23 Aug 2023 at 17:03, Jonathan Wakely via Libstdc++
> > > wrote:
>
Hi,
I will need to notify you that x_riscv_xventana_subext,
MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
want to rewrite those definitions like the rest). Also, be careful not
to remove TARGET_ZICOND_LIKE.
Thanks,
Tsukasa
On 2023/09/06 11:02, Feng Wang wrote:
> This
Hi,
As discussed in PR111303:
For pattern "(X + C) / N": "div (plus@3 @0 INTEGER_CST@1) INTEGER_CST@2)",
Even if "X" has value-range and "X + C" does not overflow, "@3" may still
be undefined. Like below example:
_3 = _2 + -5;
if (0 != 0)
goto ; [34.00%]
else
goto ; [66.00%]
;; succ:
On Mon, 28 Aug 2023, Jason Merrill wrote:
> On 8/24/23 09:31, Patrick Palka wrote:
> > On Wed, 23 Aug 2023, Jason Merrill wrote:
> >
> > > On 8/21/23 21:51, Patrick Palka wrote:
> > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look like
> > > > a reasonable approach? I
On Thu, 7 Sept 2023 at 00:09, Hans-Peter Nilsson wrote:
>
> > From: Jonathan Wakely
> > Date: Wed, 6 Sep 2023 23:30:08 +0100
>
> > On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote:
> > >
> > > On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++
> > > wrote:
> > > >
> > > > >
On Thu, 7 Sept 2023 at 00:10, Jonathan Wakely wrote:
>
> On Thu, 7 Sept 2023 at 00:09, Hans-Peter Nilsson wrote:
> >
> > > From: Jonathan Wakely
> > > Date: Wed, 6 Sep 2023 23:30:08 +0100
> >
> > > On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely
> > > wrote:
> > > >
> > > > On Mon, 4 Sept 2023
> From: Jonathan Wakely
> Date: Wed, 6 Sep 2023 23:30:08 +0100
> On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote:
> >
> > On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++
> > wrote:
> > >
> > > > Date: Fri, 1 Sep 2023 12:16:40 +0100
> > > > Reply-To: Jonathan Wakely
> > > >
On Wed, Sep 06, 2023 at 06:38:25PM +0800, Xi Ruoyao wrote:
> On Wed, 2023-09-06 at 18:06 +0800, Yang Yujie wrote:
> > When multilib is enabled, the c++ header directory of the default multilib
> > variant needs to be linked to the toplevel since g++ does not search the
> > toplevel in this case.
>
This patch removes the incorrect earliest poset vsetvl optimization,
such bug was found in vect-double-reduc-5.c which is runtime(execution fail)
and also in PR111313.
For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl (see
vector.md) to
occupy a scalar register which is
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk? This cache apparently has a 98% hit rate for TYPE_HAS_CONVERSION
types on some test files.
-- >8 --
gcc/cp/ChangeLog:
* config-lang.in (gtfiles): Add search.cc.
* search.cc
> Date: Thu, 7 Sep 2023 00:11:04 +0100
> From: Jonathan Wakely via Gcc-patches
> On Thu, 7 Sept 2023 at 00:10, Jonathan Wakely wrote:
> > I don't think there's a bug. $is_hosted is true for
> > --enable-hosted-libstdcxx which is on by default.
>
> And IIRC __STDC_HOSTED__ is defined unless you
Thanks reminder, I should rebase again.
--
Feng Wang
>Hi,
>
>I will need to notify you that x_riscv_xventana_subext,
>MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
>want to rewrite those definitions like the rest). Also, be careful not
>to remove
Hi Robin,
Yes, you're right, this should not be necessary. This is more of a
test for the execution environment than the compiler. I think Juzhe
removed it already in his patch that enables the vector test suite.
In the future we would use the checks that Joern added, not sure if
they are
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Thursday, September 7, 2023 11:39 AM
To: Juzhe-Zhong
Cc: GCC Patches ; Kito Cheng
Subject: Re: [PATCH] RISC-V: Remove incorrect earliest vsetvl post
optimization[PR111313]
On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote:
> From: David Malcolm
This is probably something for the gcc-rust maintainers to review
(rather than me self-reviewing with my "diagnostics maintainer" hat
on).
Doesn't have a ChangeLog entry, FWIW.
Doesn't have a signed-off-by, so here's
On 9/6/23 16:12, David Malcolm wrote:
On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote:
From: David Malcolm
I guess I can review this patch :)
Needs a ChangeLog entry, so here's one:
gcc/ChangeLog
* diagnostic-core.h (error_meta): New decl.
* diagnostic.cc
Hi!
Thanks for the patch reviews (and to Richi and Uros as well) and everyone
who participated in discussions.
Here is the updated version of the C _BitInt support [PR102989] patch
I've committed to trunk in addition to the rest of the series (except the
_BitInt a ? ~b : b match.pd fix patch,
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