Re: [PATCH 04/12] mode-switching: Fix the mode passed to the emit hook

On 11/5/23 11:47, Richard Sandiford wrote: optimize_mode_switching passes an entity's current mode (if known) to the emit hook. However, the mode that it passed ignored the effect of the after hook. Instead, the mode for the first emit call in a block was taken from the incoming mode,

[PATCH] RISC-V regression test: Fix FAIL of bb-slp-39.c

Like s390, add riscv to fix the fail. gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-39.c: Add RISCV. --- gcc/testsuite/gcc.dg/vect/bb-slp-39.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-39.c

[PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV#

RVV didn't explictly enable DIV_POW2 optab but we cen vectorize it. We should check pattern recognition instead of explicit pattern check. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-sdiv-pow2-1.c: Fix dump check. --- gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c | 2 +- 1 file changed,

Re: [PATCH] Reduce false positives for -Wnonnull for VLA parameters [PR98541]

On 11/6/23 20:58, Hans-Peter Nilsson wrote: From: Martin Uecker Date: Tue, 31 Oct 2023 20:05:09 +0100 Reduce false positives for -Wnonnull for VLA parameters [PR98541] This patch limits the warning about NULL arguments to VLA parameters declared [static n].

Re: [PATCH][_Hashtable] Add missing destructor call

On Mon, 6 Nov 2023 at 21:39, François Dumont wrote: > > Noticed looking for other occasion to replace __try/__catch with RAII > helper. > > libstdc++: [_Hashtable] Add missing node destructor call > > libstdc++-v3/ChangeLog: > > * include/bits/hashtable_policy.h >

Re: [PATCH] RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization

Ping this simple optimization. Ok for trunk ? juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-11-06 11:34 To: gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong Subject: [PATCH] RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization I notice we

Re: [PATCH 06/12] mode-switching: Tweak entry/exit handling

On 11/5/23 11:48, Richard Sandiford wrote: An entity isn't transparent in a block that requires a specific mode. optimize_mode_switching took that into account for normal insns, but didn't for the exit block. Later patches misbehaved because of this. In contrast, an entity was correctly

RE: [PATCH] test: Fix FAIL of bb-slp-cond-1.c for RVV

Committed, thanks Jeff. Pan -Original Message- From: Jeff Law Sent: Tuesday, November 7, 2023 11:25 AM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: rguent...@suse.de Subject: Re: [PATCH] test: Fix FAIL of bb-slp-cond-1.c for RVV On 11/6/23 16:03, Juzhe-Zhong wrote: > This patch

Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV

On 11/6/23 20:30, juzhe.zh...@rivai.ai wrote: >> So will this create a FAIL if someone runs the testsuite with the autovec preference set to scalable? No, it won't. Since it is always -fno-vect-cost-model. When a scalable vector doesn't have 256bit vector,  it always XFAIL, for example,

[PATCH v4] c++: implement P2564, consteval needs to propagate up [PR107687]

On Fri, Nov 03, 2023 at 01:51:07PM -0400, Jason Merrill wrote: > On 11/2/23 11:28, Marek Polacek wrote: > > On Sat, Oct 14, 2023 at 12:56:11AM -0400, Jason Merrill wrote: > > > On 10/10/23 13:20, Marek Polacek wrote: > > > > On Tue, Aug 29, 2023 at 03:26:46PM -0400, Jason Merrill wrote: > > > > >

[PATCH] test: Fix XPASS of bb-slp-43.c for RVV

RVV is variable length vector but also has 256 bit VLS mode vector. This test is vectorized as: f: vsetivlizero,8,e32,m2,ta,ma vle32.v v2,0(a0) vmv.v.i v4,1 vle16.v v1,0(a1) vmseq.vvv0,v2,v4 vsetvli zero,zero,e16,m1,ta,ma

[PATCH] test: Fix XPASS of bb-slp-43.c for RVV

RVV is variable length vector but also has 256 bit VLS mode vector. This test is vectorized as: f: vsetivlizero,8,e32,m2,ta,ma vle32.v v2,0(a0) vmv.v.i v4,1 vle16.v v1,0(a1) vmseq.vvv0,v2,v4 vsetvli zero,zero,e16,m1,ta,ma

Re: [PATCH 01/12] mode-switching: Tweak the macro/hook documentation

On 11/5/23 11:46, Richard Sandiford wrote: I found the documentation for the mode-switching macros/hooks a bit hard to follow at first. This patch tries to add the information that I think would have made it easier to understand. Of course, documentation preferences are personal, and so I

Re: [PATCH 07/12] mode-switching: Allow targets to set the mode for EH handlers

On 11/5/23 11:48, Richard Sandiford wrote: The mode-switching pass already had hooks to say what mode an entity is in on entry to a function and what mode it must be in on return. For SME, we also want to say what mode an entity is guaranteed to be in on entry to an exception handler. gcc/

Re: [PATCH 11/12] mode-switching: Add a target-configurable confluence operator

On 11/5/23 11:50, Richard Sandiford wrote: The mode-switching pass assumed that all of an entity's modes were mutually exclusive. However, the upcoming SME changes have an entity with some overlapping modes, so that there is sometimes a "superunion" mode that contains two given modes. We can

[PATCH] riscv: thead: Add support for the XTheadInt ISA extension

The XTheadInt ISA extension provides acceleration interruption instructions as defined in T-Head-specific: * th.ipush * th.ipop gcc/ChangeLog: * config/riscv/riscv-protos.h (th_int_get_mask): New prototype. (th_int_get_save_adjustment): Likewise.

Re: [PATCH] RISC-V: VECT: Remember to assert any_known_not_updated_vssa

On 11/6/23 06:18, Kito Cheng wrote: Oh, you're right! I should have checked the master branch first... and I was even wondering why it wasn't marked as such. Should perhaps cherry pick this for gcc-13-with-riscv-opts? gcc-13-with-riscv-opts mostly maintained by Ventana folks, so maybe ask

Re: RISC-V patchworks call tomorrow ?

On 11/6/23 18:19, Vineet Gupta wrote: Do we have call tomorrow, given some folks are traveling for RV Summit ? I'll be in the air, so "no" from me. jeff

Re: [PATCH] test: Fix FAIL of bb-slp-cond-1.c for RVV

On 11/6/23 16:03, Juzhe-Zhong wrote: This patch fixes: FAIL: gcc.dg/vect/bb-slp-cond-1.c -flto -ffat-lto-objects scan-tree-dump-times vect "loop vectorized" 1 FAIL: gcc.dg/vect/bb-slp-cond-1.c scan-tree-dump-times vect "loop vectorized" 1 For RVV, "loop vectorized" appears 2 times instead

Re: [PATCH] Reduce false positives for -Wnonnull for VLA parameters [PR98541]

> From: Martin Uecker > Date: Tue, 31 Oct 2023 20:05:09 +0100 > Reduce false positives for -Wnonnull for VLA parameters [PR98541] > > This patch limits the warning about NULL arguments to VLA > parameters declared [static n]. > > PR c/98541 > > gcc/ >

[PATCH/RFC] libdiagnostics: a shared library for emitting diagnostics

It's fairly easy for tools to implement simple diagnostics via fprintf of FILE:LINE:COLUMN: error: message to stderr, but as diagnostics get more featureful, using a shared library makes sense. This patch kit extends GCC to add a new "libdiagnostics" shared library on the host, built around

[PATCH 1/2] libdiagnostics: header and examples

Here's a work-in-progress patch for GCC that adds a libdiagnostics.h header describing the public interface, along with various testcases that show usage examples for the API. Various aspects of this need work; posting now for early feedback on overall direction. How does the interface look?

Re: [PATCH-3v2, rs6000] Enable 16-byte by pieces move [PR111449]

Hi, on 2023/11/6 17:47, HAO CHEN GUI wrote: > Hi, > The patch 2 enables 16-byte by pieces move on rs6000. This patch fixes > the regression cases caused by previous patch. For sra-17/18, the long > array with 4 elements can be loaded by one 16-byte by pieces move on 32-bit > platform. So the

Re: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV

>> So will this create a FAIL if someone runs the testsuite with the >> autovec preference set to scalable? No, it won't. Since it is always -fno-vect-cost-model. When a scalable vector doesn't have 256bit vector, it always XFAIL, for example, ARM SVE. >> Or are the fallbacks to VLS still >>

[PATCH v1] LoongArch: Add instructions for the use of vector functions.

gcc/ChangeLog: * doc/extend.texi:Add instructions for SX and ASX vector functions to GCC documentation, including definitions and usage of function type aliases, constant types, and vector function prototypes. --- gcc/doc/extend.texi | 1673

Re: [PATCH] test: Fix FAIL of SAD tests for RVV

On 11/6/23 20:36, Juzhe-Zhong wrote: RVV didn't explicitly enable SAD optab but we can vectorize it since loop vectorizer is able to recognize SAD pattern for RVV during analysis. Current scan check of explicit SAD pattern looks odd, it should be more reasonable to check recognition of SAD

Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV#

On 11/6/23 20:50, Juzhe-Zhong wrote: RVV didn't explictly enable DIV_POW2 optab but we cen vectorize it. We should check pattern recognition instead of explicit pattern check. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-sdiv-pow2-1.c: Fix dump check. Similar to the sad test -- OK

[PATCH 2/2] libdiagnostics: work-in-progress implementation

Here's a work-in-progress patch for GCC that adds the implementation of libdiagnostics. Various aspects of this need work; posting now for early feedback on overall direction. For example, the testsuite doesn't yet check the output from the test client programs (and I'm not quite sure of the

[PATCH] binutils: experimental use of libdiagnostics in gas

Here's a patch for gas in binutils that makes it use libdiagnostics (with some nasty hardcoded paths to specific places on my hard drive to make it easier to develop the API). For now this hardcodes adding two sinks: a text sink on stderr, and also a SARIF output to stderr (which happens after

Re: [PATCH 05/12] mode-switching: Simplify recording of transparency

On 11/5/23 11:47, Richard Sandiford wrote: For a given block, an entity is either transparent for all modes or for none. Each update to the transparency set therefore used a loop like: for (i = 0; i < no_mode; i++) clear_mode_bit (transp[bb->index], j, i);

RISC-V patchworks call tomorrow ?

Do we have call tomorrow, given some folks are traveling for RV Summit ? Thx, -Vineet

Re: [PATCH] RISC-V: Add ABI requirement for XTheadFMemIdx tests

LGTM, and maybe change stdint.h to stdint-gcc.h in xtheadmemidx-helpers.h? that could make it more portable on multi-lib testing. On Tue, Nov 7, 2023 at 3:44 AM Christoph Muellner wrote: > > From: Christoph Müllner > > The XTheadFMemIdx tests set the required ABI for RV32, but not > for RV64,

[PATCH] i386: Fix isa attribute for TI/TF andnot mode

Hi all, This patch aims fo fix the wrong isa attribute which caused regression on PR111907. Regtested on x86_64-pc-linux-gnu. Ok for trunk? Thx, Haochen gcc/ChangeLog: PR target/111907 * config/i386/i386.md (avx_noavx512vl): Add missing definition. * config/i386/sse.md

Re: [PATCH] rs6000, testcase: Add require-effective-target has_arch_ppc64 to pr106550_1.c

Hi, on 2023/11/6 15:20, Jiufu Guo wrote: > Hi, > > With latest trunk, case pr106550_1.c can run with failure on ppc under -m32. > While, the case is testing 64bit constant building. So, "has_arch_ppc64" > is required. Please also mention that it failed with ICE initially due to PR111971, now

Re: [PATCH] i386: Fix isa attribute for TI/TF andnot mode

On Tue, Nov 7, 2023 at 10:27 AM Haochen Jiang wrote: > > Hi all, > > This patch aims fo fix the wrong isa attribute which caused regression > on PR111907. > > Regtested on x86_64-pc-linux-gnu. Ok for trunk? > > Thx, > Haochen > > gcc/ChangeLog: > > PR target/111907 > *

Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV

On 11/6/23 15:35, Juzhe-Zhong wrote: RVV is variable length vector but also has 256 bit VLS mode vector. This test is vectorized as: f: vsetivlizero,8,e32,m2,ta,ma vle32.v v2,0(a0) vmv.v.i v4,1 vle16.v v1,0(a1) vmseq.vvv0,v2,v4

Re: [PATCH-2, rs6000] Enable vector mode for by pieces equality compare [PR111449]

Hi Kewen, Thanks for your review comments. Just one question on following comment. 在 2023/11/7 10:40, Kewen.Lin 写道: > Nit: has_arch_pwr8 would make it un-tested on Power7 default env, I'd prefer > to remove this "has_arch_pwr8" and append "-mdejagnu-cpu=power8" to > dg-options. My original

[PATCH] test: Fix FAIL of SAD tests for RVV

RVV didn't explicitly enable SAD optab but we can vectorize it since loop vectorizer is able to recognize SAD pattern for RVV during analysis. Current scan check of explicit SAD pattern looks odd, it should be more reasonable to check recognition of SAD pattern during Loop vectorize analysis.

[PATCH v1] LoongArch: Add modifiers for lsx and lasx.

gcc/ChangeLog: * doc/extend.texi:Added modifiers for LoongArch architecture lsx and lasx in the manual. --- gcc/doc/extend.texi | 27 +++ 1 file changed, 27 insertions(+) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index

[PATCH] test: Fix FAIL of bb-slp-cond-1.c for RVV

This patch fixes: FAIL: gcc.dg/vect/bb-slp-cond-1.c -flto -ffat-lto-objects scan-tree-dump-times vect "loop vectorized" 1 FAIL: gcc.dg/vect/bb-slp-cond-1.c scan-tree-dump-times vect "loop vectorized" 1 For RVV, "loop vectorized" appears 2 times instead of 1. Because: optimized: loop vectorized

Re: [PATCH][_Hashtable] Add missing destructor call

On Mon, 6 Nov 2023 at 21:39, François Dumont wrote: > > Noticed looking for other occasion to replace __try/__catch with RAII > helper. > > libstdc++: [_Hashtable] Add missing node destructor call > > libstdc++-v3/ChangeLog: > > * include/bits/hashtable_policy.h >

RFC (V2) the proposal to resolve the missing dependency issue for counted_by attribute

Hi, Attached is the 2nd version of the proposal based on all the discussion so far. Let me know if you have more comment and suggestion. Thanks a lot for all the help. Qing === Represent the missing dependence for the "counted_by" attribute and its

Re: [PATCH 02/12] mode-switching: Add note problem

On 11/5/23 11:46, Richard Sandiford wrote: optimize_mode_switching uses REG_DEAD notes to track register liveness, but it failed to tell DF to calculate up-to-date notes. Noticed by inspection. I don't have a testcase that fails because of this. gcc/ * mode-switching.cc

Re: [PATCH 03/12] mode-switching: Avoid quadractic list operation

On 11/5/23 11:47, Richard Sandiford wrote: add_seginfo chained insn information to the end of a list by starting at the head of the list. This patch avoids the quadraticness by keeping track of the tail pointer. gcc/ * mode-switching.cc (add_seginfo): Replace head pointer with

Re: [PATCH 08/12] mode-switching: Pass set of live registers to the needed hook

On 11/5/23 11:48, Richard Sandiford wrote: The emit hook already takes the set of live hard registers as input. This patch passes it to the needed hook too. SME uses this to optimise the mode choice based on whether state is live or dead. The main caller already had access to the required

Re: [PATCH 09/12] mode-switching: Pass the set of live registers to the after hook

On 11/5/23 11:49, Richard Sandiford wrote: This patch passes the set of live hard registers to the after hook, like the previous one did for the needed hook. gcc/ * target.def (mode_switching.after): Add a regs_live parameter. * doc/tm.texi: Regenerate. *

Re: [PATCH] RISC-V regression test: Fix FAIL of bb-slp-39.c

LGTM On Tue, Nov 7, 2023 at 10:32 AM Juzhe-Zhong wrote: > > Like s390, add riscv to fix the fail. > > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/bb-slp-39.c: Add RISCV. > > --- > gcc/testsuite/gcc.dg/vect/bb-slp-39.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff

RE: [PATCH] RISC-V regression test: Fix FAIL of bb-slp-39.c

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Tuesday, November 7, 2023 10:47 AM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH] RISC-V regression test: Fix FAIL of bb-slp-39.c

Re: [PATCH v4 1/2] c++: Initial support for P0847R7 (Deducing this) [PR102609]

I noticed I made a bit of a mistake in grokdeclarator:find_xobj_parm, this code: ``` if (!parm_list || parm_list == void_list_node) return false; if (TREE_PURPOSE (parm_list) != this_identifier) return false; ``` Can be simplified to this code: ``` if (!parm_list || TREE_PURPOSE (parm_list)

Re: [PATCH-2, rs6000] Enable vector mode for by pieces equality compare [PR111449]

Hi, on 2023/11/7 11:24, HAO CHEN GUI wrote: > Hi Kewen, > >Thanks for your review comments. Just one question on following > comment. > > 在 2023/11/7 10:40, Kewen.Lin 写道: >> Nit: has_arch_pwr8 would make it un-tested on Power7 default env, I'd prefer >> to remove this "has_arch_pwr8" and

c: Refer more consistently to C23 not C2X

Continuing the move to refer to C23 in place of C2X throughout the source tree, update documentation, diagnostics, comments, variable and function names, etc., to use the C23 name. Testsuite updates are left for a future patch, except for testcases that test diagnostics that previously mentioned

Re: [PATCH-2, rs6000] Enable vector mode for by pieces equality compare [PR111449]

Hi Haochen, on 2023/11/6 10:36, HAO CHEN GUI wrote: > Hi, > This patch enables vector mode for by pieces equality compare. It > adds a new expand pattern - cbrnachv16qi4 and set MOVE_MAX_PIECES > and COMPARE_MAX_PIECES to 16 bytes when P8 vector enabled. The compare > relies both move and

Re: [PATCH 10/12] mode-switching: Use 1-based edge aux fields

On 11/5/23 11:49, Richard Sandiford wrote: The pass used the edge aux field to record which mode change should happen on the edge, with -1 meaning "none". It's more convenient for later patches to leave aux zero for "none", and use numbers based at 1 to record a change. gcc/ *

Re: [PATCH V2] RISC-V: Early expand DImode vec_duplicate in RV32 system

On 11/6/23 07:12, Juzhe-Zhong wrote: An ICE was discovered in recent rounding autovec support: config/riscv/riscv-v.cc:4314 65 | } | ^ 0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**, rtx_def*, bool)

[V2 PATCH] Handle bitop with INTEGER_CST in analyze_and_compute_bitop_with_inv_effect.

analyze_and_compute_bitop_with_inv_effect assumes the first operand is loop invariant which is not the case when it's INTEGER_CST. Bootstrapped and regtseted on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR tree-optimization/105735 PR tree-optimization/111972

Re: [PATCH] binutils: experimental use of libdiagnostics in gas

Thank you very much for this proof-of-concept use! Inspecting it raises the following questions to me, both for a possible binutils implementation and for the library use in general: * How should the application set the relevant context (often lines are shown before/after)? * Should it be

Re: [PATCH] Reduce false positives for -Wnonnull for VLA parameters [PR98541]

Am Montag, dem 06.11.2023 um 21:01 -0700 schrieb Jeff Law: > > On 11/6/23 20:58, Hans-Peter Nilsson wrote: > > > From: Martin Uecker > > > Date: Tue, 31 Oct 2023 20:05:09 +0100 > > > > > Reduce false positives for -Wnonnull for VLA parameters [PR98541] > > > > > > This patch

Re: [PATCH] RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization

LGTM. Regards Robin

Re: Re: [PATCH] test: Fix FAIL of SAD tests for RVV

Thanks Jeff. Just finish bootstrap +regression passed. Committed. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-11-07 11:52 To: Juzhe-Zhong; gcc-patches CC: rguenther Subject: Re: [PATCH] test: Fix FAIL of SAD tests for RVV On 11/6/23 20:36, Juzhe-Zhong wrote: > RVV didn't explicitly

Re: [PATCH 2/2] libdiagnostics: work-in-progress implementation

Thank you for our work and providing this patch. GCC related questions: Is it planned to change GCC diagnostics to use libdiagnostic itself? Is it planned to "directly" add features or would the result for GCC be identical (apart from build changes)? So far it looks like it wouldn't be

Re: [PATCH] RISC-V: Fixed failed rvv combine testcases

LGTM. Thanks for fixing it. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-11-07 15:49 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH] RISC-V: Fixed failed rvv combine testcases Hi, This patch fixed the fellowing failed testcases on

Re: [PATCH v1] RISC-V: Support FP ceil to i/l/ll diff size autovec

OK juzhe.zh...@rivai.ai From: pan2.li Date: 2023-11-07 14:41 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Support FP ceil to i/l/ll diff size autovec From: Pan Li This patch would like to support the FP below API auto vectorization with

RE: [PATCH] RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization

Committed, thanks Robin. Pan -Original Message- From: Robin Dapp Sent: Tuesday, November 7, 2023 2:59 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com; jeffreya...@gmail.com Subject: Re: [PATCH] RISC-V: Enhance AVL

Re: RISC-V patchworks call tomorrow ?

On Mon, 06 Nov 2023 18:47:24 PST (-0800), jeffreya...@gmail.com wrote: On 11/6/23 18:19, Vineet Gupta wrote: Do we have call tomorrow, given some folks are traveling for RV Summit ? I'll be in the air, so "no" from me. I'll be on the ground, but not sure that counts for much. IIRC Kito

Re: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV

Thanks Jeff. Just finish bootstrap +regression passed. Committed. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-11-07 11:49 To: juzhe.zh...@rivai.ai; gcc-patches CC: rguenther Subject: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV On 11/6/23 20:30, juzhe.zh...@rivai.ai wrote: > >>

Re: Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV#

Thanks Jeff. Just finish bootstrap +regression passed. Committed. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-11-07 11:53 To: Juzhe-Zhong; gcc-patches CC: rguenther Subject: Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV# On

[PATCH] vect/ifcvt: Add vec_cond fallback and check for vector versioning.

Hi, this restricts tree-ifcvt to only create COND_OPs when we versioned the loop for vectorization. Apart from that it re-creates a VEC_COND_EXPR in vect_expand_fold_left if we emitted a COND_OP. I'm still missing the "bail out" part for vect_expand_fold_left, though? Bootstrap, testsuites are

[PATCH] RISC-V: Fixed failed rvv combine testcases

Hi, This patch fixed the fellowing failed testcases on the trunk: FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c scan-assembler-times \\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 2 ... FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c scan-assembler-times

[PATCH v1] RISC-V: Support FP ceil to i/l/ll diff size autovec

From: Pan Li This patch would like to support the FP below API auto vectorization with different type size +-+---+--+ | API | RV64 | RV32 | +-+---+--+ | iceil | DF => SI | DF => SI | | iceilf | - | -| | lceil | -

Re: c: Refer more consistently to C23 not C2X

On Tue, Nov 07, 2023 at 12:20:43AM +, Joseph Myers wrote: > Continuing the move to refer to C23 in place of C2X throughout the > source tree, update documentation, diagnostics, comments, variable and > function names, etc., to use the C23 name. > > Testsuite updates are left for a future

[PATCH] test: Fix FAIL of pr97428.c for RVV

This test shows vectorizing stmts using SLP 4 times instead of 2 for RVV. The reason is RVV has 512 bit vector. Here is comparison between RVV ans ARM SVE: https://godbolt.org/z/xc5KE5rPs But I notice AMDGCN also has 512 bit vector, seems this patch will cause FAIL in GCN ? Not sure whether GCN

Re: [PATCH] RISC-V: Fixed failed rvv combine testcases

Thanks, what I was slightly concerned about is that we now have the implicit assumption that the initial value is 0. I mean that's what the vectorizer does for reductions but theoretically, wouldn't we also combine other values into 0 now? Regards Robin

[PATCH] [i386] APX: Fix ICE due to movti postreload splitter [PR112394]

Hi, When APX EGPR enabled, the TImode move pattern *movti_internal allows move between gpr and sse reg using constraint pair ("r","Yd"). Then a post-reload splitter transform such move to vec_extractv2di, while under -msse4.1 -mno-avx EGPR is not allowed for its enabled alternative, which caused

Re: [PATCH] RISC-V: Fixed failed rvv combine testcases

Committed, thanks Juzhe. On 2023/11/7 15:51, juzhe.zh...@rivai.ai wrote: LGTM. Thanks for fixing it. juzhe.zh...@rivai.ai *From:* Lehua Ding *Date:* 2023-11-07 15:49 *To:*

Re: [PATCH v1] RISC-V: Adjust FP rint round tests for RV32

LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-11-06 16:33 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Adjust FP rint round tests for RV32 From: Pan Li The FP rint test cases for RV32 need some additional adjust for types and data.

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

On 03.11.23 20:53, Kwok Cheung Yeung wrote: On 17/10/2023 2:12 pm, Tobias Burnus wrote: C++11 (and C23) attribute do not seem to be properly handled: (Side remark: Since Saturday, the [[omp::]] attributes syntax is now also supported in C23.) [Quoted email text by Kwok: Lots of lines removed

[PATCH] tree-optimization/112369 - strip_float_extensions and vectors

The following fixes an error in strip_float_extensions when facing vector conversions. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/112369 * tree.cc (strip_float_extensions): Use element_precision. * gcc.dg/pr112369.c: New testcase.

[PATCH v1] RISC-V: Adjust FP rint round tests for RV32

From: Pan Li The FP rint test cases for RV32 need some additional adjust for types and data. This patch would like to fix this which is missed in FP rint support PATCH for RV32 only by mistake. Please note the math-llrintf-run-0.c will trigger one ICE in the vsetvl pass in RV32 only.

Re: [PATCH] Fix PR ada/111909 On Darwin, determine filesystem case sensitivity at runtime

> > So without changing fundamentally the model, you can't decide dynamically > > for the whole > > system. Making the choice based on the current directory is pretty random, > > since the current > > directory isn't well defined at program's start up and could be pretty much > > any

Re: [RFC] vect: disable multiple calls of poly simdclones

On 06/11/2023 07:52, Richard Biener wrote: On Fri, 3 Nov 2023, Andre Vieira (lists) wrote: Hi, The current codegen code to support VF's that are multiples of a simdclone simdlen rely on BIT_FIELD_REF to create multiple input vectors. This does not work for non-constant simdclones, so we

Re: [PATCH] libstdc++: Improve static assert messages for monadic operations

On Thu, 2 Nov 2023 at 14:55, Jonathan Wakely wrote: > > Any objections or suggestions for better wording? > > Tested x86_64-linux. Pushed to trunk. > > -- >8 -- > > The monadic operations for std::optional and std::expected make use of > internal helper traits __is_optional nad __is_expected,

Re: [PATCH 5/5] x86: yet more PR target/100711-like splitting

On 25.06.2023 08:41, Hongtao Liu wrote: > On Sun, Jun 25, 2023 at 2:35 PM Hongtao Liu wrote: >> >> On Sun, Jun 25, 2023 at 2:25 PM Jan Beulich wrote: >>> >>> On 25.06.2023 07:12, Hongtao Liu wrote: On Wed, Jun 21, 2023 at 2:29 PM Jan Beulich via Gcc-patches wrote: > > ---

[PATCH] LoongArch: Remove redundant barrier instructions before LL-SC loops

This is isomorphic to the LLVM changes [1-2]. On LoongArch, the LL and SC instructions has memory barrier semantics: - LL: + - SC: + But the compare and swap operation is allowed to fail, and if it fails the SC instruction is not executed, thus the guarantee of acquiring semantics cannot be

[PATCH 3/3] attribs: Namespace-aware lookup_attribute_spec

attribute_ignored_p already used a namespace-aware query to find the attribute_spec for an existing attribute: const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr)); This patch does the same for other callers in the file. Tested on aarch64-linux-gnu & x86_64-linux-gnu.

[PATCH 2/3] attribs: Consider namespaces when comparing attributes

decl_attributes and comp_type_attributes both had code that iterated over one list of attributes and looked for coresponding attributes in another list. This patch makes those lookups namespace-aware. Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install? Richard gcc/ *

Re: [PATCH] attribs: Use existing traits for excl_hash_traits

Ping. Richard Sandiford via Gcc-patches writes: > excl_hash_traits can be defined more simply by reusing existing traits. > > Tested on aarch64-linux-gnu. OK to install? > > Richard > > > gcc/ > * attribs.cc (excl_hash_traits): Delete. > (test_attribute_exclusions): Use pair_hash

[committed] libgfortran: Fix calloc call by swapping arg order [PR112364]

See PR for a discussion whether this change is required for alignment (or other) reasons (looks as if not) - or"just" to match the indented order (arg names + description) and to silence a -Walloc-size warning. Committed as r14-5148-g17df6ddcf11aef (BTW: I don't think that it is worthwhile to

[PATCH] testsuite: require avx_runtime for some tests

These 3 tests fails parsing the 'vect' dump when not using -mavx. Make the dependency explicit. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-ifcvt-18.c: Add dep on avx_runtime. * gcc.dg/vect/vect-simd-clone-16f.c: Likewise. * gcc.dg/vect/vect-simd-clone-18f.c: Likewise.

Re: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Stamatis Markianos-Wright writes: >> One of the main reasons for reading the arm bits was to try to answer >> the question: if we switch to a downcounting loop with a GE condition, >> how do we make sure that the start value is not a large unsigned >> number that is interpreted as negative by GE?

[PATCH 0/2] libgfortran: empty array fixes [PR112371]

Hello, while preparing a testcase, I encountered a bug which I filed as PR112371. Investigating further, I found two different problems which I propose to fix with the followup patches. Those have been bootstraped and regression tested on x86_64-pc-linux-gnu. OK for master? Mikael Mikael

[PATCH] libstdc++/112351 - deal with __gthread_once failure during locale init

The following makes the C++98 locale init path follow the way the C++11 performs initialization. This way we deal with pthread_once failing, falling back to non-threadsafe initialization which, given we initialize from the library, should be serialized by the dynamic loader already. Bootstrapped

Re: [PATCH v2] AArch64: Fix strict-align cpymem/setmem [PR103100]

ping   v2: Use UINTVAL, rename max_mops_size. The cpymemdi/setmemdi implementation doesn't fully support strict alignment. Block the expansion if the alignment is less than 16 with STRICT_ALIGNMENT. Clean up the condition when to use MOPS.     Passes regress/bootstrap, OK for commit?    

Re: [PATCH] AArch64: Cleanup memset expansion

ping   Cleanup memset implementation.  Similar to memcpy/memmove, use an offset and bytes throughout.  Simplify the complex calculations when optimizing for size by using a fixed limit. Passes regress/bootstrap, OK for commit?     gcc/ChangeLog:     * config/aarch64/aarch64.cc

Re: [PATCH] AArch64: Fix __sync_val_compare_and_swap [PR111404]

  ping   __sync_val_compare_and_swap may be used on 128-bit types and either calls the outline atomic code or uses an inline loop.  On AArch64 LDXP is only atomic if the value is stored successfully using STXP, but the current implementations do not perform the store if the comparison fails.  In

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

  ping From: Wilco Dijkstra Sent: 04 August 2023 16:05 To: GCC Patches ; Richard Sandiford Cc: Kyrylo Tkachov Subject: [PATCH] libatomic: Improve ifunc selection on AArch64   Add support for ifunc selection based on CPUID register.  Neoverse N1 supports atomic 128-bit load/store, so use

Re: [PATCH] libstdc++/112351 - deal with __gthread_once failure during locale init

On Mon, 6 Nov 2023 at 11:52, Richard Biener wrote: > > The following makes the C++98 locale init path follow the way the > C++11 performs initialization. This way we deal with pthread_once > failing, falling back to non-threadsafe initialization which, given we > initialize from the library,

Re: [PATCH] libstdc++/112351 - deal with __gthread_once failure during locale init

On Mon, Nov 06, 2023 at 11:52:08AM +, Richard Biener wrote: > The following makes the C++98 locale init path follow the way the > C++11 performs initialization. This way we deal with pthread_once > failing, falling back to non-threadsafe initialization which, given we > initialize from the

[PATCH 1/3] attribs: Cache the gnu namespace

Later patches add more calls to get_attribute_namespace. For scoped attributes, this is a simple operation on tree pointers. But for normal GNU attributes (the vast majority), it involves a call to get_identifier ("gnu"). This patch caches the identifier for speed. Admittedly I'm just going off

[PATCH] Avoid generating RTL code when d->testing_p.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. gcc/ChangeLog: PR target/112393 * config/i386/i386-expand.cc (ix86_expand_vec_perm_vpermt2): Avoid generating RTL code when d->testing_p. gcc/testsuite/ChangeLog: *

[PATCH] testsuite: skip gcc.target/i386/pr106910-1.c test when using newlib

Using newlib produces a different codegen because the support for c99 differs (see libc_has_function hook). gcc/testsuite/ChangeLog: * gcc.target/i386/pr106910-1.c: Disable for newlib. --- Tested on x86_64-linux and x86_64-elf. OK for master? gcc/testsuite/gcc.target/i386/pr106910-1.c

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