Re: [fortran, patch] Follow-up widechar error patch
FX wrote: This patch fixes PR 52559 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52559), which was due to my earlier patch for displaying error loci in lines containing wide characters (http://gcc.gnu.org/ml/fortran/2012-03/msg00015.html). In preexisting code, a tab is displayed as a single space when an error is printed. I didn't handle it consistently, which should now be fixed. Bootstrapped and regtested on x86_64-apple-darwin11. OK to commit? OK. Thanks for the patch! Tobias
Re: [patch] Fix non-standard Ada bootstrap failure on IA-64
It could be the case that an alternate, legitimate representation of the same expression is used elsewhere, and at the point that goes into cselib, the previously debug-only entry should become a regular entry in the cselib table. Is this what you observe? Sure, that's what I've been saying since the beginning: a legitimate (address) expression coming from a regular insn is equivalenced to the non-legitimate expression already present in the table because of a debug insn and, thus, the location of the latter is promoted to non-debug. If that's it, maybe we need to somehow mark debug-only locs in loc lists, and get some code other than VTA to skip the debug-only locs, or somethink like that. Do you mean getting rid of the promotion-to-non-debug-location code? -- Eric Botcazou
[SH] PR 50751 - Add QImode displacement addressing
Hi,
This is an updated version of the QImode displacement addressing patch
from the PR that applies to rev 185405. Tested on sh-sim with no new
failures.
The issue as a whole requires some more work and I'd like to split it in
smaller incremental changes and separate patches.
Cheers,
Oleg
ChangeLog:
PR target/50751
* config/sh/sh.h (CONST_OK_FOR_K04, CONST_OK_FOR_K12,
DISP_ADDR_P, DISP_ADDR_OFFSET): New macros.
* config/sh/sh.c (sh_address_cost): Add SH2A special case.
(sh_legitimate_index_p): Allow QImode displacements for
non-SH2A.
(sh_legitimize_address): Add QImode displacement handling.
(sh_cannot_change_mode_class): Disallow GENERAL_REGS for SFmode
vector subregs.
(sh_secondary_reload): Add QImode displacement handling.
* config/sh/predicates.md (movsrc_no_disp_mem_operand): New
predicate.
* config/sh/constraints.md (K04, Snd, Sdd): New constraints.
* config/sh/sh.md (extendqisi2): Remove constraints from
expander.
(*extendqisi2_compact): Rename to *extendqisi2_compact_reg,
restrict to register operands only.
(*extendqisi2_compact_mem_disp, *extendqisi2_compact_snd): New
insns.
(extendqihi2): Change insn to expander.
(*extendqihi2_compact_reg): New insn.
(movqi_i, movqi): Replace with ...
(movqi, *movqi_reg_reg, *movqi_store_mem_disp12,
*movqi_load_mem_disp, *movqi_load_mem_disp): ... these.
Add new peepholes for QImode displacement addressing.
Index: gcc/config/sh/predicates.md
===
--- gcc/config/sh/predicates.md (revision 185405)
+++ gcc/config/sh/predicates.md (working copy)
@@ -418,6 +418,30 @@
return general_operand (op, mode);
})
+;; Same as movsrc_operand, but rejects displacement addressing.
+
+(define_predicate movsrc_no_disp_mem_operand
+ (match_code subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector)
+{
+ if (!general_movsrc_operand (op, mode))
+return 0;
+
+ if ((mode == QImode || mode == HImode)
+ mode == GET_MODE (op)
+ (MEM_P (op)
+ || (GET_CODE (op) == SUBREG MEM_P (SUBREG_REG (op)
+{
+ rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
+
+ if (GET_CODE (x) == PLUS
+ REG_P (XEXP (x, 0))
+ CONST_INT_P (XEXP (x, 1)))
+ return 0;
+}
+
+ return 1;
+})
+
;; Returns 1 if OP can be a destination of a move. Same as
;; general_operand, but no preinc allowed.
Index: gcc/config/sh/sh.c
===
--- gcc/config/sh/sh.c (revision 185405)
+++ gcc/config/sh/sh.c (working copy)
@@ -3137,6 +3137,11 @@
sh_address_cost (rtx X,
bool speed ATTRIBUTE_UNUSED)
{
+ /* SH2A supports 4 byte displacement mov insns with higher offsets.
+ Consider those as more expensive than 2 byte insns. */
+ if (DISP_ADDR_P (X) GET_MODE (X) == QImode)
+return DISP_ADDR_OFFSET (X) 16 ? 0 : 1;
+
return (GET_CODE (X) == PLUS
! CONSTANT_P (XEXP (X, 1))
! TARGET_SHMEDIA ? 1 : 0);
@@ -9606,11 +9611,13 @@
if (TARGET_SH2A)
{
- if (GET_MODE_SIZE (mode) == 1
- (unsigned) INTVAL (op) 4096)
+ if (mode == QImode (unsigned) INTVAL (op) 4096)
return true;
}
+ if (mode == QImode (unsigned) INTVAL (op) 16)
+ return true;
+
if ((GET_MODE_SIZE (mode) == 4
(unsigned) INTVAL (op) 64
!(INTVAL (op) 3)
@@ -9816,6 +9823,25 @@
}
}
+ /* This could be generalized for SImode, HImode, QImode displacement
+ addressing. */
+ if (mode == QImode GET_CODE (x) == PLUS
+ BASE_REGISTER_RTX_P (XEXP (x, 0)) CONST_INT_P (XEXP (x, 1)))
+{
+ rtx index_rtx = XEXP (x, 1);
+ HOST_WIDE_INT offset = INTVAL (index_rtx);
+ HOST_WIDE_INT offset_base = offset ~15;
+
+ if (offset - offset_base = 16)
+ {
+ rtx sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
+ GEN_INT (offset_base), NULL_RTX, 0,
+ OPTAB_LIB_WIDEN);
+
+ return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
+ }
+}
+
return x;
}
@@ -11444,8 +11470,13 @@
{
/* We want to enable the use of SUBREGs as a means to
VEC_SELECT a single element of a vector. */
+
+ /* This effectively disallows using GENERAL_REGS for SFmode vector subregs.
+ This can be problematic when SFmode vector subregs need to be accessed
+ on the stack with displacement addressing, as it happens with -O0.
+ Thus we disallow the mode change for -O0. */
if (to == SFmode VECTOR_MODE_P (from) GET_MODE_INNER (from) == SFmode)
-return (reg_classes_intersect_p (GENERAL_REGS, rclass));
+return optimize ? (reg_classes_intersect_p (GENERAL_REGS, rclass)) : false;
if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
{
@@ -11460,7 +11491,7 @@
return reg_classes_intersect_p (DF_HI_REGS, rclass);
}
Re: [Patch]: Uncouple size_t and sizetype
currently sizetype precision (cf store-layout.c:initialize_sizetypes) is the same as size_t. This is an issue on VMS, where size_t is 'unsigned int', but we'd like to have a 64 bit sizetype for Ada. My understanding is that ISO-C doesn't require size_t precision to match the one of void *. In fact this is very recent: up to (and including) GCC 4.6, each language could set its own sizetype (by means of set_sizetype). I initially thought about using Pmode precision for sizetype precision, but there are a few machines (m32c, sh, h8300) where the precisions aren't the same. I don't know wether this is on purpose or unintentional. That's what we used to do in Ada, see gnat_init: /* In Ada, we use the unsigned type corresponding to the width of Pmode as SIZETYPE. In most cases when ptr_mode and Pmode differ, C will use the width of ptr_mode for SIZETYPE, but we get better code using the width of Pmode. Note that, although we manipulate negative offsets for some internal constructs and rely on compile time overflow detection in size computations, using unsigned types for SIZETYPEs is fine since they are treated specially by the middle-end, in particular sign-extended. */ size_type_node = gnat_type_for_mode (Pmode, 1); set_sizetype (size_type_node); TYPE_NAME (sizetype) = get_identifier (size_type); -- Eric Botcazou
Re: [Patch]: Uncouple size_t and sizetype
The middle-end of course would not care much what you use for sizetype. But be warned - if the mode for sizetype is different of ptr_mode things are going to be interesting for you (yes, ptr_mode, not Pmode). That worked well up to GCC 4.6 though, at least in Ada. Of course using the same setting in all languages would be even better than we used to have. -- Eric Botcazou
Re: [Patch]: Uncouple size_t and sizetype
On Mar 19, 2012, at 9:46 AM, Eric Botcazou wrote: The middle-end of course would not care much what you use for sizetype. But be warned - if the mode for sizetype is different of ptr_mode things are going to be interesting for you (yes, ptr_mode, not Pmode). That worked well up to GCC 4.6 though, at least in Ada. Of course using the same setting in all languages would be even better than we used to have. I am lost here. Which targets (with ptr_mode size != Pmode size != sizetype size) are you referring to ? Tristan.
Re: [SH] PR 50751 - Add QImode displacement addressing
Oleg Endo oleg.e...@t-online.de wrote: This is an updated version of the QImode displacement addressing patch from the PR that applies to rev 185405. Tested on sh-sim with no new failures. The issue as a whole requires some more work and I'd like to split it in smaller incremental changes and separate patches. Either way, the patch is OK. Regards, kaz
Re: [Patch]: Uncouple size_t and sizetype
I am lost here. Which targets (with ptr_mode size != Pmode size != sizetype size) are you referring to ? Targets for which sizetype mode isn't necessarily equal to ptr_mode like VMS. Up to GCC 4.6, sizetype was Pmode in Ada, but ptr_mode in C. -- Eric Botcazou
Re: [Patch]: Uncouple size_t and sizetype
On Mon, 19 Mar 2012, Eric Botcazou wrote: I am lost here. Which targets (with ptr_mode size != Pmode size != sizetype size) are you referring to ? Targets for which sizetype mode isn't necessarily equal to ptr_mode like VMS. Up to GCC 4.6, sizetype was Pmode in Ada, but ptr_mode in C. It does make sense to give the target control over the mode used for sizetype. Of course a global change of the default (for example to use Pmode as Ada did) will require testing each affected target, so I think it makes sense to keep the default as-is. Btw, we still have the issue on which _precision_ we should use for sizetype -- if we expect modulo-semantics of arithmetic using it (thus basically sign-less arithmetic) then the precision has to match the expectation the C frontend (and other frontends) assume how pointer offsets are handled. Currently the C frontend gets this not correct which means negative offsets will be not correctly handled. Similar issues arise from the mode/precision chosen for the bitsize types. We choose a way to wide precision for them, so the modulo-semantics assumption does not usually hold for bitsize quantities. Richard.
Re: [Patch]: Uncouple size_t and sizetype
On Mar 19, 2012, at 10:41 AM, Eric Botcazou wrote: I am lost here. Which targets (with ptr_mode size != Pmode size != sizetype size) are you referring to ? Targets for which sizetype mode isn't necessarily equal to ptr_mode like VMS. VMS was (in gcc 4.8) configured with POINTER_SIZE = 64, Pmode = DImode and sizetype = unsigned long long int. Up to GCC 4.6, sizetype was Pmode in Ada, but ptr_mode in C. Yes. Tristan.
Re: [PATCH] Fix PRs 52080, 52097 and 48124, rewrite bitfield expansion, enable the C++ memory model wrt bitfields everywhere
But it's only ever computed for RECORD_TYPEs where DECL_QUALIFIER is unused. OK, that could work indeed. For now giving up seems to be easiest (just give up when DECL_FIELD_OFFSET is not equal for all of the bitfield members). That will at most get you the miscompiles for the PRs back, for languages with funny structure layout. I have another variant of the DECL_FIELD_OFFSET problem: FAIL: gnat.dg/specs/pack8.ads (test for excess errors) Excess errors: +===GNAT BUG DETECTED==+ | 4.8.0 20120314 (experimental) [trunk revision 185395] (i586-suse-linux) GCC error:| | in finish_bitfield_representative, at stor-layout.c:1762 | | Error detected at pack8.ads:17:4 Testcase attached: gnat.dg/specs/pack8.ads gnat.dg/specs/pack8_pkg.ads I agree that giving up (for now) is a sensible option. Thanks. -- Eric Botcazou with Pack8_Pkg; package Pack8 is subtype Index_Type is Integer range 1 .. Pack8_Pkg.N; subtype Str is String( Index_Type); subtype Str2 is String (1 .. 11); type Rec is record S1 : Str; S2 : Str; B : Boolean; S3 : Str2; end record; pragma Pack (Rec); end Pack8; package Pack8_Pkg is N : Natural := 1; end Pack8_Pkg;
Re: [Patch]: Uncouple size_t and sizetype
On Mon, 19 Mar 2012, Eric Botcazou wrote: It does make sense to give the target control over the mode used for sizetype. Of course a global change of the default (for example to use Pmode as Ada did) will require testing each affected target, so I think it makes sense to keep the default as-is. No disagreement here. Btw, we still have the issue on which _precision_ we should use for sizetype -- if we expect modulo-semantics of arithmetic using it (thus basically sign-less arithmetic) then the precision has to match the expectation the C frontend (and other frontends) assume how pointer offsets are handled. Currently the C frontend gets this not correct which means negative offsets will be not correctly handled. Is this theoritical or practical? Are you talking about GET_MODE_BITSIZE vs GET_MODE_PRECISION wrt TYPE_PRECISION? No, about the disagreement of the precision of ptrdiff_t and that of sizetype. See c-common.c:pointer_int_sum: /* Convert the integer argument to a type the same size as sizetype so the multiply won't overflow spuriously. */ if (TYPE_PRECISION (TREE_TYPE (intop)) != TYPE_PRECISION (sizetype) || TYPE_UNSIGNED (TREE_TYPE (intop)) != TYPE_UNSIGNED (sizetype)) intop = convert (c_common_type_for_size (TYPE_PRECISION (sizetype), TYPE_UNSIGNED (sizetype)), intop); and consider what happens for example on m32c - we truncate the 24bit ptrdiff_t to the 16bit sizetype, losing bits. And we are performing the index * size multiplication in a maybe artificially large type, losing information about overflow behavior and possibly generating slow code for no good reason. ISTR there was a correctness issue here, too, but maybe I've fixed that already. Similar issues arise from the mode/precision chosen for the bitsize types. We choose a way to wide precision for them, so the modulo-semantics assumption does not usually hold for bitsize quantities. Again because of GET_MODE_PRECISION vs GET_MODE_BITSIZE? Otherwise we round up the precision since GCC 4.5 so there should be no more weird precision. Well, because if sizetype is SImode (with -m32) and bitsizetype DImode (we round up its precision to 64bits) then a negative byte-offset in the unsigned sizetype is 0x for example. When we then perform arithmetic on bits, say (bitsizetype)sz * BITS_PER_UNIT + 9 we get 0x * 8 == 0x80001 (oops) + 9 == 0x80001. bitsizetype is of too large precision to be a modulo-arithmetic bit-equivalent to sizetype (at least for our constant-folding code) for negative offsets. Probably one of the reasons of the weird sizetype-is-unsigned-but-constants-are-sign-extended rule. Richard.
Ping #1: [Patch,AVR]: Hack around PR rtl-optimization/52543
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00641.html Georg-Johann Lay wrote: The problem with the PR is that lower-subreg.c happily splits multi-byte moves from address spaces without knowing anything about the additional costs this is causing. The TARGET_MODE_DEPENDENT_ADDRESS_P hook cannot be used for 16-bit addresses because that hook is not sensitive to address spaces, but is is used for the 24-bit address space to avoid subreg lowering for PSImode. For the 16-bit address spaces the mov expander now assigns the address register by hand as post-increment. Luckily, post-increment is the only addressing mode that makes sense with the non-generic address spaces and there is no choice for the address register resp. addressing mode, anyway... This patch does not fix the PR issue, of course, it just avoids subreg lowering by using/pretending mode-dependent addresses. Ok for trunk? Johann PR rtl-optimization/52543 * config/avr/avr.c (avr_mode_dependent_address_p): New function. (TARGET_MODE_DEPENDENT_ADDRESS_P): New define. * config/avr/avr.md (unspec): Add UNSPEC_LPM. (load_mode_libgcc): Use UNSPEC_LPM instead of MEM. (movmode): For multi-byte move from non-generic 16-bit address spaces: Expand to use Z++ as address for inline code and use UNSPEC_LPM (Z) for code from libgcc. (loadmode_libgcc): Remove expander. (split-lpmx): Remove split.
Re: Ping #1: [Patch,AVR]: Hack around PR rtl-optimization/52543
2012/3/19 Georg-Johann Lay a...@gjlay.de: http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00641.html Georg-Johann Lay wrote: The problem with the PR is that lower-subreg.c happily splits multi-byte moves from address spaces without knowing anything about the additional costs this is causing. The TARGET_MODE_DEPENDENT_ADDRESS_P hook cannot be used for 16-bit addresses because that hook is not sensitive to address spaces, but is is used for the 24-bit address space to avoid subreg lowering for PSImode. For the 16-bit address spaces the mov expander now assigns the address register by hand as post-increment. Luckily, post-increment is the only addressing mode that makes sense with the non-generic address spaces and there is no choice for the address register resp. addressing mode, anyway... This patch does not fix the PR issue, of course, it just avoids subreg lowering by using/pretending mode-dependent addresses. Ok for trunk? Johann PR rtl-optimization/52543 * config/avr/avr.c (avr_mode_dependent_address_p): New function. (TARGET_MODE_DEPENDENT_ADDRESS_P): New define. * config/avr/avr.md (unspec): Add UNSPEC_LPM. (load_mode_libgcc): Use UNSPEC_LPM instead of MEM. (movmode): For multi-byte move from non-generic 16-bit address spaces: Expand to use Z++ as address for inline code and use UNSPEC_LPM (Z) for code from libgcc. (loadmode_libgcc): Remove expander. (split-lpmx): Remove split. Approved. Denis.
Re: [Patch]: Uncouple size_t and sizetype
On Mar 16, 2012, at 12:38 PM, Richard Guenther wrote:
[…]
Well, this setup is not well supported by the middle-end (and indeed m32c
has existing issues with that). So in your case decoupling sizetype from
size_t sounds like the more appropriate solution.
Btw, while we are transitioning to target hooks in this case I'd prefer
a target macro alongside the existing SIZE_TYPE, etc. ones.
Ok.
I'd choose SIZETYPE (for confusion, heh), defaulting to SIZE_TYPE.
Richard.
Hi,
here is the patch. As SIZETYPE was already used as a size_type_kind
enumeration constant, I made a little renaming work.
Bootstrapped, no regressions on x86_64-darwin. Tested on ia64-hp-openvms.
Ok for trunk ?
Tristan.
2012-03-19 Tristan Gingold ging...@adacore.com
* tree.h (enum size_type_kind): Add STK_ prefix to constants.
(sizetype_tab, sizetype, bitsizetype, ssizetype, sbitsizetype)
(size_int, ssize_int, bitsize_int, sbitsize_int): Adjust.
* stor-layout.c (sizetype_tab): Adjust.
(initialize_sizetypes): Use SIZETYPE instead of SIZE_TYPE.
* tree-streamer.c (preload_common_nodes): Use STK_TYPE_KIND_LAST
instead of TYPE_KIND_LAST.
* tree-scalar-evolution.c (interpret_rhs_expr): Use size_int
instead of size_int_kind.
* doc/tm.texi.in (Type Layout): Document SIZETYPE.
* doc/tm.texi: Regenerate.
* defaults.h (SIZETYPE): Provide a default value.
* config/vms/vms.h (SIZE_TYPE): Define as unsigned int.
(SIZETYPE): Define.
diff --git a/gcc/config/vms/vms.h b/gcc/config/vms/vms.h
index f2bc354..47028c8 100644
--- a/gcc/config/vms/vms.h
+++ b/gcc/config/vms/vms.h
@@ -60,15 +60,18 @@ extern void vms_c_register_includes (const char *, const
char *, int);
#define POINTER_SIZE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? 32 : 64)
#define POINTERS_EXTEND_UNSIGNED 0
-/* FIXME: It should always be a 32 bit type. */
+/* Always a 32 bit type. */
#undef SIZE_TYPE
-#define SIZE_TYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
- unsigned int : long long unsigned int)
+#define SIZE_TYPE unsigned int
+
/* ???: Defined as a 'int' by dec-c, but obstack.h doesn't like it. */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
int : long long int)
+#define SIZETYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
+ unsigned int : long long unsigned int)
+
#define C_COMMON_OVERRIDE_OPTIONS vms_c_common_override_options ()
/* VMS doesn't support other sections than .text for code. */
diff --git a/gcc/defaults.h b/gcc/defaults.h
index 1780dda..296bb6a 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -582,6 +582,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively.
If not, see
#define SIZE_TYPE long unsigned int
#endif
+#ifndef SIZETYPE
+#define SIZETYPE SIZE_TYPE
+#endif
+
#ifndef PID_TYPE
#define PID_TYPE int
#endif
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 69f8aba..2891bb6 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -1642,6 +1642,18 @@ If you don't define this macro, the default is
@code{long unsigned
int}.
@end defmac
+@defmac SIZETYPE
+GCC defines internal types (@code{sizetype}, @code{ssizetype},
+@code{bitsizetype} and @code{sbitsizetype}) for expressions
+dealing with size. This macro is a C expression for a string describing
+the name of the data type from which the precision of @code{sizetype}
+is extracted.
+
+The string has the same restrictions as @code{SIZE_TYPE} string.
+
+If you don't define this macro, the default is @code{SIZE_TYPE}.
+@end defmac
+
@defmac PTRDIFF_TYPE
A C expression for a string describing the name of the data type to use
for the result of subtracting two pointers. The typedef name
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index c24cf1e..a222654 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -1630,6 +1630,18 @@ If you don't define this macro, the default is
@code{long unsigned
int}.
@end defmac
+@defmac SIZETYPE
+GCC defines internal types (@code{sizetype}, @code{ssizetype},
+@code{bitsizetype} and @code{sbitsizetype}) for expressions
+dealing with size. This macro is a C expression for a string describing
+the name of the data type from which the precision of @code{sizetype}
+is extracted.
+
+The string has the same restrictions as @code{SIZE_TYPE} string.
+
+If you don't define this macro, the default is @code{SIZE_TYPE}.
+@end defmac
+
@defmac PTRDIFF_TYPE
A C expression for a string describing the name of the data type to use
for the result of subtracting two pointers. The typedef name
diff --git a/gcc/stor-layout.c b/gcc/stor-layout.c
index 98b7886..479c407 100644
--- a/gcc/stor-layout.c
+++ b/gcc/stor-layout.c
@@ -44,7 +44,7 @@ along with GCC; see the file COPYING3. If not see
/* Data type for the expressions representing sizes of data types.
It is the first integer
[patch] Minor tweaks
Hi,
around line 380, we have in tree.def:
/* References to storage. */
/* The ordering of the following codes is optimized for the classification
in handled_component_p. Keep them in a consecutive group. */
The hitch is that VIEW_CONVERT_EXPR is far apart from the others, so the patch
puts them together (and orders them consistently). It also tweaks a couple of
places where callers of get_inner_reference initializes unsignedp:
int unsignedp = 0, volatilep = 0;
decl = get_inner_reference (decl, bitsize, bitpos, toffset,
mode, unsignedp, volatilep, false);
This is useless since unsignedp is always set (unlike volatilep).
Tested on i586-suse-linux, OK for the mainline?
2012-03-19 Eric Botcazou ebotca...@adacore.com
* tree.def (REALPART_EXPR, IMAGPART_EXPR, VIEW_CONVERT_EXPR): Move.
* tree.h (handled_component_p): Reorder cases.
* dwarf2out.c (loc_list_for_address_of_addr_expr_of_indirect_ref): Do
not initialize unsignedp.
(loc_list_from_tree): Likewise.
(fortran_common): Likewise.
* simplify-rtx.c (delegitimize_mem_from_attrs): Likewise.
--
Eric Botcazou
Index: dwarf2out.c
===
--- dwarf2out.c (revision 185395)
+++ dwarf2out.c (working copy)
@@ -13328,8 +13328,8 @@ cst_pool_loc_descr (tree loc)
}
/* Return dw_loc_list representing address of addr_expr LOC
- by looking for innder INDIRECT_REF expression and turing it
- into simple arithmetics. */
+ by looking for inner INDIRECT_REF expression and turning
+ it into simple arithmetics. */
static dw_loc_list_ref
loc_list_for_address_of_addr_expr_of_indirect_ref (tree loc, bool toplev)
@@ -13337,8 +13337,7 @@ loc_list_for_address_of_addr_expr_of_ind
tree obj, offset;
HOST_WIDE_INT bitsize, bitpos, bytepos;
enum machine_mode mode;
- int volatilep;
- int unsignedp = TYPE_UNSIGNED (TREE_TYPE (loc));
+ int unsignedp, volatilep = 0;
dw_loc_list_ref list_ret = NULL, list_ret1 = NULL;
obj = get_inner_reference (TREE_OPERAND (loc, 0),
@@ -13628,8 +13627,7 @@ loc_list_from_tree (tree loc, int want_a
tree obj, offset;
HOST_WIDE_INT bitsize, bitpos, bytepos;
enum machine_mode mode;
- int volatilep;
- int unsignedp = TYPE_UNSIGNED (TREE_TYPE (loc));
+ int unsignedp, volatilep = 0;
obj = get_inner_reference (loc, bitsize, bitpos, offset, mode,
unsignedp, volatilep, false);
@@ -14927,7 +14925,7 @@ fortran_common (tree decl, HOST_WIDE_INT
enum machine_mode mode;
HOST_WIDE_INT bitsize, bitpos;
tree offset;
- int volatilep = 0, unsignedp = 0;
+ int unsignedp, volatilep = 0;
/* If the decl isn't a VAR_DECL, or if it isn't static, or if
it does not have a value (the offset into the common area), or if it
Index: simplify-rtx.c
===
--- simplify-rtx.c (revision 185395)
+++ simplify-rtx.c (working copy)
@@ -293,7 +293,7 @@ delegitimize_mem_from_attrs (rtx x)
{
HOST_WIDE_INT bitsize, bitpos;
tree toffset;
- int unsignedp = 0, volatilep = 0;
+ int unsignedp, volatilep = 0;
decl = get_inner_reference (decl, bitsize, bitpos, toffset,
mode, unsignedp, volatilep, false);
Index: tree.def
===
--- tree.def (revision 185395)
+++ tree.def (working copy)
@@ -400,11 +400,6 @@ DEFTREECODE (COMPONENT_REF, component_r
to its mode width. */
DEFTREECODE (BIT_FIELD_REF, bit_field_ref, tcc_reference, 3)
-/* Used only on an operand of complex type, these return
- a value of the corresponding component type. */
-DEFTREECODE (REALPART_EXPR, realpart_expr, tcc_reference, 1)
-DEFTREECODE (IMAGPART_EXPR, imagpart_expr, tcc_reference, 1)
-
/* Array indexing.
Operand 0 is the array; operand 1 is a (single) array index.
Operand 2, if present, is a copy of TYPE_MIN_VALUE of the index.
@@ -417,6 +412,23 @@ DEFTREECODE (ARRAY_REF, array_ref, tcc
of the range is taken from the type of the expression. */
DEFTREECODE (ARRAY_RANGE_REF, array_range_ref, tcc_reference, 4)
+/* Used only on an operand of complex type, these return
+ a value of the corresponding component type. */
+DEFTREECODE (REALPART_EXPR, realpart_expr, tcc_reference, 1)
+DEFTREECODE (IMAGPART_EXPR, imagpart_expr, tcc_reference, 1)
+
+/* Represents viewing something of one type as being of a second type.
+ This corresponds to an Unchecked Conversion in Ada and roughly to
+ the idiom *(type2 *)X in C. The only operand is the value to be
+ viewed as being of another type. It is undefined if the type of the
+ input and of the expression have different sizes.
+
+ This code may also be used within the LHS of a MODIFY_EXPR, in which
+ case no actual data motion may occur. TREE_ADDRESSABLE will be set in
+ this case and GCC must abort if it could not do the operation
Re: [patch] Minor tweaks
On Mon, Mar 19, 2012 at 1:21 PM, Eric Botcazou ebotca...@adacore.com wrote: Hi, around line 380, we have in tree.def: /* References to storage. */ /* The ordering of the following codes is optimized for the classification in handled_component_p. Keep them in a consecutive group. */ The hitch is that VIEW_CONVERT_EXPR is far apart from the others, so the patch puts them together (and orders them consistently). It also tweaks a couple of places where callers of get_inner_reference initializes unsignedp: int unsignedp = 0, volatilep = 0; decl = get_inner_reference (decl, bitsize, bitpos, toffset, mode, unsignedp, volatilep, false); This is useless since unsignedp is always set (unlike volatilep). Tested on i586-suse-linux, OK for the mainline? Ok. I think volatilep should be always set as well. Thanks, Richard. 2012-03-19 Eric Botcazou ebotca...@adacore.com * tree.def (REALPART_EXPR, IMAGPART_EXPR, VIEW_CONVERT_EXPR): Move. * tree.h (handled_component_p): Reorder cases. * dwarf2out.c (loc_list_for_address_of_addr_expr_of_indirect_ref): Do not initialize unsignedp. (loc_list_from_tree): Likewise. (fortran_common): Likewise. * simplify-rtx.c (delegitimize_mem_from_attrs): Likewise. -- Eric Botcazou
Re: [debug/profile-mode] broken c++config.h
On 03/16/2012 06:16 PM, Jonathan Wakely wrote: 2012/3/16 Paweł Sikora: Should the addition be \$$ to escape it for the shell as well as for make? (I know it works, but that might not be true for all shells.) i don't think that $, could be expaneded by any shell. I'm not worried about it not expanding, but rather being rejected as invalid syntax - but maybe it's fine. It certainly works OK with bash and ksh. Thus, are we going to apply the patch? Maybe Paolo can double check the sed detail. Thanks, Paolo.
Re: [Patch]: Uncouple size_t and sizetype
On Mon, Mar 19, 2012 at 1:02 PM, Tristan Gingold ging...@adacore.com wrote:
On Mar 16, 2012, at 12:38 PM, Richard Guenther wrote:
[…]
Well, this setup is not well supported by the middle-end (and indeed m32c
has existing issues with that). So in your case decoupling sizetype from
size_t sounds like the more appropriate solution.
Btw, while we are transitioning to target hooks in this case I'd prefer
a target macro alongside the existing SIZE_TYPE, etc. ones.
Ok.
I'd choose SIZETYPE (for confusion, heh), defaulting to SIZE_TYPE.
Richard.
Hi,
here is the patch. As SIZETYPE was already used as a size_type_kind
enumeration constant, I made a little renaming work.
Bootstrapped, no regressions on x86_64-darwin. Tested on ia64-hp-openvms.
Ok for trunk ?
Ok with a minor nit - can you make STK_* lower-case now, similar to
itk_ and ti_? They are not macros after all.
Thanks,
Richard.
Tristan.
2012-03-19 Tristan Gingold ging...@adacore.com
* tree.h (enum size_type_kind): Add STK_ prefix to constants.
(sizetype_tab, sizetype, bitsizetype, ssizetype, sbitsizetype)
(size_int, ssize_int, bitsize_int, sbitsize_int): Adjust.
* stor-layout.c (sizetype_tab): Adjust.
(initialize_sizetypes): Use SIZETYPE instead of SIZE_TYPE.
* tree-streamer.c (preload_common_nodes): Use STK_TYPE_KIND_LAST
instead of TYPE_KIND_LAST.
* tree-scalar-evolution.c (interpret_rhs_expr): Use size_int
instead of size_int_kind.
* doc/tm.texi.in (Type Layout): Document SIZETYPE.
* doc/tm.texi: Regenerate.
* defaults.h (SIZETYPE): Provide a default value.
* config/vms/vms.h (SIZE_TYPE): Define as unsigned int.
(SIZETYPE): Define.
diff --git a/gcc/config/vms/vms.h b/gcc/config/vms/vms.h
index f2bc354..47028c8 100644
--- a/gcc/config/vms/vms.h
+++ b/gcc/config/vms/vms.h
@@ -60,15 +60,18 @@ extern void vms_c_register_includes (const char *, const
char *, int);
#define POINTER_SIZE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? 32 :
64)
#define POINTERS_EXTEND_UNSIGNED 0
-/* FIXME: It should always be a 32 bit type. */
+/* Always a 32 bit type. */
#undef SIZE_TYPE
-#define SIZE_TYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
- unsigned int : long long unsigned int)
+#define SIZE_TYPE unsigned int
+
/* ???: Defined as a 'int' by dec-c, but obstack.h doesn't like it. */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
int : long long int)
+#define SIZETYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
+ unsigned int : long long unsigned int)
+
#define C_COMMON_OVERRIDE_OPTIONS vms_c_common_override_options ()
/* VMS doesn't support other sections than .text for code. */
diff --git a/gcc/defaults.h b/gcc/defaults.h
index 1780dda..296bb6a 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -582,6 +582,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively.
If not, see
#define SIZE_TYPE long unsigned int
#endif
+#ifndef SIZETYPE
+#define SIZETYPE SIZE_TYPE
+#endif
+
#ifndef PID_TYPE
#define PID_TYPE int
#endif
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 69f8aba..2891bb6 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -1642,6 +1642,18 @@ If you don't define this macro, the default is
@code{long unsigned
int}.
@end defmac
+@defmac SIZETYPE
+GCC defines internal types (@code{sizetype}, @code{ssizetype},
+@code{bitsizetype} and @code{sbitsizetype}) for expressions
+dealing with size. This macro is a C expression for a string describing
+the name of the data type from which the precision of @code{sizetype}
+is extracted.
+
+The string has the same restrictions as @code{SIZE_TYPE} string.
+
+If you don't define this macro, the default is @code{SIZE_TYPE}.
+@end defmac
+
@defmac PTRDIFF_TYPE
A C expression for a string describing the name of the data type to use
for the result of subtracting two pointers. The typedef name
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index c24cf1e..a222654 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -1630,6 +1630,18 @@ If you don't define this macro, the default is
@code{long unsigned
int}.
@end defmac
+@defmac SIZETYPE
+GCC defines internal types (@code{sizetype}, @code{ssizetype},
+@code{bitsizetype} and @code{sbitsizetype}) for expressions
+dealing with size. This macro is a C expression for a string describing
+the name of the data type from which the precision of @code{sizetype}
+is extracted.
+
+The string has the same restrictions as @code{SIZE_TYPE} string.
+
+If you don't define this macro, the default is @code{SIZE_TYPE}.
+@end defmac
+
@defmac PTRDIFF_TYPE
A C expression for a string describing the name of the data type to use
for the result of subtracting two pointers. The typedef name
[PATCH, i386]: Consistently use Pmode
Hello!
This patch uses Pmode consistently for some remaining cases.
No functional change.
2012-03-19 Uros Bizjak ubiz...@gmail.com
* config/i386/i386.c (ix86_expand_prologue) CM_LARGE_PIC: Use Pmode
mode consistently. Use ix86_gen_add3. Assert that Pmode == DImode.
(ix86_expand_split_stack_prologue): Use ix86_gen_add3.
(ix86_split_long_move): Ditto.
(legitimize_tls_address): Use ix86_gen_sub3.
(construct_plt_address): Assert that Pmode == DImode.
Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline.
Uros.
Index: i386.c
===
--- i386.c (revision 185515)
+++ i386.c (working copy)
@@ -10458,15 +10458,19 @@ ix86_expand_prologue (void)
{
if (ix86_cmodel == CM_LARGE_PIC)
{
- rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
- rtx label = gen_label_rtx ();
+ rtx label, tmp_reg;
+
+ gcc_assert (Pmode == DImode);
+ label = gen_label_rtx ();
emit_label (label);
LABEL_PRESERVE_P (label) = 1;
+ tmp_reg = gen_rtx_REG (Pmode, R11_REG);
gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
- insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx,
label));
+ insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx,
+ label));
insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
- insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
- pic_offset_table_rtx, tmp_reg));
+ insn = emit_insn (ix86_gen_add3 (pic_offset_table_rtx,
+ pic_offset_table_rtx, tmp_reg));
}
else
insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
@@ -11196,8 +11200,8 @@ ix86_expand_split_stack_prologue (void)
else
{
emit_move_insn (scratch_reg, offset);
- emit_insn (gen_adddi3 (scratch_reg, scratch_reg,
-stack_pointer_rtx));
+ emit_insn (ix86_gen_add3 (scratch_reg, scratch_reg,
+ stack_pointer_rtx));
}
current = scratch_reg;
}
@@ -11244,6 +11248,7 @@ ix86_expand_split_stack_prologue (void)
{
HOST_WIDE_INT argval;
+ gcc_assert (Pmode == DImode);
/* When using the large model we need to load the address
into a register, and we've run out of registers. So we
switch to a different calling convention, and we call a
@@ -11266,7 +11271,7 @@ ix86_expand_split_stack_prologue (void)
LABEL_PRESERVE_P (label) = 1;
emit_insn (gen_set_rip_rex64 (reg10, label));
emit_insn (gen_set_got_offset_rex64 (reg11, label));
- emit_insn (gen_adddi3 (reg10, reg10, reg11));
+ emit_insn (ix86_gen_add3 (reg10, reg10, reg11));
x = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, split_stack_fn_large),
UNSPEC_GOT);
x = gen_rtx_CONST (Pmode, x);
@@ -12722,7 +12727,7 @@ legitimize_tls_address (rtx x, enum tls_model mode
{
base = get_thread_pointer (true);
dest = gen_reg_rtx (Pmode);
- emit_insn (gen_subsi3 (dest, base, off));
+ emit_insn (ix86_gen_sub3 (dest, base, off));
}
break;
@@ -12743,7 +12748,7 @@ legitimize_tls_address (rtx x, enum tls_model mode
{
base = get_thread_pointer (true);
dest = gen_reg_rtx (Pmode);
- emit_insn (gen_subsi3 (dest, base, off));
+ emit_insn (ix86_gen_sub3 (dest, base, off));
}
break;
@@ -20626,8 +20631,8 @@ ix86_split_long_move (rtx operands[])
if (nparts == 3)
{
if (TARGET_128BIT_LONG_DOUBLE mode == XFmode)
-emit_insn (gen_addsi3 (stack_pointer_rtx,
- stack_pointer_rtx, GEN_INT (-4)));
+emit_insn (ix86_gen_add3 (stack_pointer_rtx,
+ stack_pointer_rtx, GEN_INT (-4)));
emit_move_insn (part[0][2], part[1][2]);
}
else if (nparts == 4)
@@ -22975,14 +22980,17 @@ ix86_expand_strlen (rtx out, rtx src, rtx eoschar,
rtx
construct_plt_address (rtx symbol)
{
- rtx tmp = gen_reg_rtx (Pmode);
- rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
+ rtx tmp, unspec;
gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
gcc_assert (ix86_cmodel == CM_LARGE_PIC);
+ gcc_assert (Pmode == DImode);
+ tmp = gen_reg_rtx (Pmode);
+ unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
+
emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
- emit_insn (gen_adddi3 (tmp, tmp,
Re: [PATCH] Fix PRs 52080, 52097 and 48124, rewrite bitfield expansion, enable the C++ memory model wrt bitfields everywhere
On Mon, 19 Mar 2012, Eric Botcazou wrote:
But it's only ever computed for RECORD_TYPEs where DECL_QUALIFIER is
unused.
OK, that could work indeed.
For now giving up seems to be easiest (just give up when
DECL_FIELD_OFFSET is not equal for all of the bitfield members).
That will at most get you the miscompiles for the PRs back, for
languages with funny structure layout.
I have another variant of the DECL_FIELD_OFFSET problem:
FAIL: gnat.dg/specs/pack8.ads (test for excess errors)
Excess errors:
+===GNAT BUG DETECTED==+
| 4.8.0 20120314 (experimental) [trunk revision 185395] (i586-suse-linux) GCC
error:|
| in finish_bitfield_representative, at stor-layout.c:1762 |
| Error detected at pack8.ads:17:4
Testcase attached:
gnat.dg/specs/pack8.ads
gnat.dg/specs/pack8_pkg.ads
Thanks. That one indeed has different DECL_FIELD_OFFSET,
((sizetype) MAX_EXPR (integer) pack8__R1s, 0 + (sizetype) MAX_EXPR
(integer) pack8__R1s, 0) + 1
vs.
(sizetype) MAX_EXPR (integer) pack8__R1s, 0 + (sizetype) MAX_EXPR
(integer) pack8__R1s, 0
we're not putting the 1 byte offset into DECL_FIELD_BIT_OFFSET
because DECL_OFFSET_ALIGN is 8 in this case. Eventually we should
be able to relax how many bits we push into DECL_FIELD_BIT_OFFSET.
I agree that giving up (for now) is a sensible option. Thanks.
Done with the patch below. We're actually not going to generate
possibly wrong-code again but sub-optimal code.
Bootstrap regtest pending on x86_64-unknown-linux-gnu.
Richard.
2012-03-19 Richard Guenther rguent...@suse.de
* stor-layout.c (finish_bitfield_representative): Fallback
to conservative maximum size if the padding up to the next
field cannot be computed as a constant.
(finish_bitfield_layout): If we cannot compute the distance
between the start of the bitfield representative and the
bitfield member start a new representative.
* expr.c (get_bit_range): The distance between the start of
the bitfield representative and the bitfield member is zero
if the field offsets are not constants.
* gnat.dg/pack16.adb: New testcase.
* gnat.dg/pack16_pkg.ads: Likewise.
* gnat.dg/specs/pack8.ads: Likewise.
* gnat.dg/specs/pack8_pkg.ads: Likewise.
Index: gcc/stor-layout.c
===
*** gcc/stor-layout.c (revision 185518)
--- gcc/stor-layout.c (working copy)
*** finish_bitfield_representative (tree rep
*** 1781,1790
return;
maxsize = size_diffop (DECL_FIELD_OFFSET (nextf),
DECL_FIELD_OFFSET (repr));
! gcc_assert (host_integerp (maxsize, 1));
! maxbitsize = (tree_low_cst (maxsize, 1) * BITS_PER_UNIT
! + tree_low_cst (DECL_FIELD_BIT_OFFSET (nextf), 1)
! - tree_low_cst (DECL_FIELD_BIT_OFFSET (repr), 1));
}
else
{
--- 1781,1792
return;
maxsize = size_diffop (DECL_FIELD_OFFSET (nextf),
DECL_FIELD_OFFSET (repr));
! if (host_integerp (maxsize, 1))
! maxbitsize = (tree_low_cst (maxsize, 1) * BITS_PER_UNIT
! + tree_low_cst (DECL_FIELD_BIT_OFFSET (nextf), 1)
! - tree_low_cst (DECL_FIELD_BIT_OFFSET (repr), 1));
! else
! maxbitsize = bitsize;
}
else
{
*** finish_bitfield_layout (record_layout_in
*** 1888,1893
--- 1890,1897
}
else if (DECL_BIT_FIELD_TYPE (field))
{
+ gcc_assert (repr != NULL_TREE);
+
/* Zero-size bitfields finish off a representative and
do not have a representative themselves. This is
required by the C++ memory model. */
*** finish_bitfield_layout (record_layout_in
*** 1896,1901
--- 1900,1923
finish_bitfield_representative (repr, prev);
repr = NULL_TREE;
}
+
+ /* We assume that either DECL_FIELD_OFFSET of the representative
+and each bitfield member is a constant or they are equal.
+This is because we need to be able to compute the bit-offset
+of each field relative to the representative in get_bit_range
+during RTL expansion.
+If these constraints are not met, simply force a new
+representative to be generated. That will at most
+generate worse code but still maintain correctness with
+respect to the C++ memory model. */
+ if (!((host_integerp (DECL_FIELD_OFFSET (repr), 1)
+ host_integerp (DECL_FIELD_OFFSET (field), 1))
+ || operand_equal_p (DECL_FIELD_OFFSET (repr),
+ DECL_FIELD_OFFSET (field), 0)))
+ {
+ finish_bitfield_representative
Re: [C++ Patch] PR 14710 (add -Wuseless-cast)
On 03/18/2012 11:32 AM, Paolo Carlini wrote: + if ((TREE_CODE (type) == REFERENCE_TYPE + lvalue_p (expr) + same_type_p (TREE_TYPE (expr), TREE_TYPE (type))) + || same_type_p (TREE_TYPE (expr), type)) + warning (OPT_Wuseless_cast, useless cast to type %qT, type); I think instead of just lvalue_p (expr) you want TYPE_REF_IS_RVALUE (type) ? xvalue_p (expr) : real_lvalue_p (expr) where xvalue_p is a new function that just does return lvalue_kind (expr) == clk_rvalueref; Jason
Re: [C++ Patch] PR 14710 (add -Wuseless-cast)
On 03/19/2012 02:17 PM, Jason Merrill wrote:
On 03/18/2012 11:32 AM, Paolo Carlini wrote:
+ if ((TREE_CODE (type) == REFERENCE_TYPE
+ lvalue_p (expr)
+ same_type_p (TREE_TYPE (expr), TREE_TYPE (type)))
+ || same_type_p (TREE_TYPE (expr), type))
+warning (OPT_Wuseless_cast, useless cast to type %qT, type);
I think instead of just lvalue_p (expr) you want
TYPE_REF_IS_RVALUE (type) ? xvalue_p (expr) : real_lvalue_p (expr)
where xvalue_p is a new function that just does
return lvalue_kind (expr) == clk_rvalueref;
Ah, thanks. Then I tested on x86_64-linux the below.
Ok now?
Thanks again,
Paolo.
//
2012-03-19 Paolo Carlini paolo.carl...@oracle.com
PR c++/14710
* doc/invoke.texi: Document -Wuseless-cast.
/c-family
2012-03-19 Paolo Carlini paolo.carl...@oracle.com
PR c++/14710
* c.opt ([Wuseless-cast]): Add.
/cp
2012-03-19 Paolo Carlini paolo.carl...@oracle.com
PR c++/14710
* cp-tree.h (xvalue_p, maybe_warn_about_useless_cast): Declare.
* tree.c (xvalue_p): Define.
* typeck.c (maybe_warn_about_useless_cast): Define.
(build_reinterpret_cast, build_const_cast,
build_static_cast, cp_build_c_cast): Use maybe_warn_about_useless_cast.
* rtti.c (build_dynamic_cast): Likewise.
* pt.c (tsubst_copy_and_build, case CAST_EXPR): Increment/decrement
c_inhibit_evaluation_warnings before/after the build_* calls.
/testsuite
2012-03-19 Paolo Carlini paolo.carl...@oracle.com
PR c++/14710
* g++.dg/warn/Wuseless-cast.C: New.
Index: doc/invoke.texi
===
--- doc/invoke.texi (revision 185519)
+++ doc/invoke.texi (working copy)
@@ -274,8 +274,8 @@ Objective-C and Objective-C++ Dialects}.
-Wunused-label -Wunused-local-typedefs -Wunused-parameter @gol
-Wno-unused-result -Wunused-value @gol -Wunused-variable @gol
-Wunused-but-set-parameter -Wunused-but-set-variable @gol
--Wvariadic-macros -Wvector-operation-performance -Wvla
--Wvolatile-register-var -Wwrite-strings -Wzero-as-null-pointer-constant}
+-Wuseless-cast -Wvariadic-macros -Wvector-operation-performance @gol
+-Wvla -Wvolatile-register-var -Wwrite-strings -Wzero-as-null-pointer-constant}
@item C and Objective-C-only Warning Options
@gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol
@@ -4199,6 +4199,11 @@ types. @option{-Wconversion-null} is enabled by de
Warn when a literal '0' is used as null pointer constant. This can
be useful to facilitate the conversion to @code{nullptr} in C++11.
+@item -Wuseless-cast @r{(C++ and Objective-C++ only)}
+@opindex Wuseless-cast
+@opindex Wno-useless-cast
+Warn when an expression is casted to its own type.
+
@item -Wempty-body
@opindex Wempty-body
@opindex Wno-empty-body
Index: c-family/c.opt
===
--- c-family/c.opt (revision 185519)
+++ c-family/c.opt (working copy)
@@ -697,6 +697,10 @@ Wzero-as-null-pointer-constant
C++ ObjC++ Var(warn_zero_as_null_pointer_constant) Warning
Warn when a literal '0' is used as null pointer
+Wuseless-cast
+C++ ObjC++ Var(warn_useless_cast) Warning
+Warn about useless casts
+
ansi
C ObjC C++ ObjC++
A synonym for -std=c89 (for C) or -std=c++98 (for C++)
Index: testsuite/g++.dg/warn/Wuseless-cast.C
===
--- testsuite/g++.dg/warn/Wuseless-cast.C (revision 0)
+++ testsuite/g++.dg/warn/Wuseless-cast.C (revision 0)
@@ -0,0 +1,123 @@
+// { dg-options -Wuseless-cast }
+
+templatetypename T
+ void tmpl_f1(T t)
+ {
+(int)(t);
+static_castint(t);
+reinterpret_castint(t);
+
+(int*)(t);
+const_castint*(t);
+static_castint*(t);
+reinterpret_castint*(t);
+
+(int)(t);
+const_castint(t);
+static_castint(t);
+reinterpret_castint(t);
+ }
+
+templatetypename T
+ void tmpl_f2(T t)
+ {
+(int)(t);
+const_castint(t);
+static_castint(t);
+reinterpret_castint(t);
+ }
+
+struct A { };
+
+templatetypename T
+ void tmpl_f3(T t)
+ {
+(A)(t);
+static_castA(t);
+
+(A*)(t);
+const_castA*(t);
+static_castA*(t);
+reinterpret_castA*(t);
+dynamic_castA*(t);
+
+(A)(t);
+const_castA(t);
+static_castA(t);
+reinterpret_castA(t);
+dynamic_castA(t);
+ }
+
+templatetypename T
+ void tmpl_f4(T t)
+ {
+(A)(t);
+const_castA(t);
+static_castA(t);
+reinterpret_castA(t);
+dynamic_castA(t);
+ }
+
+void f()
+{
+ int n;
+
+ (int)(n);// { dg-warning useless cast }
+ static_castint(n); // { dg-warning useless cast }
+ reinterpret_castint(n);// { dg-warning useless cast }
+
+ (int*)(n); // { dg-warning useless cast }
+ const_castint*(n);// { dg-warning useless cast }
+ static_castint*(n); // { dg-warning useless cast }
+
Re: [PATCH][ARM] Improve use of conditional execution in thumb mode.
Ping. On 08/03/12 15:48, Andrew Stubbs wrote: On 17/02/12 15:30, Andrew Stubbs wrote: I've got a full test run going again. OK for 4.8, again? The test run revealed some bugs handling MINUS. This update has been tested and passes a bootstrap and test with no regressions. Indeed, it has actually corrected a failure in gcc.target/arm/combine-movs.c. OK? Andrew
Re: [PATCH, ARM, 4.6] backport PR pch/45979
On 16/03/12 01:41, Michael Hope wrote: Hi there. This patch backports my PCH on ARM EABI fix[1] for pch/PR45979 to the 4.6 branch. This fixes PCH support on ARM and tidies up the random pch testsuite failures that are seen between runs. OK for 4.6? OK. R. -- Michael [1] http://gcc.gnu.org/ml/gcc-patches/2011-05/msg00017.html gcc/ 2012-03-16 Michael Hope michael.h...@linaro.org Backport from mainline 2011-05-05 Michael Hope michael.h...@linaro.org PR pch/45979 * config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for __ARM_EABI__ hosts. diff --git a/gcc/config/host-linux.c b/gcc/config/host-linux.c index 47ce3ea..ec61055 100644 --- a/gcc/config/host-linux.c +++ b/gcc/config/host-linux.c @@ -84,6 +84,8 @@ # define TRY_EMPTY_VM_SPACE 0x6000 #elif defined(__mc68000__) # define TRY_EMPTY_VM_SPACE 0x4000 +#elif defined(__ARM_EABI__) +# define TRY_EMPTY_VM_SPACE 0x6000 #else # define TRY_EMPTY_VM_SPACE 0 #endif
Re: [PATCH][ARM] Improve use of conditional execution in thumb mode.
On 08/03/12 15:48, Andrew Stubbs wrote: On 17/02/12 15:30, Andrew Stubbs wrote: I've got a full test run going again. OK for 4.8, again? The test run revealed some bugs handling MINUS. This update has been tested and passes a bootstrap and test with no regressions. Indeed, it has actually corrected a failure in gcc.target/arm/combine-movs.c. OK? OK. R.
Re: [C++ Patch] PR 14710 (add -Wuseless-cast)
OK. Jason
Re: [patch] Minor tweaks
Ok. I think volatilep should be always set as well. Thanks. No strong opinion, but at least one caller (fold_truthop through decode_field_reference) calls the function 4 times in a row and only checks volatilep at the end to disable the transformation. -- Eric Botcazou
[PATCH][RFC] Merge 'expand' and 'rtl_eh'
We have the unfortunate situation that expand may leave us with
unreachable blocks that are required by proper rtl_eh functioning
(unreachable landing-pads, that is). This is bad for any verification
pass the pass manager may want to call that requires dominators to
be computed (I'm thinking of verifying loop structures, which I really
want to do after expand as I am trying to preserve loop structures
from tree loop optimization until after RTL loop optimization).
This limitation has been introduced with the introduction of
rtl_eh - and is, IMHO, bad as it exposed a partly broken IL state
to the passmanager.
Thus the following patch makes sure we can leave cfgexpand with
no unreachable blocks around and simply merges the rtl_eh pass
and expand.
Yes, we do have several tests in the testsuite where EH landing
pads get unreachable during expansion, by a disconnect of what
GIMPLE thinks can throw and what the expanded code sequence says
(bogus SSE builtin definitions in the x86_64 backend for example,
see g++.dg/other/i386-1.C for two cases).
Bootstrap and regtest on x86_64-unknown-linux-gnu running.
Comments?
Thanks,
Richard.
2012-03-19 Richard Guenther rguent...@suse.de
* tree-pass.h (pass_rtl_eh): Remove.
* except.c (gate_handle_eh): Likewise.
(rest_of_handle_eh): Likewise.
(pass_rtl_eh): Likewise.
(finish_eh_generation): Export.
* except.h (finish_eh_generation): Declare.
* passes.c (init_optimization_passes): Remove pass_rtl_eh.
* cfgexpand.c (gimple_expand_cfg): Call finish_eh_generation
after expanding stack alignment. Instead of compacting blocks
call cleanup_cfg.
Index: gcc/tree-pass.h
===
--- gcc/tree-pass.h.orig2012-03-19 16:29:36.0 +0100
+++ gcc/tree-pass.h 2012-03-19 16:28:03.0 +0100
@@ -488,7 +488,6 @@ extern struct gimple_opt_pass pass_fixup
extern struct rtl_opt_pass pass_expand;
extern struct rtl_opt_pass pass_init_function;
extern struct rtl_opt_pass pass_jump;
-extern struct rtl_opt_pass pass_rtl_eh;
extern struct rtl_opt_pass pass_initial_value_sets;
extern struct rtl_opt_pass pass_unshare_all_rtl;
extern struct rtl_opt_pass pass_instantiate_virtual_regs;
Index: gcc/except.c
===
--- gcc/except.c.orig 2012-03-19 16:29:36.0 +0100
+++ gcc/except.c2012-03-19 16:29:06.0 +0100
@@ -81,7 +81,7 @@ along with GCC; see the file COPYING3.
gimple to eh_region mapping that had been recorded in the
THROW_STMT_TABLE.
- During pass_rtl_eh (except.c), we generate the real landing pads
+ Then, via finish_eh_generation, we generate the real landing pads
to which the runtime will actually transfer control. These new
landing pads perform whatever bookkeeping is needed by the target
backend in order to resume execution within the current function.
@@ -1414,7 +1414,7 @@ sjlj_build_landing_pads (void)
/* After initial rtl generation, call back to finish generating
exception support code. */
-static void
+void
finish_eh_generation (void)
{
basic_block bb;
@@ -1461,41 +1461,6 @@ finish_eh_generation (void)
}
}
}
-
-static bool
-gate_handle_eh (void)
-{
- /* Nothing to do if no regions created. */
- return cfun-eh-region_tree != NULL;
-}
-
-/* Complete generation of exception handling code. */
-static unsigned int
-rest_of_handle_eh (void)
-{
- finish_eh_generation ();
- cleanup_cfg (CLEANUP_NO_INSN_DEL);
- return 0;
-}
-
-struct rtl_opt_pass pass_rtl_eh =
-{
- {
- RTL_PASS,
- rtl_eh, /* name */
- gate_handle_eh, /* gate */
- rest_of_handle_eh, /* execute */
- NULL, /* sub */
- NULL, /* next */
- 0,/* static_pass_number */
- TV_JUMP, /* tv_id */
- 0,/* properties_required */
- 0,/* properties_provided */
- 0,/* properties_destroyed */
- 0,/* todo_flags_start */
- 0 /* todo_flags_finish */
- }
-};
/* This section handles removing dead code for flow. */
Index: gcc/except.h
===
--- gcc/except.h.orig 2011-07-25 10:50:26.0 +0200
+++ gcc/except.h2012-03-19 16:24:58.0 +0100
@@ -291,6 +291,8 @@ extern void assign_filter_values (void);
extern eh_region get_eh_region_from_rtx (const_rtx);
extern eh_landing_pad get_eh_landing_pad_from_rtx (const_rtx);
+extern void finish_eh_generation (void);
+
struct GTY(()) throw_stmt_node {
gimple stmt;
int lp_nr;
Index: gcc/passes.c
Re: [Patch]: Uncouple size_t and sizetype
On Mar 19, 2012, at 1:36 PM, Richard Guenther wrote:
On Mon, Mar 19, 2012 at 1:02 PM, Tristan Gingold ging...@adacore.com wrote:
On Mar 16, 2012, at 12:38 PM, Richard Guenther wrote:
[…]
Well, this setup is not well supported by the middle-end (and indeed m32c
has existing issues with that). So in your case decoupling sizetype from
size_t sounds like the more appropriate solution.
Btw, while we are transitioning to target hooks in this case I'd prefer
a target macro alongside the existing SIZE_TYPE, etc. ones.
Ok.
I'd choose SIZETYPE (for confusion, heh), defaulting to SIZE_TYPE.
Richard.
Hi,
here is the patch. As SIZETYPE was already used as a size_type_kind
enumeration constant, I made a little renaming work.
Bootstrapped, no regressions on x86_64-darwin. Tested on ia64-hp-openvms.
Ok for trunk ?
Ok with a minor nit - can you make STK_* lower-case now, similar to
itk_ and ti_? They are not macros after all.
Sure. Here is what I will commit (I have just checked that the compiler still
bootstrap).
Thank you for the review and the discussion.
Tristan.
2012-03-19 Tristan Gingold ging...@adacore.com
* tree.h (enum size_type_kind): Add stk_ prefix to constants,
convert in lowercase.
(sizetype_tab, sizetype, bitsizetype, ssizetype, sbitsizetype)
(size_int, ssize_int, bitsize_int, sbitsize_int): Adjust.
* stor-layout.c (sizetype_tab): Adjust.
(initialize_sizetypes): Use SIZETYPE instead of SIZE_TYPE.
* tree-streamer.c (preload_common_nodes): Use stk_type_kind_last
instead of type_kind_last.
* tree-scalar-evolution.c (interpret_rhs_expr): Use size_int
instead of size_int_kind.
* doc/tm.texi.in (Type Layout): Document SIZETYPE.
* doc/tm.texi: Regenerate.
* defaults.h (SIZETYPE): Provide a default value.
* config/vms/vms.h (SIZE_TYPE): Define as unsigned int.
(SIZETYPE): Define.
diff --git a/gcc/config/vms/vms.h b/gcc/config/vms/vms.h
index f2bc354..47028c8 100644
--- a/gcc/config/vms/vms.h
+++ b/gcc/config/vms/vms.h
@@ -60,15 +60,18 @@ extern void vms_c_register_includes (const char *, const
char *, int);
#define POINTER_SIZE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? 32 : 64)
#define POINTERS_EXTEND_UNSIGNED 0
-/* FIXME: It should always be a 32 bit type. */
+/* Always a 32 bit type. */
#undef SIZE_TYPE
-#define SIZE_TYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
- unsigned int : long long unsigned int)
+#define SIZE_TYPE unsigned int
+
/* ???: Defined as a 'int' by dec-c, but obstack.h doesn't like it. */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
int : long long int)
+#define SIZETYPE (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ? \
+ unsigned int : long long unsigned int)
+
#define C_COMMON_OVERRIDE_OPTIONS vms_c_common_override_options ()
/* VMS doesn't support other sections than .text for code. */
diff --git a/gcc/defaults.h b/gcc/defaults.h
index 1780dda..296bb6a 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -582,6 +582,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively.
If not, see
#define SIZE_TYPE long unsigned int
#endif
+#ifndef SIZETYPE
+#define SIZETYPE SIZE_TYPE
+#endif
+
#ifndef PID_TYPE
#define PID_TYPE int
#endif
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 69f8aba..2891bb6 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -1642,6 +1642,18 @@ If you don't define this macro, the default is
@code{long unsigned
int}.
@end defmac
+@defmac SIZETYPE
+GCC defines internal types (@code{sizetype}, @code{ssizetype},
+@code{bitsizetype} and @code{sbitsizetype}) for expressions
+dealing with size. This macro is a C expression for a string describing
+the name of the data type from which the precision of @code{sizetype}
+is extracted.
+
+The string has the same restrictions as @code{SIZE_TYPE} string.
+
+If you don't define this macro, the default is @code{SIZE_TYPE}.
+@end defmac
+
@defmac PTRDIFF_TYPE
A C expression for a string describing the name of the data type to use
for the result of subtracting two pointers. The typedef name
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index c24cf1e..a222654 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -1630,6 +1630,18 @@ If you don't define this macro, the default is
@code{long unsigned
int}.
@end defmac
+@defmac SIZETYPE
+GCC defines internal types (@code{sizetype}, @code{ssizetype},
+@code{bitsizetype} and @code{sbitsizetype}) for expressions
+dealing with size. This macro is a C expression for a string describing
+the name of the data type from which the precision of @code{sizetype}
+is extracted.
+
+The string has the same restrictions as @code{SIZE_TYPE} string.
+
+If you don't define this macro, the default is @code{SIZE_TYPE}.
+@end defmac
+
@defmac PTRDIFF_TYPE
A
Re: PATCH: Properly generate X32 IE sequence
On Sun, Mar 18, 2012 at 1:55 PM, Uros Bizjak ubiz...@gmail.com wrote:
On Sun, Mar 18, 2012 at 5:01 PM, Uros Bizjak ubiz...@gmail.com wrote:
I am testing this patch. OK for trunk if it passes all tests?
No, force_reg will generate a pseudo, so this conversion is valid only
for !can_create_pseudo ().
At least for *tls_initial_exec_x32_store, you will need a temporary to
split the pattern after reload.
Here is the updated patch to add can_create_pseudo. I also changed
tls_initial_exec_x32 to take an input register operand as thread pointer.
Please try attached patch. It simply throws away all recent
complications w.r.t. to thread pointer and always handles TP in
DImode.
The testcase:
--cut here--
__thread int foo __attribute__ ((tls_model (initial-exec)));
void bar (int x)
{
foo = x;
}
int baz (void)
{
return foo;
}
--cut here--
Now compiles to:
bar:
movq foo@gottpoff(%rip), %rax
movl %edi, %fs:(%rax)
ret
baz:
movq foo@gottpoff(%rip), %rax
movl %fs:(%rax), %eax
ret
In effect, this always generates %fs(%rDI) and emits REX prefix before
mov/add to satisfy brain-dead linkers.
The patch is bootstrapping now on x86_64-pc-linux-gnu.
For
--
extern __thread char c;
extern char y;
void
ie (void)
{
y = c;
}
--
Your patch generates:
movl%fs:0, %eax
movqc@gottpoff(%rip), %rdx
movzbl (%rax,%rdx), %edx
movb%dl, y(%rip)
ret
It can be optimized to:
movqc@gottpoff(%rip), %rax
movzbl %fs:(%rax), %eax
movb%al, y(%rip)
ret
H.J.
2012-03-19 H.J. Lu hongjiu...@intel.com
* config/i386/i386-protos.h (ix86_split_tls_initial_exec_x32): New.
* config/i386/i386.c (legitimize_tls_address): Also pass thread
pointer to gen_tls_initial_exec_x32.
(ix86_split_tls_initial_exec_x32): New.
* config/i386/i386.md (*load_tp_x32): Renamed to ...
(*load_tp_x32_mode): This. Replace SI with SWI48x.
(tls_initial_exec_x32): Add an input register operand as thread
pointer. Generate a REX prefix if needed.
(*tls_initial_exec_x32_load): New.
(*tls_initial_exec_x32_store): Likewise.
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index 630112f..528eeaa 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -142,6 +142,7 @@ extern void ix86_split_lshr (rtx *, rtx, enum machine_mode);
extern rtx ix86_find_base_term (rtx);
extern bool ix86_check_movabs (rtx, int);
extern void ix86_split_idivmod (enum machine_mode, rtx[], bool);
+extern void ix86_split_tls_initial_exec_x32 (rtx [], enum machine_mode, bool);
extern rtx assign_386_stack_local (enum machine_mode, enum ix86_stack_slot);
extern int ix86_attr_length_immediate_default (rtx, bool);
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 78a366e..fb802ee 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -12671,13 +12671,14 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
}
else if (Pmode == SImode)
{
- /* Always generate
- movl %fs:0, %reg32
+ /* Always generate a REX prefix for
addl xgottpoff(%rip), %reg32
- to support linker IE-LE optimization and avoid
- fs:(%reg32) as memory operand. */
+ to support linker IE-LE optimization. */
dest = gen_reg_rtx (Pmode);
- emit_insn (gen_tls_initial_exec_x32 (dest, x));
+ base = get_thread_pointer (for_mov
+ || !(TARGET_TLS_DIRECT_SEG_REFS
+ TARGET_TLS_INDIRECT_SEG_REFS));
+ emit_insn (gen_tls_initial_exec_x32 (dest, base, x));
return dest;
}
@@ -12754,6 +12755,28 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
return dest;
}
+/* Split x32 TLS IE access in MODE. Split load if LOAD is TRUE,
+ otherwise split store. */
+
+void
+ix86_split_tls_initial_exec_x32 (rtx operands[],
+ enum machine_mode mode, bool load)
+{
+ rtx base, mem;
+ rtx off = load ? operands[1] : operands[0];
+ off = gen_rtx_UNSPEC (DImode, gen_rtvec (1, off), UNSPEC_GOTNTPOFF);
+ off = gen_rtx_CONST (DImode, off);
+ off = gen_const_mem (DImode, off);
+ set_mem_alias_set (off, ix86_GOT_alias_set ());
+ base = gen_rtx_UNSPEC (DImode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
+ off = gen_rtx_PLUS (DImode, base, force_reg (DImode, off));
+ mem = gen_rtx_MEM (mode, off);
+ if (load)
+emit_move_insn (operands[0], mem);
+ else
+emit_move_insn (mem, operands[1]);
+}
+
/* Create or return the unique __imp_DECL dllimport symbol corresponding
to symbol DECL. */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index eae26ae..1643792 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -12747,11 +12747,11 @@
(define_mode_attr tp_seg [(SI gs) (DI fs)])
;; Load and add the thread base pointer from %tp_seg:0.
-(define_insn *load_tp_x32
- [(set
Re: [PATCH][RFC] Merge 'expand' and 'rtl_eh'
We have the unfortunate situation that expand may leave us with unreachable blocks that are required by proper rtl_eh functioning (unreachable landing-pads, that is). This is bad for any verification pass the pass manager may want to call that requires dominators to be computed (I'm thinking of verifying loop structures, which I really want to do after expand as I am trying to preserve loop structures from tree loop optimization until after RTL loop optimization). This limitation has been introduced with the introduction of rtl_eh - and is, IMHO, bad as it exposed a partly broken IL state to the passmanager. Thus the following patch makes sure we can leave cfgexpand with no unreachable blocks around and simply merges the rtl_eh pass and expand. Yes, we do have several tests in the testsuite where EH landing pads get unreachable during expansion, by a disconnect of what GIMPLE thinks can throw and what the expanded code sequence says (bogus SSE builtin definitions in the x86_64 backend for example, see g++.dg/other/i386-1.C for two cases). Those cases are in fact mostly broken. When gimple thinks somehting throws and it does not, it is a missed optimization. Especially the SSE intrincisc not having NOTHROW. We should have at least tracking PR for them. Bootstrap and regtest on x86_64-unknown-linux-gnu running. Comments? This seems OK to me... NEXT_PASS (pass_init_function); NEXT_PASS (pass_jump); - NEXT_PASS (pass_rtl_eh); NEXT_PASS (pass_initial_value_sets); NEXT_PASS (pass_unshare_all_rtl); IL is deeply irregular until this step, since RTL sharing is nothing any of other passes are designed to handle and it does not match what rtl.texi says. I would suggest merging all those into cfgexpand, not just rtl_eh. Honza
Re: [PATCH][RFC] Merge 'expand' and 'rtl_eh'
On Mon, 19 Mar 2012, Jan Hubicka wrote: We have the unfortunate situation that expand may leave us with unreachable blocks that are required by proper rtl_eh functioning (unreachable landing-pads, that is). This is bad for any verification pass the pass manager may want to call that requires dominators to be computed (I'm thinking of verifying loop structures, which I really want to do after expand as I am trying to preserve loop structures from tree loop optimization until after RTL loop optimization). This limitation has been introduced with the introduction of rtl_eh - and is, IMHO, bad as it exposed a partly broken IL state to the passmanager. Thus the following patch makes sure we can leave cfgexpand with no unreachable blocks around and simply merges the rtl_eh pass and expand. Yes, we do have several tests in the testsuite where EH landing pads get unreachable during expansion, by a disconnect of what GIMPLE thinks can throw and what the expanded code sequence says (bogus SSE builtin definitions in the x86_64 backend for example, see g++.dg/other/i386-1.C for two cases). Those cases are in fact mostly broken. When gimple thinks somehting throws and it does not, it is a missed optimization. Especially the SSE intrincisc not having NOTHROW. We should have at least tracking PR for them. Bootstrap and regtest on x86_64-unknown-linux-gnu running. Comments? This seems OK to me... NEXT_PASS (pass_init_function); NEXT_PASS (pass_jump); - NEXT_PASS (pass_rtl_eh); NEXT_PASS (pass_initial_value_sets); NEXT_PASS (pass_unshare_all_rtl); IL is deeply irregular until this step, since RTL sharing is nothing any of other passes are designed to handle and it does not match what rtl.texi says. I would suggest merging all those into cfgexpand, not just rtl_eh. Ok. If the posted patch passes bootstrap regtest I'll see what I can do. Richard.
Re: RFC: PATCH: Add -maddress-mode=short|long for x86
On Sun, Mar 18, 2012 at 3:17 PM, Gerald Pfeifer ger...@pfeifer.com wrote: On Wed, 14 Mar 2012, H.J. Lu wrote: Apart from the above, at least invoke.texi does not define what an x32 environment is. Shouldn't that done somewhere (before this terminology is used)? I am not sure where to put it. In any case, here is a patch to update GCC 4.7.0 changes with link to x32 website. Please add two thes, once for the ABI and once for the options; fine with this change. Done. Thanks. -- H.J.
Re: [PATCH][RFC] Merge 'expand' and 'rtl_eh'
On Mon, Mar 19, 2012 at 4:41 PM, Richard Guenther rguent...@suse.de wrote: Comments? What does rtl_eh do for no-SJLJ exceptions? Have you tested with SJLJ exceptions? (Can/should we move that code to GIMPLE?) Ciao! Steven
Re: [PATCH] eh_personality.cc: unwinding on ARM
On 16/03/12 13:29, EXTERNAL Waechtler Peter (Fa. TCP, CM-AI/PJ-CF31) wrote:
The CodeSourcery toolchain contains a fix like the following,
please consider for adding it.
Here's the full original patch with ChangeLog.
I don't know why Dan never submitted this one. Perhaps it's not suitable
for upstream or not considered the correct fix?
Anyway, as far as copyright goes, I don't believe CodeSourcery has any
problem with this being committed.
Andrew
2010-02-04 Daniel Jacobowitz d...@codesourcery.com
libstdc++-v3/
* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): For
ARM EABI, skip handlers for _US_VIRTUAL_UNWIND_FRAME
| _US_FORCE_UNWIND.
--- libstdc++-v3/libsupc++/eh_personality.cc
+++ libstdc++-v3/libsupc++/eh_personality.cc
@@ -384,6 +384,8 @@
switch (state _US_ACTION_MASK)
{
case _US_VIRTUAL_UNWIND_FRAME:
+ if (state _US_FORCE_UNWIND)
+ CONTINUE_UNWINDING;
actions = _UA_SEARCH_PHASE;
break;
Re: RFA: consolidate DWARF strings into libiberty
But given the pushback for even one new library, I think we're unnecessarily slowing ourselves down. I'm not opposed to libiberty becoming the kitchen sink, if that's what people want. If it does go that route, my reason for being a libiberty maintainer no longer applies, and others who are more kitchen-sink-minded should take over. The only drawback to adding toplevel libraries is coordinating changes among the toplevel configury.
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 8:54 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Mon, Mar 19, 2012 at 8:51 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Sun, Mar 18, 2012 at 1:55 PM, Uros Bizjak ubiz...@gmail.com wrote:
On Sun, Mar 18, 2012 at 5:01 PM, Uros Bizjak ubiz...@gmail.com wrote:
I am testing this patch. OK for trunk if it passes all tests?
No, force_reg will generate a pseudo, so this conversion is valid only
for !can_create_pseudo ().
At least for *tls_initial_exec_x32_store, you will need a temporary to
split the pattern after reload.
Here is the updated patch to add can_create_pseudo. I also changed
tls_initial_exec_x32 to take an input register operand as thread pointer.
Please try attached patch. It simply throws away all recent
complications w.r.t. to thread pointer and always handles TP in
DImode.
The testcase:
--cut here--
__thread int foo __attribute__ ((tls_model (initial-exec)));
void bar (int x)
{
foo = x;
}
int baz (void)
{
return foo;
}
--cut here--
Now compiles to:
bar:
movq foo@gottpoff(%rip), %rax
movl %edi, %fs:(%rax)
ret
baz:
movq foo@gottpoff(%rip), %rax
movl %fs:(%rax), %eax
ret
In effect, this always generates %fs(%rDI) and emits REX prefix before
mov/add to satisfy brain-dead linkers.
The patch is bootstrapping now on x86_64-pc-linux-gnu.
For
--
extern __thread char c;
extern char y;
void
ie (void)
{
y = c;
}
--
Your patch generates:
movl %fs:0, %eax
movq c@gottpoff(%rip), %rdx
movzbl (%rax,%rdx), %edx
movb %dl, y(%rip)
ret
It can be optimized to:
movq c@gottpoff(%rip), %rax
movzbl %fs:(%rax), %eax
movb %al, y(%rip)
ret
Combine failed:
(set (reg:QI 63 [ c ])
(mem/c:QI (plus:DI (zero_extend:DI (unspec:SI [
(const_int 0 [0])
] UNSPEC_TP))
(mem/u/c:DI (const:DI (unspec:DI [
(symbol_ref:SI (c) [flags 0x60]
var_decl 0x719b8140 c)
] UNSPEC_GOTNTPOFF)) [2 S8 A8])) [0 c+0 S1 A8]))
Wrong testcase. IT should be
--
extern __thread char c;
extern __thread short w;
extern char y;
extern short i;
void
ie (void)
{
y = c;
i = w;
}
---
I got
movl%fs:0, %eax
movqc@gottpoff(%rip), %rdx
movzbl (%rax,%rdx), %edx
movb%dl, y(%rip)
movqw@gottpoff(%rip), %rdx
movzwl (%rax,%rdx), %eax
movw%ax, i(%rip)
ret
It can be
movqc@gottpoff(%rip), %rax
movzbl %fs:(%rax), %eax
movb%al, y(%rip)
movqw@gottpoff(%rip), %rax
movzwl %fs:(%rax), %eax
movw%ax, i(%rip)
ret
--
H.J.
[Ada] Allocation of unconstrained limited type
This patch adds code to detect a particular form of expansion produced by the build-in-place machinery for the allocation of a private limited indefinite type where the full view lacks discriminants. The allocator appears as a qualified expression containing a build-in-place call. The patch prevents the generation of spurious error messages related to missing initialization during allocation. -- Source -- -- types.ads package Types is type Simple_Rec is limited private; type Fake_Indefinite_Rec () is limited private; type Indefinite_Rec () is limited private; function Make return Simple_Rec; function Make return Fake_Indefinite_Rec; function Make return Indefinite_Rec; procedure Print_Data (Obj : Simple_Rec); procedure Print_Data (Obj : Fake_Indefinite_Rec); procedure Print_Data (Obj : Indefinite_Rec); private type Simple_Rec is limited record Data : Integer; end record; type Fake_Indefinite_Rec is limited record Data : Integer; end record; type Indefinite_Rec (Discr : Integer) is limited record Data : Integer; end record; end Types; -- types.adb with Ada.Text_IO; use Ada.Text_IO; package body Types is function Make return Simple_Rec is begin return Result : Simple_Rec := Simple_Rec'(Data = 1); end Make; function Make return Fake_Indefinite_Rec is begin return Result : Fake_Indefinite_Rec := Fake_Indefinite_Rec'(Data = 2); end Make; function Make return Indefinite_Rec is begin return Result : Indefinite_Rec := Indefinite_Rec'(Discr = 3, Data = 4); end Make; procedure Print_Data (Obj : Simple_Rec) is begin Put_Line (Obj.Data'Img); end Print_Data; procedure Print_Data (Obj : Fake_Indefinite_Rec) is begin Put_Line (Obj.Data'Img); end Print_Data; procedure Print_Data (Obj : Indefinite_Rec) is begin Put_Line (Obj.Data'Img); end Print_Data; end Types; -- main.adb with Types; use Types; procedure Main is type Simple_Rec_Ptr is access all Simple_Rec; type Fake_Indefinite_Rec_Ptr is access all Fake_Indefinite_Rec; type Indefinite_Rec_Ptr is access all Indefinite_Rec; Obj1 : Simple_Rec_Ptr := new Simple_Rec'(Make); Obj2 : Fake_Indefinite_Rec_Ptr := new Fake_Indefinite_Rec'(Make); Obj3 : Indefinite_Rec_Ptr := new Indefinite_Rec'(Make); begin Print_Data (Obj1.all); Print_Data (Obj2.all); Print_Data (Obj3.all); end Main; - -- Compilation and expected output -- - $ gnatmake -q -gnat05 main.adb $ ./main $ 1 $ 2 $ 4 Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Hristian Kirtchev kirtc...@adacore.com * sem_ch4.adb (Analyze_Allocator): Detect an allocator generated by the build-in-place machinery where the designated type is indefinite, but the underlying type is not. Do not emit errors related to missing initialization in this case. Index: sem_ch4.adb === --- sem_ch4.adb (revision 185520) +++ sem_ch4.adb (working copy) @@ -661,9 +661,22 @@ if Is_Indefinite_Subtype (Type_Id) and then Serious_Errors_Detected = Sav_Errs then - if Is_Class_Wide_Type (Type_Id) then + -- The build-in-place machinery may produce an allocator when + -- the designated type is indefinite but the underlying type is + -- not. In this case the unknown discriminants are meaningless + -- and should not trigger error messages. Check the parent node + -- because the allocator is marked as coming from source. + + if Present (Underlying_Type (Type_Id)) + and then not Is_Indefinite_Subtype (Underlying_Type (Type_Id)) + and then not Comes_From_Source (Parent (N)) + then + null; + + elsif Is_Class_Wide_Type (Type_Id) then Error_Msg_N (initialization required in class-wide allocation, N); + else if Ada_Version Ada_2005 and then Is_Limited_Type (Type_Id)
[Ada] Missing debug info for object of class-wide interface type
For an object of a class-wide interface type, the object declaration is rewritten as a renaming with a new entity, and debug info was not being generated for the renaming, preventing printing of the object's value in gdb. The entity of the renaming is now marked as needing debug info. Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Gary Dismukes dismu...@adacore.com * exp_ch3.adb (Expand_N_Object_Declaration): In the case of an object of a class-wide interface type, where the declaration is rewritten as a renaming, call Set_Debug_Info_Needed on the renaming entity so that Materialize_Entity will be set. Also, change existing call (for other than interface cases) to call Set_Debug_Info_Needed rather than Set_Needs_Debug_Info (as specified for that flag). Index: exp_ch3.adb === --- exp_ch3.adb (revision 185520) +++ exp_ch3.adb (working copy) @@ -4820,6 +4820,17 @@ Subtype_Mark= New_Occurrence_Of (Typ, Loc), Name = Convert_Tag_To_Interface (Typ, Tag_Comp))); + -- If the original entity comes from source, then mark the + -- new entity as needing debug information, even though it's + -- defined by a generated renaming that does not come from + -- source, so that Materialize_Entity will be set on the + -- entity when Debug_Renaming_Declaration is called during + -- analysis. + + if Comes_From_Source (Def_Id) then + Set_Debug_Info_Needed (Defining_Identifier (N)); + end if; + Analyze (N, Suppress = All_Checks); -- Replace internal identifier of rewritten node by the @@ -5065,7 +5076,7 @@ -- renaming that does not come from source. if Comes_From_Source (Defining_Identifier (N)) then - Set_Needs_Debug_Info (Defining_Identifier (N)); + Set_Debug_Info_Needed (Defining_Identifier (N)); end if; -- Now call the routine to generate debug info for the renaming
[Ada] Remove spurious warning with -gnatw.t on trivial postconditions
It may be useful to have trivial postconditions of True or False on some subprograms. The first is essentially a confirming postcondition, while the second indicates that a procedure will not return (if postconditions are checked). Do not emit warnings on such postconditions. Similarly for Ensures components of contract-cases. GNAT does not issue warnings on the following code: $ gcc -c -gnatc -gnat12 -gnatw.t p.ads 1. package P is 2.function Func return Boolean with 3. Post = True, 4. Contract_Case = (Name= all, 5.Mode= Nominal, 6.Ensures = True); 7.procedure Proc with 8. Post = False, 9. Contract_Case = (Name= all, 10.Mode= Nominal, 11.Ensures = False); 12. end P; Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Yannick Moy m...@adacore.com * sem_ch6.adb (Check_Subprogram_Contract): Do not emit warnings on trivially True or False postconditions and Ensures components of contract-cases. Index: sem_ch6.adb === --- sem_ch6.adb (revision 185520) +++ sem_ch6.adb (working copy) @@ -6927,23 +6927,29 @@ -- Inherited_Subprograms (Spec_Id); ---- List of subprograms inherited by this subprogram + -- We ignore postconditions True or False and contract-cases which + -- have similar Ensures components, which we call trivial, when + -- issuing warnings, since these postconditions and contract-cases + -- purposedly ignore the post-state. + Last_Postcondition : Node_Id := Empty; - -- Last postcondition on the subprogram, or else Empty if either no - -- postcondition or only inherited postconditions. + -- Last non-trivial postcondition on the subprogram, or else Empty if + -- either no non-trivial postcondition or only inherited postconditions. Last_Contract_Case : Node_Id := Empty; - -- Last contract-case on the subprogram, or else Empty + -- Last non-trivial contract-case on the subprogram, or else Empty Attribute_Result_Mentioned : Boolean := False; - -- Whether attribute 'Result is mentioned in a postcondition + -- Whether attribute 'Result is mentioned in a non-trivial postcondition + -- or contract-case. No_Warning_On_Some_Postcondition : Boolean := False; - -- Whether there exists a postcondition or a contract-case without a - -- corresponding warning. + -- Whether there exists a non-trivial postcondition or contract-case + -- without a corresponding warning. Post_State_Mentioned : Boolean := False; - -- Whether some expression mentioned in a postcondition can have a - -- different value in the post-state than in the pre-state. + -- Whether some expression mentioned in a postcondition or contract-case + -- can have a different value in the post-state than in the pre-state. function Check_Attr_Result (N : Node_Id) return Traverse_Result; -- Check if N is a reference to the attribute 'Result, and if so set @@ -6956,6 +6962,9 @@ -- reference to attribute 'Old, in order to ignore its prefix, which -- is precisely evaluated in the pre-state. Otherwise return OK. + function Is_Trivial_Post_Or_Ensures (N : Node_Id) return Boolean; + -- Return whether node N is trivially True or False + procedure Process_Contract_Cases (Spec : Node_Id); -- This processes the Spec_CTC_List from Spec, processing any contract -- case from the list. The caller has checked that Spec_CTC_List is @@ -7046,13 +7055,26 @@ end if; end Check_Post_State; + + -- Is_Trivial_Post_Or_Ensures -- + + + function Is_Trivial_Post_Or_Ensures (N : Node_Id) return Boolean is + begin + return Is_Entity_Name (N) + and then (Entity (N) = Standard_True + or else + Entity (N) = Standard_False); + end Is_Trivial_Post_Or_Ensures; + -- Process_Contract_Cases -- procedure Process_Contract_Cases (Spec : Node_Id) is - Prag: Node_Id; - Arg : Node_Id; + Prag : Node_Id; + Arg : Node_Id; + Ignored : Traverse_Final_Result; pragma Unreferenced (Ignored); @@ -7063,8 +7085,12 @@ Arg := Get_Ensures_From_CTC_Pragma (Prag); -if Pragma_Name (Prag) = Name_Contract_Case then +-- Ignore trivial contract-case when Ensures component is True +-- or False. +if Pragma_Name (Prag) = Name_Contract_Case + and then not
Re: [PATCH] allowing fwprop to propagate subregs
Il 19/03/2012 17:07, Ulrich Weigand ha scritto: Hello, now that the apply_distributive_law change is in, I'd like to pick up Richard's original patch, see discussion here: http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00852.html The version below integrates all requests for changes that were raised. It's been part of Linaro GCC releases in this form for a while with no problem reported. We see performance improvements in several libav loops, as described in Richard's original mail. We've seen no test case so far where this patch (against current baseline) has shown any significant performance regressions. Re-tested on arm-linux-gnueabi and i386-linux-gnu with no regressions. OK for mainline? Bye, Ulrich ChangeLog: * fwprop.c (propagate_rtx): Also set PR_CAN_APPEAR for subregs. === modified file 'gcc/fwprop.c' --- gcc/fwprop.c 2011-12-19 22:05:28 + +++ gcc/fwprop.c 2012-02-22 11:57:19 + @@ -664,7 +664,12 @@ return NULL_RTX; flags = 0; - if (REG_P (new_rtx) || CONSTANT_P (new_rtx)) + if (REG_P (new_rtx) + || CONSTANT_P (new_rtx) + || (GET_CODE (new_rtx) == SUBREG +REG_P (SUBREG_REG (new_rtx)) +(GET_MODE_SIZE (mode) + = GET_MODE_SIZE (GET_MODE (SUBREG_REG (new_rtx)) flags |= PR_CAN_APPEAR; if (!for_each_rtx (new_rtx, varying_mem_p, NULL)) flags |= PR_HANDLE_MEM; I cannot approve it, but it looks good. Paolo
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 9:19 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Mon, Mar 19, 2012 at 8:54 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Mon, Mar 19, 2012 at 8:51 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Sun, Mar 18, 2012 at 1:55 PM, Uros Bizjak ubiz...@gmail.com wrote:
On Sun, Mar 18, 2012 at 5:01 PM, Uros Bizjak ubiz...@gmail.com wrote:
I am testing this patch. OK for trunk if it passes all tests?
No, force_reg will generate a pseudo, so this conversion is valid only
for !can_create_pseudo ().
At least for *tls_initial_exec_x32_store, you will need a temporary to
split the pattern after reload.
Here is the updated patch to add can_create_pseudo. I also changed
tls_initial_exec_x32 to take an input register operand as thread pointer.
Please try attached patch. It simply throws away all recent
complications w.r.t. to thread pointer and always handles TP in
DImode.
The testcase:
--cut here--
__thread int foo __attribute__ ((tls_model (initial-exec)));
void bar (int x)
{
foo = x;
}
int baz (void)
{
return foo;
}
--cut here--
Now compiles to:
bar:
movq foo@gottpoff(%rip), %rax
movl %edi, %fs:(%rax)
ret
baz:
movq foo@gottpoff(%rip), %rax
movl %fs:(%rax), %eax
ret
In effect, this always generates %fs(%rDI) and emits REX prefix before
mov/add to satisfy brain-dead linkers.
The patch is bootstrapping now on x86_64-pc-linux-gnu.
For
--
extern __thread char c;
extern char y;
void
ie (void)
{
y = c;
}
--
Your patch generates:
movl %fs:0, %eax
movq c@gottpoff(%rip), %rdx
movzbl (%rax,%rdx), %edx
movb %dl, y(%rip)
ret
It can be optimized to:
movq c@gottpoff(%rip), %rax
movzbl %fs:(%rax), %eax
movb %al, y(%rip)
ret
Combine failed:
(set (reg:QI 63 [ c ])
(mem/c:QI (plus:DI (zero_extend:DI (unspec:SI [
(const_int 0 [0])
] UNSPEC_TP))
(mem/u/c:DI (const:DI (unspec:DI [
(symbol_ref:SI (c) [flags 0x60]
var_decl 0x719b8140 c)
] UNSPEC_GOTNTPOFF)) [2 S8 A8])) [0 c+0 S1 A8]))
Wrong testcase. IT should be
--
extern __thread char c;
extern __thread short w;
extern char y;
extern short i;
void
ie (void)
{
y = c;
i = w;
}
---
I got
movl %fs:0, %eax
movq c@gottpoff(%rip), %rdx
movzbl (%rax,%rdx), %edx
movb %dl, y(%rip)
movq w@gottpoff(%rip), %rdx
movzwl (%rax,%rdx), %eax
movw %ax, i(%rip)
ret
It can be
movq c@gottpoff(%rip), %rax
movzbl %fs:(%rax), %eax
movb %al, y(%rip)
movq w@gottpoff(%rip), %rax
movzwl %fs:(%rax), %eax
movw %ax, i(%rip)
ret
How about this patch? I changed 32 TP load to
(define_insn *load_tp_x32_mode
[(set (match_operand:SWI48x 0 register_operand =r)
(unspec:SWI48x [(const_int 0)] UNSPEC_TP))]
TARGET_X32
mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}
[(set_attr type imov)
(set_attr modrm 0)
(set_attr length 7)
(set_attr memory load)
(set_attr imm_disp false)])
and removed *load_tp_x32_zext.
--
H.J.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 9aa5ee7..66221e4 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -12483,15 +12483,12 @@ legitimize_pic_address (rtx orig, rtx reg)
/* Load the thread pointer. If TO_REG is true, force it into a register. */
static rtx
-get_thread_pointer (bool to_reg)
+get_thread_pointer (enum machine_mode tp_mode, bool to_reg)
{
- rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
-
- if (GET_MODE (tp) != Pmode)
-tp = convert_to_mode (Pmode, tp, 1);
+ rtx tp = gen_rtx_UNSPEC (tp_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
if (to_reg)
-tp = copy_addr_to_reg (tp);
+tp = copy_to_mode_reg (tp_mode, tp);
return tp;
}
@@ -12543,6 +12540,7 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
{
rtx dest, base, off;
rtx pic = NULL_RTX, tp = NULL_RTX;
+ enum machine_mode tp_mode = Pmode;
int type;
switch (model)
@@ -12568,7 +12566,7 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
else
emit_insn (gen_tls_dynamic_gnu2_32 (dest, x, pic));
- tp = get_thread_pointer (true);
+ tp = get_thread_pointer (Pmode, true);
dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
set_unique_reg_note (get_last_insn (), REG_EQUAL, x);
@@ -12618,7 +12616,7 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
else
emit_insn (gen_tls_dynamic_gnu2_32 (base, tmp, pic));
- tp = get_thread_pointer (true);
+ tp = get_thread_pointer (Pmode, true);
set_unique_reg_note (get_last_insn (), REG_EQUAL,
gen_rtx_MINUS (Pmode, tmp, tp));
}
@@ -12664,27 +12662,18 @@
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 5:34 PM, H.J. Lu hjl.to...@gmail.com wrote:
Combine failed:
(set (reg:QI 63 [ c ])
(mem/c:QI (plus:DI (zero_extend:DI (unspec:SI [
(const_int 0 [0])
] UNSPEC_TP))
(mem/u/c:DI (const:DI (unspec:DI [
(symbol_ref:SI (c) [flags 0x60]
var_decl 0x719b8140 c)
] UNSPEC_GOTNTPOFF)) [2 S8 A8])) [0 c+0 S1 A8]))
Wrong testcase. IT should be
--
extern __thread char c;
extern __thread short w;
extern char y;
extern short i;
void
ie (void)
{
y = c;
i = w;
}
---
I got
movl %fs:0, %eax
movq c@gottpoff(%rip), %rdx
movzbl (%rax,%rdx), %edx
movb %dl, y(%rip)
movq w@gottpoff(%rip), %rdx
movzwl (%rax,%rdx), %eax
movw %ax, i(%rip)
ret
It can be
movq c@gottpoff(%rip), %rax
movzbl %fs:(%rax), %eax
movb %al, y(%rip)
movq w@gottpoff(%rip), %rax
movzwl %fs:(%rax), %eax
movw %ax, i(%rip)
ret
How about this patch? I changed 32 TP load to
(define_insn *load_tp_x32_mode
[(set (match_operand:SWI48x 0 register_operand =r)
(unspec:SWI48x [(const_int 0)] UNSPEC_TP))]
TARGET_X32
mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}
[(set_attr type imov)
(set_attr modrm 0)
(set_attr length 7)
(set_attr memory load)
(set_attr imm_disp false)])
and removed *load_tp_x32_zext.
No, your whole approach with splitters is wrong.
@@ -12747,11 +12747,11 @@
(define_mode_attr tp_seg [(SI gs) (DI fs)])
;; Load and add the thread base pointer from %tp_seg:0.
-(define_insn *load_tp_x32
- [(set (match_operand:SI 0 register_operand =r)
- (unspec:SI [(const_int 0)] UNSPEC_TP))]
+(define_insn *load_tp_x32_mode
+ [(set (match_operand:SWI48x 0 register_operand =r)
+ (unspec:SWI48x [(const_int 0)] UNSPEC_TP))]
TARGET_X32
- mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}
+ mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}
The result is zero_extended SImode register, not fake SImode register in DImore.
But as said, you should generate correct sequence from the beginning.
Uros.
Re: [PATCH] eh_personality.cc: unwinding on ARM
On Mon, Mar 19, 2012 at 12:12 PM, Andrew Stubbs a...@codesourcery.com wrote: On 16/03/12 13:29, EXTERNAL Waechtler Peter (Fa. TCP, CM-AI/PJ-CF31) wrote: The CodeSourcery toolchain contains a fix like the following, please consider for adding it. Here's the full original patch with ChangeLog. I don't know why Dan never submitted this one. Perhaps it's not suitable for upstream or not considered the correct fix? I think it was just a pain to write a test for. Anyway, as far as copyright goes, I don't believe CodeSourcery has any problem with this being committed. Andrew -- Thanks, Daniel
[Ada] gnatmake crashes with -cargs -m -margs -m
This patch ensures that gnatmake no longer crashes when there are -m switches after -cargs and after -margs on the command line. Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Vincent Celier cel...@adacore.com * make.adb (Scan_Make_Arg): Make sure all significant -m switches on the command line are counted. Index: make.adb === --- make.adb(revision 185520) +++ make.adb(working copy) @@ -7423,6 +7423,16 @@ Add_Switch (Argv, Program_Args, And_Save = And_Save); + -- Make sure that all significant switches -m on the command line + -- are counted. + + if Argv'Length 2 + and then Argv (1 .. 2) = -m + and then Argv /= -mieee + then +N_M_Switch := N_M_Switch + 1; + end if; + -- Handle non-default compiler, binder, linker, and handle --RTS switch elsif Argv'Length 2 and then Argv (1 .. 2) = -- then
[Ada] Better error message for a ** b ** c
This patch gives better error recovery and message for a ** b ** c 1. package ParenExp is 2.a : Integer := 2 ** 3 ** 4; | parenthesization required for ** 3. end; Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Robert Dewar de...@adacore.com * par-ch4.adb (Check_Bad_Exp): New procedure Index: par-ch4.adb === --- par-ch4.adb (revision 185520) +++ par-ch4.adb (working copy) @@ -6,7 +6,7 @@ -- -- -- B o d y -- -- -- --- Copyright (C) 1992-2011, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- GNAT is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -81,6 +81,9 @@ -- Called to place complaint about bad range attribute at the given -- source location. Terminates by raising Error_Resync. + procedure Check_Bad_Exp; + -- Called after scanning a**b, posts error if ** detected + procedure P_Membership_Test (N : Node_Id); -- N is the node for a N_In or N_Not_In node whose right operand has not -- yet been processed. It is called just after scanning out the IN keyword. @@ -107,6 +110,20 @@ Resync_Expression; end Bad_Range_Attribute; + --- + -- Check_Bad_Exp -- + --- + + procedure Check_Bad_Exp is + begin + if Token = Tok_Double_Asterisk then + Error_Msg_SC (parenthesization required for '*'*); + Scan; -- past ** + Discard_Junk_Node (P_Primary); + Check_Bad_Exp; + end if; + end Check_Bad_Exp; + -- -- 4.1 Name (also 6.4) -- -- @@ -1933,6 +1950,7 @@ Scan; -- past ** Set_Left_Opnd (Node2, Node1); Set_Right_Opnd (Node2, P_Primary); + Check_Bad_Exp; Node1 := Node2; end if; @@ -2320,6 +2338,7 @@ Scan; -- past ** Set_Left_Opnd (Node2, Node1); Set_Right_Opnd (Node2, P_Primary); +Check_Bad_Exp; return Node2; else return Node1;
[Ada] Initial framework for Valid_Scalars attribute
This is the initial checkin to establish the framework for this new attribute which will check subcomponents of composite objects. No test yet, since the implementation is not there yet! Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Robert Dewar de...@adacore.com * exp_attr.adb, sem_attr.adb, sem_attr.ads, snames.ads-tmpl: Add initial framework for Valid_Scalars attribute. Index: exp_attr.adb === --- exp_attr.adb(revision 185520) +++ exp_attr.adb(working copy) @@ -5368,6 +5368,15 @@ Validity_Checks_On := Save_Validity_Checks_On; end Valid; + --- + -- Valid_Scalars -- + --- + + when Attribute_Valid_Scalars = Valid_Scalars : declare + begin + raise Program_Error; + end Valid_Scalars; + --- -- Value -- --- Index: sem_attr.adb === --- sem_attr.adb(revision 185520) +++ sem_attr.adb(working copy) @@ -5196,6 +5196,15 @@ Set_Etype (N, Standard_Boolean); + --- + -- Valid_Scalars -- + --- + + when Attribute_Valid_Scalars = + Check_E0; + Check_Type; + -- More stuff TBD ??? + --- -- Value -- --- @@ -6034,7 +6043,7 @@ return; -- No other cases are foldable (they certainly aren't static, and at - -- the moment we don't try to fold any cases other than these three). + -- the moment we don't try to fold any cases other than the ones above). else Check_Expressions; @@ -8145,6 +8154,7 @@ Attribute_Universal_Literal_String | Attribute_Unrestricted_Access| Attribute_Valid | + Attribute_Valid_Scalars | Attribute_Value | Attribute_Wchar_T_Size | Attribute_Wide_Value | Index: sem_attr.ads === --- sem_attr.ads(revision 185520) +++ sem_attr.ads(working copy) @@ -6,7 +6,7 @@ -- -- -- S p e c -- -- -- --- Copyright (C) 1992-2011, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- GNAT is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -549,6 +549,13 @@ -- Natural'Size is typically 31, the value of Natural'VADS_Size is 32. -- For all other types, Size and VADS_Size yield the same value. + --- + -- Valid_Scalars -- + --- + + Attribute_Valid_Scalars = True, + -- Typ'Valid_Scalars applies to ??? + -- Value_Size -- Index: snames.ads-tmpl === --- snames.ads-tmpl (revision 185520) +++ snames.ads-tmpl (working copy) @@ -854,6 +854,7 @@ Name_VADS_Size : constant Name_Id := N + $; -- GNAT Name_Val: constant Name_Id := N + $; Name_Valid : constant Name_Id := N + $; + Name_Valid_Scalars : constant Name_Id := N + $; -- GNAT Name_Value_Size : constant Name_Id := N + $; -- GNAT Name_Variable_Indexing : constant Name_Id := N + $; -- GNAT Name_Version: constant Name_Id := N + $; @@ -1418,6 +1419,7 @@ Attribute_VADS_Size, Attribute_Val, Attribute_Valid, + Attribute_Valid_Scalars, Attribute_Value_Size, Attribute_Variable_Indexing, Attribute_Version,
[Ada] Better error message for misused preprocessor directive
This patch causes the scanner to recognize preprocessor directives in the case where the preprocessor is in active, and give better messages, as shown by this example compiled with -gnatld7 -gnatj60. 1. package Preproc is 2. #if JUNK then | preprocessor directive ignored, preprocessor not active 3.X : Integer; 4. #elsif JUNK1 then | preprocessor directive ignored, preprocessor not active 5.Y : Integer; 6. #else | preprocessor directive ignored, preprocessor not active 7.Z : Integer; 8. #end if; | preprocessor directive ignored, preprocessor not active 9. end Preproc; Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Robert Dewar de...@adacore.com * scng.adb (Scan): Recognize incorrect preprocessor directive Index: scng.adb === --- scng.adb(revision 185520) +++ scng.adb(working copy) @@ -6,7 +6,7 @@ -- -- -- B o d y -- -- -- --- Copyright (C) 1992-2011, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- -- -- -- GNAT is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -2242,6 +2242,71 @@ Scan_Ptr := Scan_Ptr + 1; return; +-- Check for something looking like a preprocessor directive + +elsif Source (Scan_Ptr) = '#' + and then (Source (Scan_Ptr + 1 .. Scan_Ptr + 2) = if + or else +Source (Scan_Ptr + 1 .. Scan_Ptr + 5) = elsif + or else +Source (Scan_Ptr + 1 .. Scan_Ptr + 4) = else + or else +Source (Scan_Ptr + 1 .. Scan_Ptr + 3) = end) +then + Error_Msg_S + (preprocessor directive ignored, preprocessor not active); + + -- Skip to end of line + + loop + if Source (Scan_Ptr) in Graphic_Character + or else + Source (Scan_Ptr) = HT + then + Scan_Ptr := Scan_Ptr + 1; + + -- Done if line terminator or EOF + + elsif Source (Scan_Ptr) in Line_Terminator + or else +Source (Scan_Ptr) = EOF + then + exit; + + -- If we have a wide character, we have to scan it out, + -- because it might be a legitimate line terminator + + elsif Start_Of_Wide_Character then + declare +Wptr : constant Source_Ptr := Scan_Ptr; +Code : Char_Code; +Err : Boolean; + + begin +Scan_Wide (Source, Scan_Ptr, Code, Err); + +-- If not well formed wide character, then just skip +-- past it and ignore it. + +if Err then + Scan_Ptr := Wptr + 1; + +-- If UTF_32 terminator, terminate comment scan + +elsif Is_UTF_32_Line_Terminator (UTF_32 (Code)) then + Scan_Ptr := Wptr; + exit; +end if; + end; + + -- Else keep going (don't worry about bad comment chars + -- in this context, we just want to find the end of line. + + else + Scan_Ptr := Scan_Ptr + 1; + end if; + end loop; + -- Otherwise, this is an illegal character else
[Ada] Remove high level optimizer framework
This framework was implemented years ago, but never documented, and no optimizer was ever implemented, so best just to remove it at this stage. If anyone ever wants to implement a high level optimizer, the least of the effort will be putting this back. Note that the critical point (which is that reanalysis works) has not been checked for many many years, and is almost certainly broken anyway. Tested on x86_64-pc-linux-gnu, committed on trunk 2012-03-19 Robert Dewar de...@adacore.com * opt.ads: Remove HLO_Active flag. * sem.adb: Remove call of high level optimizer. * sem.ads (New_Nodes_OK): Removed. * sem_ch10.adb: Remove references to New_Nodes_OK. * switch-c.adb: Remove handling of -gnatH switch. Index: switch-c.adb === --- switch-c.adb(revision 185520) +++ switch-c.adb(working copy) @@ -634,12 +634,6 @@ Ptr := Ptr + 1; Usage_Requested := True; --- Processing for H switch - -when 'H' = - Ptr := Ptr + 1; - HLO_Active := True; - -- Processing for i switch when 'i' = Index: sem_ch10.adb === --- sem_ch10.adb(revision 185520) +++ sem_ch10.adb(working copy) @@ -2977,7 +2977,6 @@ -- Start of processing for Expand_With_Clause begin - New_Nodes_OK := New_Nodes_OK + 1; Withn := Make_With_Clause (Loc, Name = Build_Unit_Name (Nam)); @@ -3002,8 +3001,6 @@ if Nkind (Nam) = N_Expanded_Name then Expand_With_Clause (Item, Prefix (Nam), N); end if; - - New_Nodes_OK := New_Nodes_OK - 1; end Expand_With_Clause; --- @@ -3165,7 +3162,6 @@ return; end if; - New_Nodes_OK := New_Nodes_OK + 1; Withn := Make_With_Clause (Loc, Name = Build_Unit_Name); Set_Library_Unit (Withn, P); @@ -3183,8 +3179,6 @@ if Is_Child_Spec (P_Unit) then Implicit_With_On_Parent (P_Unit, N); end if; - - New_Nodes_OK := New_Nodes_OK - 1; end Implicit_With_On_Parent; -- @@ -3734,8 +3728,6 @@ -- Start of processing for Expand_Limited_With_Clause begin - New_Nodes_OK := New_Nodes_OK + 1; - if Nkind (Nam) = N_Identifier then -- Create node for name of withed unit @@ -3793,8 +3785,6 @@ Install_Limited_Withed_Unit (Withn); end if; end if; - - New_Nodes_OK := New_Nodes_OK - 1; end Expand_Limited_With_Clause; -- Index: sem.adb === --- sem.adb (revision 185520) +++ sem.adb (working copy) @@ -30,7 +30,6 @@ with Errout; use Errout; with Expander; use Expander; with Fname;use Fname; -with HLO; use HLO; with Lib; use Lib; with Lib.Load; use Lib.Load; with Nlists; use Nlists; @@ -1367,7 +1366,6 @@ S_Global_Dis_Names : constant Boolean := Global_Discard_Names; S_In_Spec_Expr : constant Boolean := In_Spec_Expression; S_Inside_A_Generic : constant Boolean := Inside_A_Generic; - S_New_Nodes_OK : constant Int := New_Nodes_OK; S_Outer_Gen_Scope : constant Entity_Id:= Outer_Generic_Scope; Generic_Main : constant Boolean := @@ -1386,8 +1384,7 @@ -- and we need to restore these saved values at the end. procedure Do_Analyze; - -- Procedure to analyze the compilation unit. This is called more than - -- once when the high level optimizer is activated. + -- Procedure to analyze the compilation unit -- Do_Analyze -- @@ -1491,15 +1488,6 @@ if not Analyzed (Comp_Unit) then Initialize_Version (Current_Sem_Unit); - if HLO_Active then -Expander_Mode_Save_And_Set (False); -New_Nodes_OK := 1; -Do_Analyze; -Reset_Analyzed_Flags (Comp_Unit); -Expander_Mode_Restore; -High_Level_Optimize (Comp_Unit); -New_Nodes_OK := 0; - end if; -- Do analysis, and then append the compilation unit onto the -- Comp_Unit_List, if appropriate. This is done after analysis, @@ -1547,7 +1535,6 @@ GNAT_Mode:= S_GNAT_Mode; In_Spec_Expression := S_In_Spec_Expr; Inside_A_Generic := S_Inside_A_Generic; - New_Nodes_OK := S_New_Nodes_OK; Outer_Generic_Scope := S_Outer_Gen_Scope; Restore_Opt_Config_Switches (Save_Config_Switches); Index: sem.ads === --- sem.ads (revision 185520) +++ sem.ads (working copy) @@ -209,10 +209,6 @@ package Sem
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 5:19 PM, H.J. Lu hjl.to...@gmail.com wrote: movl %fs:0, %eax movq c@gottpoff(%rip), %rdx movzbl (%rax,%rdx), %edx movb %dl, y(%rip) movq w@gottpoff(%rip), %rdx movzwl (%rax,%rdx), %eax movw %ax, i(%rip) ret It can be movq c@gottpoff(%rip), %rax movzbl %fs:(%rax), %eax movb %al, y(%rip) movq w@gottpoff(%rip), %rax movzwl %fs:(%rax), %eax movw %ax, i(%rip) ret This is just CSE in action. It CSEd movl %fs:0, %eax, since it has to be zero extended before going into address. Uros.
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 5:47 PM, H.J. Lu hjl.to...@gmail.com wrote: For x32, thread pointer is an unsigned 32bit value. movl %fs:0, %eax is the correct instruction to load thread pointer into EAX and RAX. So, where is ZERO_EXTEND RTX then? Uros.
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 9:49 AM, Uros Bizjak ubiz...@gmail.com wrote: On Mon, Mar 19, 2012 at 5:47 PM, H.J. Lu hjl.to...@gmail.com wrote: For x32, thread pointer is an unsigned 32bit value. movl %fs:0, %eax is the correct instruction to load thread pointer into EAX and RAX. So, where is ZERO_EXTEND RTX then? Thread pointer (TP) is an opaque value to GCC. GCC needs to load TP into a SImode or DImode register. ZERO_EXTEND isn't needed when there is a single instruction to load TP into a DImode register. -- H.J.
Re: [PATCH][RFC] Merge 'expand' and 'rtl_eh'
On Mon, 19 Mar 2012, Steven Bosscher wrote: On Mon, Mar 19, 2012 at 4:41 PM, Richard Guenther rguent...@suse.de wrote: Comments? What does rtl_eh do for no-SJLJ exceptions? Quoting from except.c 'Then, via finish_eh_generation, we generate the real landing pads to which the runtime will actually transfer control. These new landing pads perform whatever bookkeeping is needed by the target backend in order to resume execution within the current function. Each of these new landing pads falls through into the post_landing_pad label which had been used within the CFG up to this point. All exception edges within the CFG are redirected to the new landing pads. If the target uses setjmp to implement exceptions, the various extra calls into the runtime to register and unregister the current stack frame are emitted at this time.' Have you tested with SJLJ exceptions? (Can/should we move that code to GIMPLE?) No. The only thing that changes is the time when we call fixup_tail_calls, otherwise the patch should be a no-op basically hiding the inconsistent state during the piecewise RTL expansion from the pass manager. As discussed on IRC, we ought to merge the passes that keeps RTL inconsistent into single pass. Until RTl reaches its specified form (that is after unsharing) those are not realy independent passes anyway. They just come from historical way rest_of_compilation function was shaped. As a followup I will try to cleanup those early stages of compilation getting rid of pass_jump/pass_jump2 and friends. Honza Richard.
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 5:55 PM, H.J. Lu hjl.to...@gmail.com wrote: For x32, thread pointer is an unsigned 32bit value. movl %fs:0, %eax is the correct instruction to load thread pointer into EAX and RAX. So, where is ZERO_EXTEND RTX then? Thread pointer (TP) is an opaque value to GCC. GCC needs to load TP into a SImode or DImode register. ZERO_EXTEND isn't needed when there is a single instruction to load TP into a DImode register. I don't agree with this explanation. The mode can't be SImode and DImode. TP is either SImode or ZERO_EXTENDed to DImode, this is the reason we went for all that TARGET_X32 stuff in TP load RTX. Please test my proposed patch. If it works OK, I will commit it to SVN. Thanks, Uros.
AW: [PATCH] eh_personality.cc: unwinding on ARM
On Mon, Mar 19, 2012 at 12:12 PM, Andrew Stubbs
a...@codesourcery.com wrote:
On 16/03/12 13:29, EXTERNAL Waechtler Peter (Fa. TCP,
CM-AI/PJ-CF31) wrote:
The CodeSourcery toolchain contains a fix like the following,
please consider for adding it.
Here's the full original patch with ChangeLog.
I don't know why Dan never submitted this one. Perhaps it's
not suitable for
upstream or not considered the correct fix?
I think it was just a pain to write a test for.
Gentlemen,
while I have your attention: what is an virtual unwind frame? ;)
One test case is quite simple:
std::vectorint v(10);
rc = v.at(42);
The versions of glibc and libstdc++ looks quite old, but montavista patches
them up (but if the customer insists on such an old version...)
So this is the unwind entry by readelf -u :
0xa518 _Z6nqueenPiii: @0x10c88
Personality routine: 0xa33c __gxx_personality_v0@@CXXABI_1.3
0x9b vsp = r11
0x42 vsp = vsp - 12
0x84 0x83 pop {r4, r5, r11, r14}
0xb0 finish
0xb0 finish
0xb0 finish
no better output for libstdc++
0xaa1b0 __gxx_personality_v0: @0xbd0f4
Personality routine: 0x3dd10 _init+0xc8c
0xad1f0 _ZN9__gnu_cxx27__verbose_terminate_handlerEv: @0xbd364
Personality routine: 0x3dd10 _init+0xc8c
So far, I think if the personality routine is called _and_ there is something
like __gnu_cxx::__verbose_terminate_handler on the stack (with attribute
noreturn)
it enters the loop.
Perhaps a function that noreturns has a virtual unwind frame -
i.e. no unwind entry exists?
Peter
# ./eh -V
Starting up
terminate called after throwing an instance of 'std::out_of_range'
what(): vector::_M_range_check
sigaction_func:(6, info:0x4dc98, context:0x4dd18) si_code: -6
eh_stack_unwind: enter
eh_stack_unwind: after backtrace: used_pointers: 100 (asm: 0)
** EXCEPTION in process PID=2614 ***
signal Aborted
command line : ./eh
thread ./eh (TID 2614)
== registers :
TRAP_NO = 0x, ERROR_CODE = 0x, OLDMASK =0x
R0 = 0x, R1 = 0x0a36, R2 = 0x0006, R3 = 0x2aab5460
R4 = 0x0a36, R5 = 0x0006, R6 = 0x4c97f000, R7 = 0x010c
R8 = 0x2aab4fc0, R9 = 0x2aab5460, R10 = 0x0bfc, FP = 0x7eacec14
IP = 0x7eaceb98, SP = 0x7eacea78, LR = 0x4c8823e8, PC = 0x4c88241c
CPSR = 0x2010, FAULT_ADDRESS = 0x
== backtrace (orig glibc):
./eh( eh_stack_unwind +0x18c)[0xde0c]
./eh[0xdfac]
/lib/libc.so.6( __default_rt_sa_restorer_v2 +0x0)[0x4c883770]
/lib/libc.so.6( gsignal +0x40)[0x4c88241c]
/lib/libc.so.6( abort +0x1c0)[0x4c88680c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6( __gnu_cxx::__verbose_terminate_handler()
+0x134)[0x4cb2ca0c]
/lib/libstdc++.so.6(
Re: RFA: consolidate DWARF strings into libiberty
DJ == DJ Delorie d...@redhat.com writes: DJ The only drawback to adding toplevel libraries is coordinating changes DJ among the toplevel configury. And adding crud to Makefiles all over. Pick a name for the new library and I will implement this. Tom
Re: [Patch,AVR]: Hack around PR rtl-optimization/52543
On Mar 9, 2012, at 10:46 AM, Georg-Johann Lay wrote: The problem with the PR is that lower-subreg.c happily splits multi-byte moves from address spaces without knowing anything about the additional costs this is causing. Nasty, arm hit this sort of problem recently as well, and I've hit this sort of problem; here's to wishing the underlying problem gets fixed soon.
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 6:01 PM, Uros Bizjak ubiz...@gmail.com wrote:
For x32, thread pointer is an unsigned 32bit value.
movl %fs:0, %eax
is the correct instruction to load thread pointer into EAX and RAX.
So, where is ZERO_EXTEND RTX then?
Thread pointer (TP) is an opaque value to GCC. GCC needs to load
TP into a SImode or DImode register. ZERO_EXTEND isn't needed
when there is a single instruction to load TP into a DImode register.
I don't agree with this explanation. The mode can't be SImode and
DImode. TP is either SImode or ZERO_EXTENDed to DImode, this is the
reason we went for all that TARGET_X32 stuff in TP load RTX.
Please test my proposed patch. If it works OK, I will commit it to SVN.
The onyl acceptable way is to generate ZERO_EXTEND in place, so:
--cut here--
static rtx
get_thread_pointer (enum machine_mode tp_mode, bool to_reg)
{
rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
if (GET_MODE (tp) != tp_mode)
{
gcc_assert (GET_MODE (tp) == SImode);
gcc_assert (tp_mode == DImode);
tp = gen_rtx_ZERO_EXTEND (tp_mode, tp);
}
if (to_reg)
tp = copy_to_mode_reg (tp_mode, tp);
return tp;
}
--cut here--
This will generate:
movqc@gottpoff(%rip), %rax
movzbl %fs:(%rax), %eax
movb%al, y(%rip)
movqw@gottpoff(%rip), %rax
movzwl %fs:(%rax), %eax
movw%ax, i(%rip)
ret
Uros.
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 10:29 AM, Uros Bizjak ubiz...@gmail.com wrote:
On Mon, Mar 19, 2012 at 6:01 PM, Uros Bizjak ubiz...@gmail.com wrote:
For x32, thread pointer is an unsigned 32bit value.
movl %fs:0, %eax
is the correct instruction to load thread pointer into EAX and RAX.
So, where is ZERO_EXTEND RTX then?
Thread pointer (TP) is an opaque value to GCC. GCC needs to load
TP into a SImode or DImode register. ZERO_EXTEND isn't needed
when there is a single instruction to load TP into a DImode register.
I don't agree with this explanation. The mode can't be SImode and
DImode. TP is either SImode or ZERO_EXTENDed to DImode, this is the
reason we went for all that TARGET_X32 stuff in TP load RTX.
FWIW, TP maintained by OS is opaque to GCC and GCC mode doesn't
apply to the TP value maintained by OS. The instruction pattern to load TP
into a register is provided by OS and is also opaque to GCC. X32 OS provides
single instructions to load TP into SImode and DImode registers. We
can load x32 TP into SImode register and ZERO_EXTENDs to DImode.
Or we can use the OS provided instruction to load TP into DImode
register directly.
Please test my proposed patch. If it works OK, I will commit it to SVN.
The onyl acceptable way is to generate ZERO_EXTEND in place, so:
--cut here--
static rtx
get_thread_pointer (enum machine_mode tp_mode, bool to_reg)
{
rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
if (GET_MODE (tp) != tp_mode)
{
gcc_assert (GET_MODE (tp) == SImode);
gcc_assert (tp_mode == DImode);
tp = gen_rtx_ZERO_EXTEND (tp_mode, tp);
}
if (to_reg)
tp = copy_to_mode_reg (tp_mode, tp);
return tp;
}
--cut here--
This version works fine.
Thanks.
--
H.J.
[lra] patch to discourage some register usage on x86/x86-64
The following patch discourages usage of BP, R12, and R13 as it results
in larger addresses on x86/x86-64.
Committed as rev. 185533.
2012-03-19 Vladimir Makarov vmaka...@redhat.com
* config/i386/i386.c (ix86_register_bank): Add special treatment
for BP, R12, and R13.
Index: config/i386/i386.c
===
--- config/i386/i386.c (revision 185531)
+++ config/i386/i386.c (working copy)
@@ -30508,14 +30508,21 @@ ix86_free_from_memory (enum machine_mode
static int
ix86_register_bank (int hard_regno)
{
+ /* ebp and r13 as the base always wants a displacement, r12 as the
+ base always wants an index. So discourage their usage in an
+ address. */
+ if (hard_regno == R12_REG || hard_regno == R13_REG)
+return 4;
+ if (hard_regno == BP_REG)
+return 2;
/* New x86-64 int registers result in bigger code size. Discourage
them. */
if (FIRST_REX_INT_REG = hard_regno hard_regno = LAST_REX_INT_REG)
-return 2;
+return 3;
/* New x86-64 SSE registers result in bigger code size. Discourage
them. */
if (FIRST_REX_SSE_REG = hard_regno hard_regno = LAST_REX_SSE_REG)
-return 2;
+return 3;
/* Usage of AX register results in smaller code. Prefer it. */
if (hard_regno == 0)
return 0;
Re: PATCH: Properly generate X32 IE sequence
On Mon, Mar 19, 2012 at 6:50 PM, H.J. Lu hjl.to...@gmail.com wrote:
Please test my proposed patch. If it works OK, I will commit it to SVN.
The onyl acceptable way is to generate ZERO_EXTEND in place, so:
--cut here--
static rtx
get_thread_pointer (enum machine_mode tp_mode, bool to_reg)
{
rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
if (GET_MODE (tp) != tp_mode)
{
gcc_assert (GET_MODE (tp) == SImode);
gcc_assert (tp_mode == DImode);
tp = gen_rtx_ZERO_EXTEND (tp_mode, tp);
}
if (to_reg)
tp = copy_to_mode_reg (tp_mode, tp);
return tp;
}
--cut here--
This version works fine.
Attached patch was committed to mainline SVN with following ChangeLog:
2012-03-19 Uros Bizjak ubiz...@gmail.com
* config/i386/i386.c (get_thread_pointer): Add tp_mode argument.
Generate ZERO_EXTEND in place if GET_MODE (tp) != tp_mode.
(legitimize_tls_address) TLS_MODEL_INITIAL_EXEC: Always generate
DImode UNSPEC_GOTNTPOFF references on TARGET_64BIT.
(ix86_decompose_address): Allow zero extended UNSPEC_TP references.
Revert:
2012-03-13 Uros Bizjak ubiz...@gmail.com
* config/i386/i386.h (TARGET_TLS_INDIRECT_SEG_REFS): New.
* config/i386/i386.c (ix86_decompose_address): Use
TARGET_TLS_INDIRECT_SEG_REFS to prevent %fs:(%reg) addresses.
(legitimize_tls_address): Use TARGET_TLS_INDIRECT_SEG_REFS to load
thread pointer to a register.
Revert:
2012-03-10 H.J. Lu hongjiu...@intel.com
* config/i386/i386.c (ix86_decompose_address): Disallow fs:(reg)
if Pmode != word_mode.
(legitimize_tls_address): Call gen_tls_initial_exec_x32 if
Pmode == SImode for TARGET_X32.
* config/i386/i386.md (UNSPEC_TLS_IE_X32): New.
(tls_initial_exec_x32): Likewise.
Tested on x86_64-pc-linux-gnu {,-m32}.
Thanks,
Uros.
Index: i386.md
===
--- i386.md (revision 185524)
+++ i386.md (working copy)
@@ -96,7 +96,6 @@
UNSPEC_TLS_LD_BASE
UNSPEC_TLSDESC
UNSPEC_TLS_IE_SUN
- UNSPEC_TLS_IE_X32
;; Other random patterns
UNSPEC_SCAS
@@ -12836,28 +12835,6 @@
}
[(set_attr type multi)])
-;; When Pmode == SImode, there may be no REX prefix for ADD. Avoid
-;; any instructions between MOV and ADD, which may interfere linker
-;; IE-LE optimization, since the last byte of the previous instruction
-;; before ADD may look like a REX prefix. This also avoids
-;; movl x@gottpoff(%rip), %reg32
-;; movl $fs:(%reg32), %reg32
-;; Since address override works only on the (reg32) part in fs:(reg32),
-;; we can't use it as memory operand.
-(define_insn tls_initial_exec_x32
- [(set (match_operand:SI 0 register_operand =r)
- (unspec:SI
-[(match_operand 1 tls_symbolic_operand)]
-UNSPEC_TLS_IE_X32))
- (clobber (reg:CC FLAGS_REG))]
- TARGET_X32
-{
- output_asm_insn
-(mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}, operands);
- return add{l}\t{%a1@gottpoff(%%rip), %0|%0, %a1@gottpoff[rip]};
-}
- [(set_attr type multi)])
-
;; GNU2 TLS patterns can be split.
(define_expand tls_dynamic_gnu2_32
Index: i386.c
===
--- i386.c (revision 185524)
+++ i386.c (working copy)
@@ -11514,6 +11514,10 @@ ix86_decompose_address (rtx addr, struct ix86_addr
scale = 1 scale;
break;
+ case ZERO_EXTEND:
+ op = XEXP (op, 0);
+ /* FALLTHRU */
+
case UNSPEC:
if (XINT (op, 1) == UNSPEC_TP
TARGET_TLS_DIRECT_SEG_REFS
@@ -12483,15 +12487,20 @@ legitimize_pic_address (rtx orig, rtx reg)
/* Load the thread pointer. If TO_REG is true, force it into a register. */
static rtx
-get_thread_pointer (bool to_reg)
+get_thread_pointer (enum machine_mode tp_mode, bool to_reg)
{
rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
- if (GET_MODE (tp) != Pmode)
-tp = convert_to_mode (Pmode, tp, 1);
+ if (GET_MODE (tp) != tp_mode)
+{
+ gcc_assert (GET_MODE (tp) == SImode);
+ gcc_assert (tp_mode == DImode);
+ tp = gen_rtx_ZERO_EXTEND (tp_mode, tp);
+}
+
if (to_reg)
-tp = copy_addr_to_reg (tp);
+tp = copy_to_mode_reg (tp_mode, tp);
return tp;
}
@@ -12543,6 +12552,7 @@ legitimize_tls_address (rtx x, enum tls_model mode
{
rtx dest, base, off;
rtx pic = NULL_RTX, tp = NULL_RTX;
+ enum machine_mode tp_mode = Pmode;
int type;
switch (model)
@@ -12568,7 +12578,7 @@ legitimize_tls_address (rtx x, enum tls_model mode
else
emit_insn (gen_tls_dynamic_gnu2_32 (dest, x, pic));
- tp = get_thread_pointer (true);
+ tp = get_thread_pointer (Pmode, true);
dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
set_unique_reg_note (get_last_insn (),
[pph] Add support to re-play actions on types (issue5845069)
Add support to re-play actions on types as well as symbols. When declaring class types, the parser calls finish_struct_methods to perform things like sorting the method vector for the class. This needs to be done at reading time, because the sorting is done based on the pointer values of the entries in the method vector. We were eagerly doing this for *all* class types we read from PPH images, but this is not applicable to all class types. Using the symtab to replay this action allows us to do it exactly on the same classes done during the original parse. The symbol table needs renaming now. Done in a subsequent patch. 2012-03-19 Diego Novillo dnovi...@google.com * Make-lang.in (cp/class.o): Add dependency on PPH_H. * class.c (finish_struct_methods): If pph_writer_enabled_p returns true, call pph_add_type_to_symtab. * pph-in.c (pph_in_tcc_type): Do not call finish_struct_methods. (pph_in_symtab_action): Handle PPH_SYMTAB_FINISH_STRUCT_METHODS. (pph_in_symtab): Likewise. * pph-out.c (pph_out_symtab_action): Likewise. (pph_add_type_to_symtab): New. * pph.h (enum pph_symtab_action): Add PPH_SYMTAB_FINISH_STRUCT_METHODS. (pph_add_type_to_symtab): Declare. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/pph@185537 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/cp/ChangeLog.pph | 27 +++ gcc/cp/Make-lang.in |2 +- gcc/cp/class.c |4 gcc/cp/pph-in.c | 26 -- gcc/cp/pph-out.c | 22 +- gcc/cp/pph.h |7 ++- 6 files changed, 75 insertions(+), 13 deletions(-) diff --git a/gcc/cp/ChangeLog.pph b/gcc/cp/ChangeLog.pph index c596b18..1cbf859 100644 --- a/gcc/cp/ChangeLog.pph +++ b/gcc/cp/ChangeLog.pph @@ -1,3 +1,30 @@ +2012-03-19 Diego Novillo dnovi...@google.com + + * Make-lang.in (cp/class.o): Add dependency on PPH_H. + * class.c (finish_struct_methods): If pph_writer_enabled_p + returns true, call pph_add_type_to_symtab. + * pph-in.c (pph_in_tcc_type): Do not call finish_struct_methods. + (pph_in_symtab_action): Handle PPH_SYMTAB_FINISH_STRUCT_METHODS. + (pph_in_symtab): Likewise. + * pph-out.c (pph_out_symtab_action): Likewise. + (pph_add_type_to_symtab): New. + * pph.h (enum pph_symtab_action): Add PPH_SYMTAB_FINISH_STRUCT_METHODS. + (pph_add_type_to_symtab): Declare. + +2012-03-19 Diego Novillo dnovi...@google.com + + * pph-streamer.h (struct pph_replay_entry): Rename from + pph_symtab_entry. + Rename field DECL to TO_REPLAY. + Update all users. + (struct pph_replay): Rename from pph_symtab. + (enum pph_replay_action): Rename from pph_symtab_action. + +2012-03-17 Diego Novillo dnovi...@google.com + + * parser.c (cp_lexer_print_token): Protect against NULL + values in CPP_NAME tokens. + 2012-03-16 Lawrence Crowl cr...@google.com * cp-tree.h (make_anon_name): Add location parameter. diff --git a/gcc/cp/Make-lang.in b/gcc/cp/Make-lang.in index 4968367..78328f9 100644 --- a/gcc/cp/Make-lang.in +++ b/gcc/cp/Make-lang.in @@ -298,7 +298,7 @@ cp/typeck.o: cp/typeck.c $(CXX_TREE_H) $(TM_H) $(FLAGS_H) \ output.h c-family/c-objc.h cp/class.o: cp/class.c $(CXX_TREE_H) $(TM_H) $(FLAGS_H) toplev.h \ $(TARGET_H) convert.h $(CGRAPH_H) $(TREE_DUMP_H) gt-cp-class.h \ - $(SPLAY_TREE_H) pointer-set.h + $(SPLAY_TREE_H) pointer-set.h $(PPH_H) cp/call.o: cp/call.c $(CXX_TREE_H) $(TM_H) $(FLAGS_H) toplev.h \ $(DIAGNOSTIC_CORE_H) intl.h gt-cp-call.h convert.h $(TARGET_H) langhooks.h \ $(TIMEVAR_H) c-family/c-objc.h diff --git a/gcc/cp/class.c b/gcc/cp/class.c index a601df6..3a94bb2 100644 --- a/gcc/cp/class.c +++ b/gcc/cp/class.c @@ -38,6 +38,7 @@ along with GCC; see the file COPYING3. If not see #include tree-dump.h #include splay-tree.h #include pointer-set.h +#include pph.h /* The number of nested classes being processed. If we are not in the scope of any class, this is zero. */ @@ -1863,6 +1864,9 @@ finish_struct_methods (tree t) if (!method_vec) return; + if (pph_writer_enabled_p ()) +pph_add_type_to_symtab (t, PPH_SYMTAB_FINISH_STRUCT_METHODS); + len = VEC_length (tree, method_vec); /* Clear DECL_IN_AGGR_P for all functions. */ diff --git a/gcc/cp/pph-in.c b/gcc/cp/pph-in.c index ba89aa4..ee72d77 100644 --- a/gcc/cp/pph-in.c +++ b/gcc/cp/pph-in.c @@ -2003,15 +2003,6 @@ pph_in_tcc_type (pph_stream *stream, tree type) default: break; } - - /* If TYPE has a METHOD_VEC, we need to resort it. Name lookup in - classes relies on the specific ordering of the class method - pointers. Since we generally instantiate them in a different - order than the original compile, the pointer values will be - different. This will cause name lookups to fail, unless we - resort the vector. */ - if (CLASS_TYPE_P (type)
[pph] Rename pph_sytmab - pph_replay (issue5846069)
This patch renames pph_symtab, pph_symtab_entry and pph_symtab_action into
pph_replay* to better reflects the semantics of this table.
No functional changes, just a rename.
2012-03-19 Diego Novillo dnovi...@google.com
* pph-streamer.h (struct pph_replay_entry): Rename from
pph_symtab_entry.
Rename field DECL to TO_REPLAY.
Update all users.
(struct pph_replay): Rename from pph_symtab.
(enum pph_replay_action): Rename from pph_symtab_action.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/pph@185539
138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/cp/class.c|2 +-
gcc/cp/decl.c |2 +-
gcc/cp/pph-core.c |2 +-
gcc/cp/pph-in.c | 74 +---
gcc/cp/pph-out.c | 53 ++-
gcc/cp/pph-streamer.h | 39 +++--
gcc/cp/pph.h | 14
gcc/cp/semantics.c|4 +-
8 files changed, 101 insertions(+), 89 deletions(-)
diff --git a/gcc/cp/class.c b/gcc/cp/class.c
index 3a94bb2..164ee10 100644
--- a/gcc/cp/class.c
+++ b/gcc/cp/class.c
@@ -1865,7 +1865,7 @@ finish_struct_methods (tree t)
return;
if (pph_writer_enabled_p ())
-pph_add_type_to_symtab (t, PPH_SYMTAB_FINISH_STRUCT_METHODS);
+pph_add_type_to_replay (t, PPH_REPLAY_FINISH_STRUCT_METHODS);
len = VEC_length (tree, method_vec);
diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index 9a04613..7503000 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -5964,7 +5964,7 @@ cp_rest_of_decl_compilation (tree decl, int top_level,
int at_end)
/* If we are generating a PPH image, add DECL to its symbol table. */
if (pph_writer_enabled_p ())
{
- pph_add_decl_to_symtab (decl, PPH_SYMTAB_DECLARE, top_level, at_end);
+ pph_add_decl_to_replay (decl, PPH_REPLAY_DECLARE, top_level, at_end);
return;
}
diff --git a/gcc/cp/pph-core.c b/gcc/cp/pph-core.c
index bdb0272..feaee29 100644
--- a/gcc/cp/pph-core.c
+++ b/gcc/cp/pph-core.c
@@ -1322,7 +1322,7 @@ pph_stream_close_1 (pph_stream *stream, bool flush_p)
stream-file = NULL;
VEC_free (pph_cache_entry, heap, stream-cache.v);
pointer_map_destroy (stream-cache.m);
- VEC_free (pph_symtab_entry, heap, stream-symtab.v);
+ VEC_free (pph_replay_entry, heap, stream-replay.v);
VEC_free (pph_stream_ptr, heap, stream-includes.v);
pointer_set_destroy (stream-includes.m);
diff --git a/gcc/cp/pph-in.c b/gcc/cp/pph-in.c
index ee72d77..b032315 100644
--- a/gcc/cp/pph-in.c
+++ b/gcc/cp/pph-in.c
@@ -2832,14 +2832,14 @@ pph_in_tree (pph_stream *stream)
/* Read a symbol table marker from STREAM. */
-static inline enum pph_symtab_action
-pph_in_symtab_action (pph_stream *stream)
-{
- enum pph_symtab_action m = (enum pph_symtab_action) pph_in_uchar (stream);
- gcc_assert (m == PPH_SYMTAB_DECLARE
- || m == PPH_SYMTAB_EXPAND
- || m == PPH_SYMTAB_EXPAND_1
- || m == PPH_SYMTAB_FINISH_STRUCT_METHODS);
+static inline enum pph_replay_action
+pph_in_replay_action (pph_stream *stream)
+{
+ enum pph_replay_action m = (enum pph_replay_action) pph_in_uchar (stream);
+ gcc_assert (m == PPH_REPLAY_DECLARE
+ || m == PPH_REPLAY_EXPAND
+ || m == PPH_REPLAY_EXPAND_1
+ || m == PPH_REPLAY_FINISH_STRUCT_METHODS);
return m;
}
@@ -2879,7 +2879,7 @@ pph_fn_already_expanded (tree fn)
original header files and out of PPH images. */
static void
-pph_in_symtab (pph_stream *stream)
+pph_in_replay (pph_stream *stream)
{
unsigned i, num;
@@ -2888,11 +2888,11 @@ pph_in_symtab (pph_stream *stream)
num = pph_in_uint (stream);
for (i = 0; i num; i++)
{
- pph_symtab_entry entry;
+ pph_replay_entry entry;
struct bitpack_d bp;
- entry.action = pph_in_symtab_action (stream);
- entry.decl = pph_in_tree (stream);
+ entry.action = pph_in_replay_action (stream);
+ entry.to_replay = pph_in_tree (stream);
bp = pph_in_bitpack (stream);
entry.top_level = bp_unpack_value (bp, 1);
entry.at_end = bp_unpack_value (bp, 1);
@@ -2900,30 +2900,32 @@ pph_in_symtab (pph_stream *stream)
entry.x_processing_template_decl = pph_in_int (stream);
entry.function_depth = pph_in_int (stream);
- if (entry.action == PPH_SYMTAB_DECLARE)
+ if (entry.action == PPH_REPLAY_DECLARE)
{
- if (pph_decl_already_emitted (entry.decl))
+ tree decl = entry.to_replay;
+ if (pph_decl_already_emitted (decl))
continue;
- cp_rest_of_decl_compilation (entry.decl, entry.top_level,
- entry.at_end);
+ cp_rest_of_decl_compilation (decl, entry.top_level, entry.at_end);
}
- else if (entry.action == PPH_SYMTAB_EXPAND
- || entry.action == PPH_SYMTAB_EXPAND_1)
+ else if (entry.action == PPH_REPLAY_EXPAND
+ || entry.action ==
Re: [v3] fix libstdc++/52476
this removes the pb_ds fails exposed by this patch.
-benjamin2012-03-19 Benjamin Kosnik b...@redhat.com
* include/ext/pb_ds/detail/pat_trie_/
constructors_destructor_fn_imps.hpp: Increment after recursion.
* include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp: Convert
node_type markup from brief.
diff --git a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp
index 8370a2e..c5748ec 100644
--- a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp
+++ b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp
@@ -1,6 +1,6 @@
// -*- C++ -*-
-// Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
+// Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
// Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
@@ -188,7 +188,11 @@ recursive_copy_node(node_const_pointer p_ncp)
__try
{
while (child_it != p_icp-end())
- a_p_children[child_i++] = recursive_copy_node(*(child_it++));
+ {
+ a_p_children[child_i] = recursive_copy_node(*(child_it));
+ child_i++;
+ child_it++;
+ }
p_ret = s_inode_allocator.allocate(1);
}
__catch(...)
diff --git a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp
index b7eb024..0a763b5 100644
--- a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp
+++ b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp
@@ -1,6 +1,6 @@
// -*- C++ -*-
-// Copyright (C) 2005, 2006, 2009, 2011 Free Software Foundation, Inc.
+// Copyright (C) 2005, 2006, 2009, 2011, 2012 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the terms
@@ -50,7 +50,11 @@ namespace __gnu_pbds
/// Base type for PATRICIA trees.
struct pat_trie_base
{
- /// Three types of nodes.
+ /**
+ * @brief Three types of nodes.
+ *
+ * i_node is used by _Inode, leaf_node by _Leaf, and head_node by _Head.
+ */
enum node_type
{
i_node,
Re: PING: PATCH: PR target/46770: Use .init_array/.fini_array sections
This breaks constructors on pretty much every elf+newlib target, because newlib and gcc both use HAVE_INITFINI_ARRAY (and have for many years) but the tests don't match. GCC puts ctors in .ctors but libgcc is built without support for them (newlib's generated config headers define HAVE_INITFINI_ARRAY, which causes gcc's initini-array.h to set USE_INITFINI_ARRAY, which shuts off libgcc's ctor/dtor support), so they don't run. 2011-08-20 H.J. Lu hongjiu...@intel.com PR target/46770 * config.gcc (tm_file): Add initfini-array.h if .init_arrary/.fini_array are supported. * crtstuff.c: Don't generate .ctors nor .dtors sections if USE_INITFINI_ARRAY is defined. * output.h (default_elf_init_array_asm_out_constructor): New. (default_elf_fini_array_asm_out_destructor): Likewise. * varasm.c (elf_init_array_section): Likewise. (elf_fini_array_section): Likewise. (get_elf_initfini_array_priority_section): Likewise. (default_elf_init_array_asm_out_constructor): Likewise. (default_elf_fini_array_asm_out_destructor): Likewise. * config/initfini-array.h: New.
[PATCH, middle-end, i386]: Trivial: use copy_addr_to_reg some more.
Hello!
This patch just substitutes copy_to_mode_reg (Pmode, ...) with
copy_addr_to_reg function where appropriate.
2012-03-19 Uros Bizjak ubiz...@gmail.com
* builtins.c (expand_builtin_cexpi): Use copy_addr_to_reg instead of
copy_to_mode_reg (Pmode, ...).
(expand_builtin_frame_address): Ditto.
* expr.c (emit_block_move_via_libcall): Ditto.
(set_storage_via_libcall): Ditto.
* config/i386/i386.c (ix86_expand_movmem): Ditto.
(ix86_expand_setmem): Ditto.
(ix86_trampoline_init): DItto.
* config/i386/i386.md (cmpstrnsi): Ditto.
(allocate_stack): Ditto.
Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline SVN as obvious.
Uros.
Index: config/i386/i386.md
===
--- config/i386/i386.md (revision 185539)
+++ config/i386/i386.md (working copy)
@@ -16073,8 +16073,8 @@
if (!REG_P (out))
out = gen_reg_rtx (SImode);
- addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
- addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
+ addr1 = copy_addr_to_reg (XEXP (operands[1], 0));
+ addr2 = copy_addr_to_reg (XEXP (operands[2], 0));
if (addr1 != XEXP (operands[1], 0))
operands[1] = replace_equiv_address_nv (operands[1], addr1);
if (addr2 != XEXP (operands[2], 0))
@@ -16737,7 +16737,7 @@
}
else
{
- x = copy_to_mode_reg (Pmode, operands[1]);
+ x = copy_addr_to_reg (operands[1]);
if (TARGET_64BIT)
emit_insn (gen_allocate_stack_worker_probe_di (x, x));
else
Index: config/i386/i386.c
===
--- config/i386/i386.c (revision 185539)
+++ config/i386/i386.c (working copy)
@@ -22101,8 +22101,8 @@ ix86_expand_movmem (rtx dst, rtx src, rtx count_ex
gcc_assert (alg != no_stringop);
if (!count)
count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
- destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
- srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
+ destreg = copy_addr_to_reg (XEXP (dst, 0));
+ srcreg = copy_addr_to_reg (XEXP (src, 0));
switch (alg)
{
case libcall:
@@ -22490,7 +22490,7 @@ ix86_expand_setmem (rtx dst, rtx count_exp, rtx va
gcc_assert (alg != no_stringop);
if (!count)
count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
- destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
+ destreg = copy_addr_to_reg (XEXP (dst, 0));
switch (alg)
{
case libcall:
@@ -24368,7 +24368,7 @@ ix86_trampoline_init (rtx m_tramp, tree fndecl, rt
if (ptr_mode == SImode
|| x86_64_zext_immediate_operand (fnaddr, VOIDmode))
{
- fnaddr = copy_to_mode_reg (Pmode, fnaddr);
+ fnaddr = copy_addr_to_reg (fnaddr);
mem = adjust_address (m_tramp, HImode, offset);
emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
Index: builtins.c
===
--- builtins.c (revision 185539)
+++ builtins.c (working copy)
@@ -2613,8 +2613,8 @@ expand_builtin_cexpi (tree exp, rtx target)
op1 = assign_temp (TREE_TYPE (arg), 0, 1, 1);
op2 = assign_temp (TREE_TYPE (arg), 0, 1, 1);
- op1a = copy_to_mode_reg (Pmode, XEXP (op1, 0));
- op2a = copy_to_mode_reg (Pmode, XEXP (op2, 0));
+ op1a = copy_addr_to_reg (XEXP (op1, 0));
+ op2a = copy_addr_to_reg (XEXP (op2, 0));
top1 = make_tree (build_pointer_type (TREE_TYPE (arg)), op1a);
top2 = make_tree (build_pointer_type (TREE_TYPE (arg)), op2a);
@@ -4580,7 +4580,7 @@ expand_builtin_frame_address (tree fndecl, tree ex
if (!REG_P (tem)
! CONSTANT_P (tem))
- tem = copy_to_mode_reg (Pmode, tem);
+ tem = copy_addr_to_reg (tem);
return tem;
}
}
Index: expr.c
===
--- expr.c (revision 185539)
+++ expr.c (working copy)
@@ -1343,8 +1343,8 @@ emit_block_move_via_libcall (rtx dst, rtx src, rtx
pseudos. We can then place those new pseudos into a VAR_DECL and
use them later. */
- dst_addr = copy_to_mode_reg (Pmode, XEXP (dst, 0));
- src_addr = copy_to_mode_reg (Pmode, XEXP (src, 0));
+ dst_addr = copy_addr_to_reg (XEXP (dst, 0));
+ src_addr = copy_addr_to_reg (XEXP (src, 0));
dst_addr = convert_memory_address (ptr_mode, dst_addr);
src_addr = convert_memory_address (ptr_mode, src_addr);
@@ -2719,7 +2719,7 @@ set_storage_via_libcall (rtx object, rtx size, rtx
/* Emit code to copy OBJECT and SIZE into new pseudos. We can then
place those into new pseudos into a VAR_DECL and use them later. */
- object = copy_to_mode_reg (Pmode, XEXP (object, 0));
+ object = copy_addr_to_reg (XEXP (object, 0));
size_mode = TYPE_MODE (sizetype);
size = convert_to_mode (size_mode, size, 1);
Re: PING: PATCH: PR target/46770: Use .init_array/.fini_array sections
On Mon, Mar 19, 2012 at 1:34 PM, DJ Delorie d...@redhat.com wrote: This breaks constructors on pretty much every elf+newlib target, because newlib and gcc both use HAVE_INITFINI_ARRAY (and have for many years) but the tests don't match. GCC puts ctors in .ctors but libgcc is built without support for them (newlib's generated config headers define HAVE_INITFINI_ARRAY, which causes gcc's initini-array.h to set USE_INITFINI_ARRAY, which shuts off libgcc's ctor/dtor support), so they don't run. This should have been fixed by: 2012-02-23 Ulrich Weigand ulrich.weig...@de.ibm.com * acinclude.m4: Use HAVE_INITFINI_ARRAY_SUPPORT instead of HAVE_INITFINI_ARRAY to work around namespace pollution in certain versions of newlib system headers. * config.in: Regenerate. * configure: Regenerate. * config/initfini-array.h: Use HAVE_INITFINI_ARRAY_SUPPORT instead of HAVE_INITFINI_ARRAY. Thanks, Andrew Pinski 2011-08-20 H.J. Lu hongjiu...@intel.com PR target/46770 * config.gcc (tm_file): Add initfini-array.h if .init_arrary/.fini_array are supported. * crtstuff.c: Don't generate .ctors nor .dtors sections if USE_INITFINI_ARRAY is defined. * output.h (default_elf_init_array_asm_out_constructor): New. (default_elf_fini_array_asm_out_destructor): Likewise. * varasm.c (elf_init_array_section): Likewise. (elf_fini_array_section): Likewise. (get_elf_initfini_array_priority_section): Likewise. (default_elf_init_array_asm_out_constructor): Likewise. (default_elf_fini_array_asm_out_destructor): Likewise. * config/initfini-array.h: New.
Re: PING: PATCH: PR target/46770: Use .init_array/.fini_array sections
Sweet! Thanks! We hadn't merged that bit into our tree yet...
Re: AW: [PATCH] eh_personality.cc: unwinding on ARM
On 19.03.2012 18:32, Paul Brook wrote: while I have your attention: what is an virtual unwind frame? ;) No such thing exists. Throwing an exception is a muti-stage process. It requires unwinding the stack frame twice, taking different actions in the process. Forced unwinding and backtracing add extra complications. The _US_* flags tell the PR which stage in the process we're at. IIRC the ARM EABI doesn't officially include forced unwinding, it's something we had to bolt on afterwards. For added fun the ARM EABI defines the set of states/actions somewhat differently to the DWARF unwinder. Forced unwinding is one of the warts that come from interaction between C++ and POSIX. Almost noone really understands how all these bits fit together. Thanx Paul, that one gave me a good laugh. :)) I worked several months (not full-time, only every now and then) to nail this loop down. It's definitely a fix for upstream - saving the sanity of some souls. Peter
Re: Ping: Re: [patch middle-end]: Fix PR/48814 - [4.4/4.5/4.6/4.7 Regression] Incorrect scalar increment result
On Fri, 16 Mar 2012 11:10:48 +0100
Richard Guenther richard.guent...@gmail.com wrote:
On Fri, Mar 16, 2012 at 1:29 AM, Jonathan Wakely
jwakely@gmail.com wrote:
On 15 March 2012 15:40, Richard Guenther wrote:
On Thu, Mar 15, 2012 at 4:22 PM, Kai Tietz
ktiet...@googlemail.com wrote:
Richard,
ping. I think now could be a good time for applying the patch you
have for this issue as we are in stage 1.
It will still regress the two libstdc++ testcases (well, I guess
so at least).
Jonathan - you didn't answer my reply to your question? Would it
be ok to apply this patch with leaving the regressions in-place,
to be investigated by libstdc++ folks?
Sorry, I've either forgotten or missed the reply - but if you think
the problem is in libstdc++ then certainly go ahead and apply it,
I'll investigate the libstdc++ problems (and ask for help if they
defeat me!)
Ok. I'll do so after re-testing the patch.
FYI, here is the patch for the new libstdc++ fails.
-benjamin
2012-03-19 Benjamin Kosnik b...@redhat.com
* include/ext/pb_ds/detail/pat_trie_/
constructors_destructor_fn_imps.hpp: Increment after recursion.
* include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp: Convert
node_type markup from brief.
diff --git a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp
index 8370a2e..c5748ec 100644
--- a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp
+++ b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/constructors_destructor_fn_imps.hpp
@@ -1,6 +1,6 @@
// -*- C++ -*-
-// Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
+// Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
// Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
@@ -188,7 +188,11 @@ recursive_copy_node(node_const_pointer p_ncp)
__try
{
while (child_it != p_icp-end())
- a_p_children[child_i++] = recursive_copy_node(*(child_it++));
+ {
+ a_p_children[child_i] = recursive_copy_node(*(child_it));
+ child_i++;
+ child_it++;
+ }
p_ret = s_inode_allocator.allocate(1);
}
__catch(...)
diff --git a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp
index b7eb024..0a763b5 100644
--- a/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp
+++ b/libstdc++-v3/include/ext/pb_ds/detail/pat_trie_/pat_trie_base.hpp
@@ -1,6 +1,6 @@
// -*- C++ -*-
-// Copyright (C) 2005, 2006, 2009, 2011 Free Software Foundation, Inc.
+// Copyright (C) 2005, 2006, 2009, 2011, 2012 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the terms
@@ -50,7 +50,11 @@ namespace __gnu_pbds
/// Base type for PATRICIA trees.
struct pat_trie_base
{
- /// Three types of nodes.
+ /**
+ * @brief Three types of nodes.
+ *
+ * i_node is used by _Inode, leaf_node by _Leaf, and head_node by _Head.
+ */
enum node_type
{
i_node,
Re: remove wrong code in immed_double_const
Mike Stump mikest...@comcast.net writes: If we're going to remove the assert, we need to define stuff like that. Orthogonal. The rest of the compiler defines what happens, it either is inconsistent, in which case it is by fiat, undefined, or it is consistent, in which case that consistency defines it. The compiler is free to document this in a nice way, or do, what is usually done, which is to assume everybody just knows what it does. Anyway, my point is, this routine doesn't define the data structure, and is _completely_ orthogonal to your concern. It doesn't matter if it zero extends or sign extends or is inconsistent, has bugs, doesn't have bugs, is documented, or isn't documented. In every single one of these cases, the code in the routine I am fixing, doesn't change. That is _why_ it is orthogonal. If it weren't, you'd be able to state a value for which is mattered. You can't, which is why you are wrong. If you think you are not wrong, please state a value for which it matters how it is defined. It isn't orthoganal. immed_double_const and CONST_DOUBLE are currently only defined for 2 HOST_WIDE_INTs. So, as good functions do, immed_double_const asserts that it is not being used out of spec. That's why the code I quoted said the filler bits for CONST_DOUBLE shouldn't matter; this assert is supposed to make sure that we never generate CONST_DOUBLEs like that. (Personally I'd have preferred it if simplify_immed_subreg asserted instead of filling with zeros.) You want to remove that restriction on immed_double_const and CONST_DOUBLE. That is, you want to change their spec. We should only do that if we define what the new semantics are. Richard
[PATCH, i386]: Simplify allocate_stack expander
Hello!
No functional change.
2012-03-19 Uros Bizjak ubiz...@gmail.com
* config/i386/i386.md (allocate_stack): Simplify.
Tested on x86_64-pc-linux-gnu, committed to mainline SVN.
Uros.
Index: i386/i386.md
===
--- i386/i386.md(revision 185541)
+++ i386/i386.md(working copy)
@@ -16729,25 +16729,26 @@
if (CHECK_STACK_LIMIT CONST_INT_P (operands[1])
INTVAL (operands[1]) CHECK_STACK_LIMIT)
-{
- x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, operands[1],
- stack_pointer_rtx, 0, OPTAB_DIRECT);
- if (x != stack_pointer_rtx)
- emit_move_insn (stack_pointer_rtx, x);
-}
+x = operands[1];
else
{
- x = copy_addr_to_reg (operands[1]);
- if (TARGET_64BIT)
-emit_insn (gen_allocate_stack_worker_probe_di (x, x));
- else
-emit_insn (gen_allocate_stack_worker_probe_si (x, x));
- x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, x,
- stack_pointer_rtx, 0, OPTAB_DIRECT);
- if (x != stack_pointer_rtx)
- emit_move_insn (stack_pointer_rtx, x);
+ rtx (*insn) (rtx, rtx);
+
+ x = copy_to_mode_reg (Pmode, operands[1]);
+
+ insn = (TARGET_64BIT
+ ? gen_allocate_stack_worker_probe_di
+ : gen_allocate_stack_worker_probe_si);
+
+ emit_insn (insn (x, x));
}
+ x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, x,
+ stack_pointer_rtx, 0, OPTAB_DIRECT);
+
+ if (x != stack_pointer_rtx)
+emit_move_insn (stack_pointer_rtx, x);
+
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE;
})
Re: RFA: consolidate DWARF strings into libiberty
On Mon, Mar 19, 2012 at 9:09 AM, Doug Evans d...@google.com wrote: On Thu, Mar 15, 2012 at 12:02 PM, Tom Tromey tro...@redhat.com wrote: DJ == DJ Delorie d...@redhat.com writes: Tom Finally, there is already stuff in libiberty not related to Tom portability. E.g., hashtab or the demangler. DJ Yeah, I know, hence my Should I give up that premise? Yeah. I am not sure there will ever be enough shared code to warrant a new library, particularly because adding a new library is so expensive -- not just the configury stuff but also adding it to the link lines in the Makefiles of all the tools that might need it. I suppose if I had my wish list implemented here, it would be to remove the portability stuff from libiberty in favor of gnulib, and keep libiberty as a higher-level library. That won't really fix libiberty being an ever growing kitchen sink. How hard would it really be to make it easier to add new libraries? It's not like we're expecting 100. But given the pushback for even one new library, I think we're unnecessarily slowing ourselves down. btw, While I like using gnulib more, do we know it will necessarily always solve portability problems in a timely manner? I wouldn't mind keeping libiberty as a fallback. Plus, some of the complexity of libiberty is supporting all of $build,$host,$target in one build. The utilities I think you're thinking of adding (or at least the utilities I've come across as wanting to add to a more useful location) are just for the tools (i.e. $host). Putting them in libiberty doesn't feel right.
Re: remove wrong code in immed_double_const
On Mar 19, 2012, at 2:44 PM, Richard Sandiford wrote:
Mike Stump mikest...@comcast.net writes:
If we're going to remove the assert, we need to define stuff like
that.
Orthogonal. The rest of the compiler defines what happens, it either
is inconsistent, in which case it is by fiat, undefined, or it is
consistent, in which case that consistency defines it. The compiler
is free to document this in a nice way, or do, what is usually done,
which is to assume everybody just knows what it does. Anyway, my
point is, this routine doesn't define the data structure, and is
_completely_ orthogonal to your concern. It doesn't matter if it zero
extends or sign extends or is inconsistent, has bugs, doesn't have
bugs, is documented, or isn't documented. In every single one of
these cases, the code in the routine I am fixing, doesn't change.
That is _why_ it is orthogonal. If it weren't, you'd be able to state
a value for which is mattered. You can't, which is why you are wrong.
If you think you are not wrong, please state a value for which it
matters how it is defined.
immed_double_const and CONST_DOUBLE are currently
only defined for 2 HOST_WIDE_INTs.
I don't happen to share your view. The routine is defined by documentation.
The documentation might exist in a .texi file, in this case there is no texi
file for immed_double_const I don't think, next up, it is defined by the
comments before the routine. In this case, it isn't so defined.
The current definition reads:
/* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
of ints: I0 is the low-order word and I1 is the high-order word.
Do not use this routine for non-integer modes; convert to
REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */
which, is is fine, and I don't _want_ to change that definition of the routine.
I can't fix it, because it isn't broken. If it were, you would be able to
state a case where the new code behaves in a manor inconsistent with the
definition, since there is none you cannot state one, and this is _why_ you
have failed to state such a case. If you disagree, please state the case.
Now, if you review comment is, could you please update the comments in the
routine, I would just say, oh, sure:
Index: emit-rtl.c
===
--- emit-rtl.c (revision 184563)
+++ emit-rtl.c (working copy)
@@ -525,10 +525,9 @@ immed_double_const (HOST_WIDE_INT i0, HO
1) If GET_MODE_BITSIZE (mode) = HOST_BITS_PER_WIDE_INT, then we use
gen_int_mode.
- 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of
- the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only
- from copies of the sign bit, and sign of i0 and i1 are the same), then
- we return a CONST_INT for i0.
+ 2) If the value of the integer fits into HOST_WIDE_INT anyway
+ (i.e., i1 consists only from copies of the sign bit, and sign
+ of i0 and i1 are the same), then we return a CONST_INT for i0.
3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
if (mode != VOIDmode)
{
@@ -540,8 +539,6 @@ immed_double_const (HOST_WIDE_INT i0, HO
if (GET_MODE_BITSIZE (mode) = HOST_BITS_PER_WIDE_INT)
return gen_int_mode (i0, mode);
-
- gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT);
}
/* If this integer fits in one word, return a CONST_INT. */
Sorry I missed it. Now, on to CONST_DOUBLE. It does appear in a texi file:
@findex const_double
@item (const_double:@var{m} @var{i0} @var{i1} @dots{})
Represents either a floating-point constant of mode @var{m} or an
integer constant too large to fit into @code{HOST_BITS_PER_WIDE_INT}
bits but small enough to fit within twice that number of bits (GCC
does not provide a mechanism to represent even larger constants). In
the latter case, @var{m} will be @code{VOIDmode}.
@findex CONST_DOUBLE_LOW
If @var{m} is @code{VOIDmode}, the bits of the value are stored in
@var{i0} and @var{i1}. @var{i0} is customarily accessed with the macro
@code{CONST_DOUBLE_LOW} and @var{i1} with @code{CONST_DOUBLE_HIGH}.
Here again, I don't want to change the definition. The current definition
applies and I am merely making the code conform to it. It says that
CONST_DOUBLE is used when the _value_ of the constant is too large to fit into
HOST_BITS_PER_WIDE_INT bits.
So, if you disagree with me, you will necessarily have to quote the definition
you are using, explain what the words mean to you _and_ state a specific case
in which the code post modification doesn't not conform with the existing
definition. You have failed yet again
[google/4.6] Fix problems with -gfission (issue5844043)
This is for the google/gcc-4_6 branch only. This revised patch fixes several problems with -gfission: - Bad index for range list in the compile unit DIE. - DW_AT_ranges attribute for compile unit in the wrong file. - Incorrect size for skeleton type unit DIEs. - Wrote location expression using DW_OP_addr to DWO file. - Emitted skeleton debug section even when there is no debug info. It also addresses a problem with the previous patch that resulted in an ICE when a location expression is removed after creating an addr_table entry for it. Tested: bootstrap, core, mantle, crust (in progress). 2012-03-19 Sterling Augustine saugust...@google.com Cary Coutant ccout...@google.com * dwarf2out.c (dwarf_stack_op_name): Add DW_OP_GNU_addr_index. (new_loc_descr): Initialize val_index. (size_of_loc_descr): Add DW_OP_GNU_addr_index. (output_loc_operands): Likewise. (output_loc_operands_raw): Likewise. (build_cfa_loc): Initialize val_index. (new_addr_loc_descr): New function. (add_AT_flag): Initialize val_index. (add_AT_int): Likewise. (add_AT_unsigned): Likewise. (add_AT_double): Likewise. (add_AT_vec): Likewise. (add_AT_data8): Likewise. (add_AT_string): Likewise. (add_AT_die_ref): Likewise. (add_AT_fde_ref): Likewise. (add_AT_loc): Likewise. (add_AT_loc_list): Likewise. (add_addr_table_entry): Change if to assert. (remove_addr_table_entry): New function. (add_AT_addr): Add force_direct parameter; adjust all callers. Initialize val_index. (add_AT_file): Initialize val_index. (add_AT_vms_delta): Likewise. (add_AT_lbl_id): Add force_direct parameter; adjust all callers. Initialize val_index. (add_AT_lineptr): Initialize val_index. (add_AT_macptr): Likewise. (add_AT_offset): Likewise. (add_AT_range_list): Add force_direct parameter; adjust all callers. Initialize val_index. (size_of_die): Check for AT_index. (value_format): Likewise. (output_attr_index_or_value): Likewise. (output_die): Fix format warning. (add_top_level_skeleton_die_attrs): Don't add DW_AT_stmt_list here. (get_skeleton_type_unit): New function. (output_skeleton_debug_sections): Add comp_unit parameter; adjust caller; don't generate debug_skeleton_info_section_label or debug_skeleton_abbrev_section_label here; call get_skeleton_type_unit. (output_comdat_type_unit): Remove assert; call get_skeleton_type_unit. (add_ranges_by_labels): Add force_direct parameter; adjust callers. (address_of_int_loc_descriptor): Initialize val_index. (mem_loc_descriptor): Initialize val_index; call new_addr_loc_descr. (implicit_ptr_descriptor): Don't generate DW_OP_GNU_implicit_pointer when splitting debug info. Initialize val_index. (loc_descriptor): Initialize val_index; call new_addr_loc_descr. (loc_list_from_tree): Likewise. (add_const_value_attribute): Likewise. (dwarf2out_init): Generate debug_skeleton_info_section_label and debug_skeleton_abbrev_section_label here. (output_indirect_string): Check for DW_FORM_strp instead of label and refcount. (output_addr_table): Check for removed entries, handle dw_val_class_loc. (resolve_addr_in_expr): Handle DW_OP_GNU_addr_index. (resolve_addr): Remove entry from addr_table if necessary. (hash_loc_operands): Add DW_OP_GNU_addr_index. (compare_loc_operands): Likewise. (dwarf2out_finish): Put DW_AT_low_pc, DW_AT_high_pc, DW_AT_ranges, DW_AT_stmt_list, DW_AT_macptr in skeleton comp_unit DIE; write skeleton debug sections if regular debug section emitted. Index: dwarf2out.c === --- dwarf2out.c (revision 18) +++ dwarf2out.c (working copy) @@ -4779,6 +4779,8 @@ dwarf_stack_op_name (unsigned int op) return DW_OP_GNU_encoded_addr; case DW_OP_GNU_implicit_pointer: return DW_OP_GNU_implicit_pointer; +case DW_OP_GNU_addr_index: + return DW_OP_GNU_addr_index; default: return OP_unknown; @@ -4797,8 +4799,10 @@ new_loc_descr (enum dwarf_location_atom descr-dw_loc_opc = op; descr-dw_loc_oprnd1.val_class = dw_val_class_unsigned_const; + descr-dw_loc_oprnd1.val_index = -1U; descr-dw_loc_oprnd1.v.val_unsigned = oprnd1; descr-dw_loc_oprnd2.val_class = dw_val_class_unsigned_const; + descr-dw_loc_oprnd2.val_index = -1U; descr-dw_loc_oprnd2.v.val_unsigned = oprnd2; return descr; @@ -4897,6 +4901,9 @@ size_of_loc_descr (dw_loc_descr_ref loc) case DW_OP_addr: size += DWARF2_ADDR_SIZE; break; +case DW_OP_GNU_addr_index: + size += size_of_uleb128 (loc-dw_loc_oprnd1.v.val_unsigned);
