[COMMITTED] Add two new methods to Value_Range.

This is for upcoming work in this area. gcc/ChangeLog: * value-range.h (Value_Range::Value_Range): New. (Value_Range::contains_p): New. --- gcc/value-range.h | 9 + 1 file changed, 9 insertions(+) diff --git a/gcc/value-range.h b/gcc/value-range.h index

[COMMITTED] Constify invariant fields of vrange and irange.

The discriminator in vrange cannot change after construction, similarly the number of allocated ranges in an irange. It's best to make them constant to avoid invalid changes. gcc/ChangeLog: * value-range.h (class vrange): Make m_discriminator const. (class irange): Make

[PATCH-1, rs6000] xfail float128 comparison test case that fails on powerpc64 [PR108728]

Hi, This patch xfails a float128 comparison test case on powerpc64 that fails due to a longstanding issue with floating-point compares. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58684 for more information. The case is xfailed when instructions of float128 hardware are generated.

[PATCH-2, rs6000] Add ppc_cpu_supports_hw into proc is-effective-target-keyword [PR108728]

Hi, This patch adds ppc_cpu_supports_hw into explicit name checking in proc is-effective-target-keyword. So ppc_cpu_supports_hw can be used as a target selector in test directives. The patch passed regression test on Power Linux platforms. Thanks Gui Haochen ChangeLog rs6000: Add

[PATCH] RISC-V: Fix PR109535

From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function. (pass_vsetvl::cleanup_insns): Fix bug. --- gcc/config/riscv/riscv-vsetvl.cc | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git

Re: [pushed][PATCH v2] LoongArch: Add built-in functions description of LoongArch Base instruction set instructions.

Pushed to r14-14. 在 2023/4/7 下午4:38, Lulu Cheng 写道: gcc/ChangeLog: * doc/extend.texi: Add section for LoongArch Base Built-in functions. --- gcc/doc/extend.texi | 129 1 file changed, 129 insertions(+) --- v1 -> v2: (1) Does not

Re: [pushed][PATCH] LoongArch: Remove the definition of the macro LOGICAL_OP_NON_SHORT_CIRCUIT under the architecture and use the default definition instead.

Pushed to r14-15. Due to my reasons, this modification did not catch up with the creation of the releases/gcc-13 branch, can I still submit this modification to releases/gcc-13?:-( 在 2023/4/13 下午8:24, Xi Ruoyao 写道: On Thu, 2023-04-13 at 19:51 +0800, Lulu Cheng wrote: In some cases,

RE: [PATCH] RISC-V: Allow Vector IOR(V1, NOT V1) optimiztion

Passed the X86 bootstrap and regression tests. Pan -Original Message- From: Li, Pan2 Sent: Monday, April 17, 2023 10:50 PM To: gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; rguent...@suse.de; Li, Pan2 ; Wang, Yanzhang ; richard.sandif...@arm.com Subject:

Re: [PATCH V1 1/1] UNRATIFIED RISC-V: Add 'ZiCond' extension

On 2/9/23 04:06, shiyul...@iscas.ac.cn wrote: From: yulong [DO NOT MERGE] Until 'ZiCond' extension is frozen/ratified and final version number is determined, this patch should not be merged upstream. This commit uses version 1.0 as in the documentation. This commit adds support for the

Re: [PATCH 3/3] RISC-V: make the stack manipulation codes more readable.

On 12/1/22 03:03, Fei Gao wrote: gcc/ChangeLog: * config/riscv/riscv.cc (riscv_first_stack_step): make codes more readable. (riscv_expand_epilogue): likewise. Thanks. I fixed up the capitalization and one or two whitespace errors and pushed this patch to the trunk.

Re: [PATCH 2/3] RISC-V: optimize stack manipulation in save-restore

On 12/1/22 03:03, Fei Gao wrote: The stack that save-restore reserves is not well accumulated in stack allocation and deallocation. This patch allows less instructions to be used in stack allocation and deallocation if save-restore enabled. before patch: bar: call

Re: ping Re: [PATCH 3/3] Fortran: Fix mpz and mpfr memory leaks

On Mon, Apr 17, 2023 at 09:47:50PM +0200, Bernhard Reutner-Fischer via Fortran wrote: > Ping! > > Harald fixed the leak in set_exponent in the meantime. > As stated in the cover-letter, it was bootstrapped and regtested > without regression on x86_64-foo-linux. > > I consider it obvious, but

[PATCH 2/2] PHIOPT: add folding/simplification detail to the dump

While debugging PHI-OPT with match-and-simplify, I found that adding more dumping to the debug dumps made it easier to understand what was going on rather than stepping in the debugger so this adds them. Note I used TDF_FOLDING rather than TDF_DETAILS as these debug messages can be chatty and only

[PATCH 1/2] PHIOPT: small cleanup in match_simplify_replacement

We know that the statement we are moving is already have a SSA_NAME on the lhs so we don't need to check that and can also just call reset_flow_sensitive_info with the name we already got. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: *

Re: [PATCH] c++: bound ttp level lowering [PR109531]

On 4/17/23 14:44, Patrick Palka wrote: Here when level lowering the bound ttp TT via the substitution T=C, we're neglecting to canonicalize (and therefore strip of simple typedefs) the resulting template arguments {A} before determining its new canonical type via hash table lookup. This leads

Re: [PATCH] aarch64: Add the cost and scheduling models for Neoverse N1

Hi, Kyrylo. > Em 11 de abr. de 2023, à(s) 04:41, Kyrylo Tkachov > escreveu: > >> -Original Message- >> From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org >> > On Behalf Of Evandro >> Menezes via Gcc-patches >> Sent:

[PATCH] Introduce VIRTUAL_REGISTER_P and VIRTUAL_REGISTER_NUM_P predicates

These two predicates are similar to existing HARD_REGISTER_P and HARD_REGISTER_NUM_P predicates and return 1 if the given register corresponds to a virtual register. gcc/ChangeLog: * rtl.h (VIRTUAL_REGISTER_P): New predicate. (VIRTUAL_REGISTER_NUM_P): Ditto. (REGNO_PTR_FRAME_P): Use

ping Re: [PATCH 3/3] Fortran: Fix mpz and mpfr memory leaks

Ping! Harald fixed the leak in set_exponent in the meantime. As stated in the cover-letter, it was bootstrapped and regtested without regression on x86_64-foo-linux. I consider it obvious, but never the less, OK for trunk (as in gcc-14) so far? thanks, On Mon, 03 Apr 2023 23:42:06 +0200

Re: [PATCH v4 00/10] RISC-V: Add autovec support

On Mon, 17 Apr 2023 11:36:51 PDT (-0700), colli...@rivosinc.com wrote: This series of patches adds foundational support for RISC-V auto-vectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the

Re: [PATCH] RISC-V: Clean up the pr106602.c testcase

On Tue, 11 Apr 2023 14:01:06 PDT (-0700), gcc-patches@gcc.gnu.org wrote: On 4/11/23 13:03, Palmer Dabbelt wrote: The test case that was added is rv64i-specific, as there's better ways to generate this code on rv32i (where the long/int cast is a NOP) and on rv64i_zba (where we have word

Re: [PATCH] RISC-V: Force ilp32d for the T-Head FMV test

On Tue, 11 Apr 2023 14:01:35 PDT (-0700), gcc-patches@gcc.gnu.org wrote: On 4/11/23 14:10, Palmer Dabbelt wrote: These functions are NOPs on the soft-float ABIs. Since we're already forcing the ISA, let's just force the ABI too. gcc/testsuite/ChangeLog: *

Re: [PATCH] RISC-V: Set the ABI for the RVV tests

On Thu, 13 Apr 2023 08:59:58 PDT (-0700), gcc-patches@gcc.gnu.org wrote: Ok, thanks :) Committed. Palmer Dabbelt 於 2023年4月13日 週四，23:12寫道： The RVV test harness currently sets the ISA according to the target tuple, but doesn't also set the ABI. This just sets the ABI to match the ISA,

[COMMITTED] PHIOPT: Remove gate_hoist_loads prototype

gate_hoist_loads is defined before its usage so there is no reason for the declaration (prototype) to be there. Committed as obvious after a bootstrap/test on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * tree-ssa-phiopt.cc (gate_hoist_loads): Remove prototype. ---

Re: [PATCH] Abstract out calculation of max HWIs per wide int.

On 4/17/23 20:47, Andrew Pinski wrote: On Mon, Apr 17, 2023 at 11:44 AM Aldy Hernandez via Gcc-patches wrote: I'm about to add one more use of the same snippet of code, for a total of 4 identical calculations in the code base. This seems safe enough even before the release, since this

Re: [PATCH] Abstract out calculation of max HWIs per wide int.

On Mon, Apr 17, 2023 at 11:44 AM Aldy Hernandez via Gcc-patches wrote: > > I'm about to add one more use of the same snippet of code, for a total > of 4 identical calculations in the code base. > > This seems safe enough even before the release, since this file hardly > changes and I'm pretty

[COMMITTED] Do not export global ranges from -Walloca pass.

A warning pass should not be exporting global ranges it finds along the way, because that will alter the behavior of future passes. The reason the present behavior was there was because of some long ago forgotten regression in another pass. This regression is no longer there, and if there's ever

[PATCH] c++: bound ttp level lowering [PR109531]

Here when level lowering the bound ttp TT via the substitution T=C, we're neglecting to canonicalize (and therefore strip of simple typedefs) the resulting template arguments {A} before determining its new canonical type via hash table lookup. This leads to an a hash mismatch ICE for the two

[PATCH] Abstract out calculation of max HWIs per wide int.

I'm about to add one more use of the same snippet of code, for a total of 4 identical calculations in the code base. This seems safe enough even before the release, since this file hardly changes and I'm pretty much the only one who's touched it this year. OK for trunk? gcc/ChangeLog:

[PATCH v4 10/10] This patch supports 8 bit auto-vectorization in riscv.

From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add new vector mode * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto *

[PATCH v4 08/10] RISC-V:autovec: Add autovectorization tests for binary integer

2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64. *

[PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.

While working on autovectorizing for the RISCV port I encountered an issue where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode), where GET_MODE_NUNITS is equal to one. Tested on RISCV and

[PATCH v4 06/10] RISC-V:autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. *

[PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv.

From: Kevin Lee Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new condition --- gcc/tree-vect-data-refs.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc index

[PATCH v4 03/10] RISC-V:autovec: Add auto-vectorization support functions

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_classify_vlmul_field): New function. (riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto.

[PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. *

[PATCH v4 04/10] RISC-V:autovec: Add target vectorization hooks

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_option_override): Set riscv_vectorization_factor. (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement

[PATCH v4 01/10] RISC-V: Add new predicates and function prototypes

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_classify_vlmul_field): New external declaration. (riscv_vector_preferred_simd_mode): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_vector_mask_mode_p): Ditto.

[PATCH v4 00/10] RISC-V: Add autovec support

This series of patches adds foundational support for RISC-V auto-vectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization

[PATCH v4 02/10] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH 13-backport 3/3] RISC-V: Force ilp32d for the T-Head FMV test

These functions are NOPs on the soft-float ABIs. Since we're already forcing the ISA, let's just force the ABI too. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmv-fmv.c: Force the ilp32d ABI. (cherry picked from commit c16848ed8f30be952ac0167fd464ae794fa5ac67) ---

[PATCH 13-backport 2/3] RISC-V: Set the ABI for the RVV tests

The RVV test harness currently sets the ISA according to the target tuple, but doesn't also set the ABI. This just sets the ABI to match the ISA, though we should really also be respecting the user's specific ISA to test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp

[PATCH 13-backport 1/3] RISC-V: Clean up the pr106602.c testcase

The test case that was added is rv64i-specific, as there's better ways to generate this code on rv32i (where the long/int cast is a NOP) and on rv64i_zba (where we have word shifts). This renames the original test case and adds two more for those targets. gcc/testsuite/ChangeLog: PR

[PATCH 13-backport 0/3] RISC-V Testsuite Fixes

These had been approved for trunk, but I hadn't gotten around to committing them before the branch. They're on trunk now. They're all pretty trivial test suite fixes. OK for 13? (Also I'm not sure if we're supposed to be using `git cherry-pick -x`)

Re: [PATCH 1/3] RISC-V: add a new parameter in riscv_first_stack_step.

On 12/1/22 03:03, Fei Gao wrote: frame->total_size to remaining_size conversion is done as an independent patch without functionality change as per review comment. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_first_stack_step): add a new function parameter remaining_size.

Re: [PATCH] RISC-V: Update multilib-generator to handle V

On Mon, 17 Apr 2023 08:24:44 PDT (-0700), Palmer Dabbelt wrote: > On Fri, 14 Apr 2023 00:15:07 PDT (-0700), Kito Cheng wrote: >> Wait, take second round review: >> >>> * All extensions were being prefixed with an underscore, which leads to >>> some odd combinations like "rv32gc_v", this just

Re: [PATCH v2 1/1] RISC-V: Optimze the reverse conditions of rotate shift

On 12/6/22 02:11, Feng Wang wrote: From: wangfeng There is no Immediate operand of ins "rol" according to the B-ext, so the immediate operand should be loaded into register at first. But we can convert it to the ins "rori" or "roriw", and then one immediate load ins can be reduced. So I

[PATCH v3] vect: Verify that GET_MODE_UNITS is greater than one for vect_grouped_store_supported

This patch properly guards gcc_assert (multiple_p (m_full_nelts, m_npatterns)) in vec_perm_indices indices (sel, 2, nelt) for VNx1 vectors. Based on the feedback from Richard Biener and Richard Sandiford, multiple_p has been used instead of maybe_lt to compare nelt with the minimum size 2.

Re: [PATCH v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a

On Mon, 17 Apr 2023 at 17:07, Kyrylo Tkachov wrote: > > > > > -Original Message- > > From: Philipp Tomsich > > Sent: Monday, April 17, 2023 11:22 AM > > To: Kyrylo Tkachov > > Cc: gcc-patches@gcc.gnu.org; Di Zhao > > Subject: Re: [PATCH v2] aarch64: disable LDP via tuning structure for

Re: [PATCH] RISC-V: Update multilib-generator to handle V

On Fri, 14 Apr 2023 00:15:07 PDT (-0700), Kito Cheng wrote: Wait, take second round review: * All extensions were being prefixed with an underscore, which leads to some odd combinations like "rv32gc_v", this just adds underscores to the multi-letter extensions. * The input base ISAs were

RE: [PATCH v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a

> -Original Message- > From: Philipp Tomsich > Sent: Monday, April 17, 2023 11:22 AM > To: Kyrylo Tkachov > Cc: gcc-patches@gcc.gnu.org; Di Zhao > Subject: Re: [PATCH v2] aarch64: disable LDP via tuning structure for - > mcpu=ampere1/1a > > OK for backport? > This will be all the way

[PATCH] RISC-V: Allow Vector IOR(V1, NOT V1) optimiztion

From: Pan Li This patch add the optimization for the vector IOR(V1, NOT V1). Assume we have below sample code. vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl) { return __riscv_vmorn_mm_b32(v1, v1, vl); } Before this patch: vsetvli a5,zero,e8,mf4,ta,ma vlm.v

GCC 14.0.0 Status Report (2023-04-17)

Status == The trunk has branched for the GCC 13 release and is now open again for general development, stage 1. Please consider not disrupting it too much during the RC phase of GCC 13 so it is possible to test important fixes for 13.1 on it. Quality Data Priority #

GCC 13.0.1 Status Report (2023-04-17)

Status == We have reached zero P1 regressions today and releases/gcc-13 branch has been created. GCC 13.1-rc1 will be built likely tomorrow. The branch is now frozen for blocking regressions and documentation fixes only, all changes to the branch require a RM approval now. If no show

[PATCH] libstdc++: Implement P2770R0 changes to join_view / join_with_view

This C++23 paper fixes a bug in these views when adapting a certain kind of non-forward range, and we treat it as a DR against C++20. Tested on x86_64-pc-linux-gnu, does this look OK for GCC 13? This is an ABI change for join_view so it'd be unsuitable for backporting later I think :(

Re: [V6][PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

Thanks a lot for the testing, Kees. Jakub, do you have any more comment on the 6th version of the patches? Is it ready for the GCC13 commit? Or we need to delay it to GCC14? This patch has been there waiting for approving for a while, I think that it’s a nice improvement to GCC and also help to

[PATCH (pushed)] ada: bump Library_Version to 14.

gcc/ada/ChangeLog: * gnatvsn.ads: Bump Library_Version to 14. --- gcc/ada/gnatvsn.ads | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/gnatvsn.ads b/gcc/ada/gnatvsn.ads index b6edc9dabed..a0e61e1b189 100644 --- a/gcc/ada/gnatvsn.ads +++ b/gcc/ada/gnatvsn.ads

[PATCH] [www] Move -fstrict-flex-arrays entry

Pushed. The following moves the -fstrict-flex-arrays option mentioning from "Other significant improvements" to "C family" since the option only applies there. --- htdocs/gcc-13/changes.html | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git

GCC 12.2.1 Status Report (2023-04-17)

Status == The gcc-12 branch is open for regression and documentation fixes. It's time to do the annual release from the branch, GCC 12.3, and the planning is to do a release candidate at the start of the first week of May following with the actual release in the second week. Please look

[PATCH] ipa: Fix double reference-count decrements for the same edge (PR 107769, PR 109318)

Hi, It turns out that since addition of the code that can identify globals which are only read from, the code that keeps track of the references can decrement their count for the same calls, once during IPA-CP and then again during inlining. Fixed by adding a special flag to the pass-through

Re: [PATCH v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a

OK for backport? This will be all the way down to GCC10, as I just realized that we need to backport the entire ampere1/1a support to GCC10 (we stopped at GCC11 for some unexplainable reason)... Philipp. On Mon, 17 Apr 2023 at 12:20, Philipp Tomsich wrote: > > Applied to master, thanks! >

Re: [PATCH v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a

Applied to master, thanks! Philipp. On Mon, 17 Apr 2023 at 11:56, Kyrylo Tkachov wrote: > > > > -Original Message- > > From: Philipp Tomsich > > Sent: Friday, April 14, 2023 7:06 PM > > To: gcc-patches@gcc.gnu.org > > Cc: Kyrylo Tkachov ; Philipp Tomsich > > ; Di Zhao > > Subject:

RE: [PATCH v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a

> -Original Message- > From: Philipp Tomsich > Sent: Friday, April 14, 2023 7:06 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Philipp Tomsich > ; Di Zhao > Subject: [PATCH v2] aarch64: disable LDP via tuning structure for - > mcpu=ampere1/1a > > AmpereOne (-mcpu=ampere1)

Re: [PATCH] testsuite: Fix up vect-simd-clone-1[678]f.c tests some more

On Mon, 17 Apr 2023, Jakub Jelinek wrote: > Hi! > > With > make check-gcc check-g++ -j32 -k > RUNTESTFLAGS='--target_board=unix\{-m32,-m32/-mavx,-m32/-mavx512f,-m32/-march=cascadelake,-m64,-m64/-mavx,-m64/-mavx512f,-m64/-march=cascadelake\} > vect.exp=vect-simd-clone*' > the

[PATCH] testsuite: Fix up vect-simd-clone-1[678]f.c tests some more

Hi! With make check-gcc check-g++ -j32 -k RUNTESTFLAGS='--target_board=unix\{-m32,-m32/-mavx,-m32/-mavx512f,-m32/-march=cascadelake,-m64,-m64/-mavx,-m64/-mavx512f,-m64/-march=cascadelake\} vect.exp=vect-simd-clone*' the vect-simd-clone-1[678]f.c tests fail with -m32/-mavx512f and

Re: [PATCH] tree-optimization/109524 - ICE with VRP edge removal

On Mon, Apr 17, 2023 at 08:41:38AM +, Richard Biener wrote: > VRP queues edges to process late for updating global ranges for > __builtin_unreachable. But this interferes with edge removal > from substitute_and_fold. The following deals with this by > looking up the edge with source/dest

[PATCH] tree-optimization/109524 - ICE with VRP edge removal

VRP queues edges to process late for updating global ranges for __builtin_unreachable. But this interferes with edge removal from substitute_and_fold. The following deals with this by looking up the edge with source/dest block indices which do not become stale. For GCC 14 we probably want to

[Ping][PATCH] libstdc++: Add missing functions to [PR79700]

Hi, just checking whether there were any issues with this patch? https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612386.html Otherwise I assume it won't be in GCC13. Thanks, Nathaniel

Re: [PATCH 2/2] libstdc++: Implement range_adaptor_closure from P2387R3 [PR108827]

On Mon, 17 Apr 2023, 05:28 Patrick Palka via Libstdc++, < libstd...@gcc.gnu.org> wrote: > On Fri, 14 Apr 2023, Patrick Palka wrote: > > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk? > > > > PR libstdc++/108827 > > > > libstdc++-v3/ChangeLog: > > > > *

Re: [PATCH] libstdc++: Fix typo in views::as_const's operator() [PR109525]

OK On Mon, 17 Apr 2023, 05:46 Patrick Palka via Libstdc++, < libstd...@gcc.gnu.org> wrote: > PR libstdc++/109525 > > libstdc++-v3/ChangeLog: > > * include/std/ranges (views::_AsConst::operator()): Add > missing const to constant_range test. > *

Re: Re: [PATCH] LoongArch: fix MUSL_DYNAMIC_LINKER

Yes, https://wiki.musl-libc.org/guidelines-for-distributions.html, "Multilib/multi-arch" section of this introduces it. > -Original Messages- > From: "Xi Ruoyao" > Sent Time:2023-04-17 14:36:52 (星期一) > To: "Peng Fan" , gcc-patches@gcc.gnu.org > Cc: chengl...@loongson.cn > Subject: Re:

Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit

On Fri, 14 Apr 2023, Hans-Peter Nilsson wrote: > On Thu, 13 Apr 2023, Richard Biener via Gcc-patches wrote: > > > On Thu, 13 Apr 2023, Richard Sandiford wrote: > > > > > ??? writes: > > > > Yeah, like kito said. > > > > Turns out the tuple type model in ARM SVE is the optimal solution for > >

Re: [PATCH] LoongArch: fix MUSL_DYNAMIC_LINKER

On Mon, 2023-04-17 at 10:39 +0800, Peng Fan wrote: > The system based on musl has no '/lib64', so change it. I like the change. IMO Glibc-based systems should avoid /lib64 as well but it's too late to change it now. Could you provide a link to the Musl doc as a reference? I'd like to include

Re: [PATCH] tree-optimization/109304 - properly handle instrumented aliases

On Fri, 14 Apr 2023, Jan Hubicka wrote: > > On Tue, 4 Apr 2023, Jan Hubicka wrote: > > > > > > On Tue, 28 Mar 2023, Richard Biener wrote: > > > > > > > > > When adjusting calls to reflect instrumentation we failed to handle > > > > > calls to aliases since they appear to have no body. Instead