Re: New Port for RISC-V v2

On Thu, 02 Feb 2017 17:08:06 PST (-0800), Palmer Dabbelt wrote: > On Thu, 02 Feb 2017 09:58:32 PST (-0800), jos...@codesourcery.com wrote: >> On Thu, 2 Feb 2017, Palmer Dabbelt wrote: >> >>> Additionally, here's a diff against wwwdocs. This is really just to check

[PATCH 3/6] RISC-V Port: libgcc

--- libgcc/config.host | 12 + libgcc/config/riscv/atomic.c | 111 + libgcc/config/riscv/crti.S | 1 + libgcc/config/riscv/crtn.S | 1 + libgcc/config/riscv/div.S | 146 libgcc/config/riscv/linux-unwind.h | 89 +++

[PATCH 4/6] RISC-V Port: libatomic

--- libatomic/configure.tgt | 1 + 1 file changed, 1 insertion(+) diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt index 6d77c94..b8af3ab 100644 --- a/libatomic/configure.tgt +++ b/libatomic/configure.tgt @@ -37,6 +37,7 @@ case "${target_cpu}" in ARCH=alpha ;;

New Port for RISC-V v2

Thanks to everyone who reviewed our original patch set. I've tried to CC everyone who provided a review, sorry if I missed anyone! Andrew, Kito and I believe that we've addressed almost all of the feedback from the reviews of our v1 patch set. Since it's been a while we wanted to get a v2 patch

[PATCH 1/6] RISC-V Port: gcc/config/riscv/riscv.c

--- gcc/config/riscv/riscv.c | 4138 ++ 1 file changed, 4138 insertions(+) create mode 100644 gcc/config/riscv/riscv.c diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c new file mode 100644 index 000..834651f --- /dev/null +++

[PATCH 6/6] RISC-V Port: contrib

--- contrib/config-list.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/contrib/config-list.mk b/contrib/config-list.mk index 9833480..0edc8a4 100644 --- a/contrib/config-list.mk +++ b/contrib/config-list.mk @@ -79,6 +79,7 @@ LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \

[PATCH 5/6] RISC-V Port: gcc/testsuite

From: Kito Cheng --- gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C| 2 +- gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 3 +++ gcc/testsuite/gcc.dg/20020312-2.c | 2 ++ gcc/testsuite/gcc.dg/builtin-apply2.c

Re: [PATCH 2/6] RISC-V Port: gcc

On Thu, 02 Feb 2017 10:08:27 PST (-0800), jos...@codesourcery.com wrote: > On Thu, 2 Feb 2017, Palmer Dabbelt wrote: > >> +@table @gcctabopt >> +@item -mbranch-cost=@var{N} >> +@opindex mbranch-cost >> +Set the cost of branches to roughly N instructions. > &g

Re: New Port for RISC-V v2

On Thu, 02 Feb 2017 09:58:32 PST (-0800), jos...@codesourcery.com wrote: > On Thu, 2 Feb 2017, Palmer Dabbelt wrote: > >> Additionally, here's a diff against wwwdocs. This is really just to check >> this >> is all I'm supposed to do, I can submit a proper patch via

Re: [PATCH 2/6] RISC-V Port: gcc

On Thu, 02 Feb 2017 11:17:42 PST (-0800), mer...@debian.org wrote: > On Thu, Feb 02, 2017 at 01:05:13AM -0800, Palmer Dabbelt wrote: > >> diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi >> index 5554d5f..5b14fc4 100644 >> --- a/gcc/doc/contrib.texi >&

Re: New Port for RISC-V v2

On Thu, 02 Feb 2017 13:07:25 PST (-0800), ger...@pfeifer.com wrote: > Hi Palmer, > > On Thu, 2 Feb 2017, Palmer Dabbelt wrote: >> Additionally, here's a diff against wwwdocs. This is really just to >> check this is all I'm supposed to do, I can submit a proper patch via &

Re: [wwwdocs] RISC-V readings and features

Sorry, I must have missed that one. They're committed. Thanks! On Wed, 08 Feb 2017 03:33:19 PST (-0800), ger...@pfeifer.com wrote: > Hi Palmer, > > On Tue, 7 Feb 2017, Palmer Dabbelt wrote: >> These were suggested as part of our review process, but I never got an >> OK

[PATCH] Add RISC-V Maintainers

2017-02-08 Palmer Dabbelt <pal...@dabbelt.com> * MAINTAINERS (CPU Port Maintainers): Add Kito Cheng, Palmer Dabbelt, and Andrew Waterman as the RISC-V maintainers. --- ChangeLog | 5 + MAINTAINERS | 3 +++ 2 files changed, 8 insertions(+) diff --git a/Chang

Re: New Port for RISC-V v3

On Wed, 08 Feb 2017 00:43:09 PST (-0800), ebotca...@adacore.com wrote: >> I believe we're in. Thanks for the help! > > Congratulations. There are a few post-integration items to be done: > > "If the back end is added to the official GCC source repository, the > following are also necessary: > >

[PATCH] Add the RISC-V ELF targets to config-list.mk

2017-02-08 Palmer Dabbelt <pal...@dabbelt.com> * config-list.mk (LIST): Add riscv32-unknown-elf and riscv64-unknown-elf. --- contrib/ChangeLog | 5 + contrib/config-list.mk | 1 + 2 files changed, 6 insertions(+) diff --git a/contrib/ChangeLog b/contrib/Cha

Re: [wwwdocs] RISC-V readings and features

01:33 - > @@ -48,7 +48,7 @@ > > RISC-V support > [2017-02-02] > - Support for the http://riscv.org;>RISC-V ISA was > added, contributed by Palmer Dabbelt and Andrew Waterman. > + Support for the https://riscv.org;>RISC-V ISA was > added, contribu

Re: New Port for RISC-V v3

On Mon, 06 Feb 2017 00:21:36 PST (-0800), ja...@redhat.com wrote: > On Sun, Feb 05, 2017 at 10:38:18AM -0800, Palmer Dabbelt wrote: >> There have been a handful of changes since we submitted our v2 port: >> >> * Some documentation formatting fixes. >> >> * A docu

Re: Mising Patch #2 from the RISC-V v3 Submission

I think this got dropped because it was over the size limit for this mailing list. I've attached a gzip'd version of the patch instead. On Mon, Feb 6, 2017 at 10:53 AM, Palmer Dabbelt <pal...@dabbelt.com> wrote: > Sorry, I'm not sure what happened to this patch. Here's patch #2 f

Re: [PATCH 2/6] RISC-V Port: gcc

On Sun, 05 Feb 2017 21:36:29 PST (-0800), san...@codesourcery.com wrote: > I didn't see a v3 with the documentation patches go by yet, and I had > some nit-picky comments on v2 (in addition to the ones Joseph already > asked for): No problem. > > diff --git a/gcc/doc/invoke.texi

[PATCH 2/2] Alphebetize RISC-V Options section

2017-02-06 Palmer Dabbelt <pal...@dabbelt.com> * docs/inwvoke.texi (RISC-V Options): Alphabetize. --- gcc/ChangeLog | 4 ++ gcc/doc/invoke.texi | 158 ++-- 2 files changed, 83 insertions(+), 79 deletions(-) diff --git

[PATCH 1/2] Use two spaces to separate options in the RISC-V docs

gcc/ChangeLog: 2017-02-06 Palmer Dabbelt <pal...@dabbelt.com> * doc/invoke.texi (RISC-V Options): Use two spaces to separate options. --- gcc/ChangeLog | 5 + gcc/doc/invoke.texi | 12 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git

RISC-V Post-v3 Documentation Fixups

A few problems in the RISC-V documentation were found as part of the submission. Here's some fixes to them, which I'll commit on top of the rest of the RISC-V port which has already been accepted. Thanks for noticing this!

[PATCH 1/6] RISC-V Port: gcc/config/riscv/riscv.c

--- gcc/config/riscv/riscv.c | 4138 ++ 1 file changed, 4138 insertions(+) create mode 100644 gcc/config/riscv/riscv.c diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c new file mode 100644 index 000..834651f --- /dev/null +++

New Port for RISC-V v3

There have been a handful of changes since we submitted our v2 port: * Some documentation formatting fixes. * A documentation typo fix. * Some changes to wwwdocs, which have been mailed to the list. * The port now builds via contrib/config-list.mk. I worked around the warnings in other

[PATCH 3/6] RISC-V Port: libgcc

--- libgcc/config.host | 12 + libgcc/config/riscv/atomic.c | 111 + libgcc/config/riscv/crti.S | 1 + libgcc/config/riscv/crtn.S | 1 + libgcc/config/riscv/div.S | 146 libgcc/config/riscv/linux-unwind.h | 89 +++

[PATCH 4/6] RISC-V Port: libatomic

--- libatomic/configure.tgt | 1 + 1 file changed, 1 insertion(+) diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt index 6d77c94..b8af3ab 100644 --- a/libatomic/configure.tgt +++ b/libatomic/configure.tgt @@ -37,6 +37,7 @@ case "${target_cpu}" in ARCH=alpha ;;

[PATCH 6/6] RISC-V Port: contrib

--- contrib/config-list.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/contrib/config-list.mk b/contrib/config-list.mk index 9833480..0edc8a4 100644 --- a/contrib/config-list.mk +++ b/contrib/config-list.mk @@ -79,6 +79,7 @@ LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \

[PATCH 5/6] RISC-V Port: gcc/testsuite

From: Kito Cheng --- gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C| 2 +- gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 3 +++ gcc/testsuite/gcc.dg/20020312-2.c | 2 ++ gcc/testsuite/gcc.dg/builtin-apply2.c

Re: New Port for RISC-V v3

On Mon, 06 Feb 2017 11:19:56 PST (-0800), ja...@redhat.com wrote: > On Mon, Feb 06, 2017 at 11:18:12AM -0800, Palmer Dabbelt wrote: >> OK, great! I think we're all set: >> >> * Here's the responses to the documentation comments >><https://gcc.gnu.org/ml/gcc

[wwwdocs] RISC-V readings and features

These were suggested as part of our review process, but I never got an OK on them. Am I meant to just commit these? Index: htdocs/backends.html === RCS file: /cvs/gcc/wwwdocs/htdocs/backends.html,v retrieving revision 1.73 diff -u

Re: [PATCH 2/6] RISC-V Port: gcc

On Sat, 14 Jan 2017 02:05:27 PST (-0800), mer...@debian.org wrote: > Palmer Dabbelt wrote: > >> diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h >> new file mode 100644 >> index 000..045f6cc >> --- /dev/null >> +++ b/gcc/config

Re: [PATCH 4/6] RISC-V Port: libsanitizer

On Thu, 12 Jan 2017 15:39:54 PST (-0800), jos...@codesourcery.com wrote: > Have these changes been sent upstream? Although at the present > development stage applying selected changes might be better than a bulk > merge from upstream libsanitizer, they should still go upstream so they > aren't a

Re: [wwwdocs] RISC-V readings and features

On Wed, 01 Mar 2017 05:38:42 PST (-0800), ger...@pfeifer.com wrote: > On Wed, 8 Feb 2017, Gerald Pfeifer wrote: >> Except http://riscv.org actually redirects to https://riscv.org . :-} > > I now made the same update to readings.html as well. > > Applied. Thanks!

[PATCH 6/6] RISC-V Port: gcc/testsuite

From: Kito Cheng --- gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C| 2 +- gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 3 +++ gcc/testsuite/gcc.dg/20020312-2.c | 2 ++ gcc/testsuite/gcc.dg/builtin-apply2.c

New Port for RISC-V

We'd like to submit for inclusion in GCC a port for the RISC-V architecture. The port suffices to build a substantial body of software (including Linux and some 2,000 Fedora packages) and passes most of the gcc and g++ test suites; so, while it is doubtlessly not complete, we think it is far

[PATCH 1/6] RISC-V Port: gcc/config/riscv/riscv.c

This is split from the rest of the gcc submission so I can fit this patch on the mailing list's 200KiB limit. --- gcc/config/riscv/riscv.c | 4157 ++ 1 file changed, 4157 insertions(+) create mode 100644 gcc/config/riscv/riscv.c diff --git

[PATCH 3/6] RISC-V Port: libgcc

From: Andrew Waterman --- libgcc/config.host | 12 ++ libgcc/config/riscv/atomic.c | 111 + libgcc/config/riscv/crti.S | 1 + libgcc/config/riscv/crtn.S | 1 + libgcc/config/riscv/div.S | 146

[PATCH 4/6] RISC-V Port: libsanitizer

--- libsanitizer/sanitizer_common/sanitizer_linux.cc | 5 + libsanitizer/sanitizer_common/sanitizer_platform.h | 4 ++-- libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc | 2 +- libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h | 7

[PATCH 5/6] RISC-V Port: libatomic

From: Andrew Waterman --- libatomic/configure.tgt | 1 + 1 file changed, 1 insertion(+) diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt index 6d77c94..b8af3ab 100644 --- a/libatomic/configure.tgt +++ b/libatomic/configure.tgt @@ -37,6 +37,7 @@ case

Re: [PATCH] RISC-V documentation cleanups

On Tue, 14 Mar 2017 13:29:22 PDT (-0700), ger...@pfeifer.com wrote: > On Mon, 13 Mar 2017, Palmer Dabbelt wrote: >> A recent mailing list post about install.texi cleanup suggested I >> take a look at ours, and there were a few problems: >> >> * N

[PATCH] RISC-V: Don't prefer FP_REGS for integers

files changed, 6 insertions(+), 13 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index de32689..5e90179 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-03-17 Palmer Dabbelt <pal...@dabbelt.com> + PR target/79912 + * config/r

[PATCH] Disable test inapplicable to RISC-V

From: Andrew Waterman The test is coupled to the branch cost model. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/ssa-thread-14.c: Adjust target selector. --- gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-14.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH] Use more conservative fences on RISC-V

microarchitecutres because they treat all fences conservatively. gcc/ChangeLog: 2017-03-17 Palmer Dabbelt <pal...@dabbelt.com> * config/riscv/riscv.c (riscv_print_operand): Use "fence iorw,ow". * config/riscv/sync.mc (mem_thread_fence_1): Use "fence

Re: [PATCH] Add RISC-V Maintainers

Whoops, I guess I dropped the ball on this one. Committed. On Sun, 19 Mar 2017 02:19:07 PDT (-0700), kito.ch...@gmail.com wrote: > ping. > > On Thu, Feb 9, 2017 at 2:50 AM, Palmer Dabbelt <pal...@dabbelt.com> wrote: >> 2017-02-08 Palmer Dabbelt <pal...@dabbelt.com>

Re: [PATCH] RISC-V: Don't prefer FP_REGS for integers

On Fri, 17 Mar 2017 15:54:16 PDT (-0700), Palmer Dabbelt wrote: > On RISC-V we can't store integers in floating-point registers as this is > forbidden by the ISA. We've always disallowed this, but we were > setting the preferred mode to FP_REGS for some integer modes. This > ca

Re: [PATCH] Disable test inapplicable to RISC-V

On Fri, 17 Mar 2017 15:52:50 PDT (-0700), Palmer Dabbelt wrote: > From: Andrew Waterman <and...@sifive.com> > > The test is coupled to the branch cost model. > > gcc/testsuite/ChangeLog: > > * gcc.dg/tree-ssa/ssa-thread-14.c: Adjust target selector. > --- >

Re: [PATCH] Use more conservative fences on RISC-V

On Fri, 17 Mar 2017 15:52:54 PDT (-0700), Palmer Dabbelt wrote: > The RISC-V memory model is still in the process of being formally > specified, so for now we're going to be safe and add the I/O bits to > userspace fences because there's no way to know if userspace is touching > memor

Re: FIx riscv port building with the trunk

On Mon, 13 Mar 2017 10:50:28 PDT (-0700), l...@redhat.com wrote: > > RISCV targets were failing to build due to implicit-fallthru warnings. > > This changes comments which indicated expected fallthru to use the > attribute and the port builds again. I assume something about the use > of the cpp

Re: FIx riscv port building with the trunk

_((fallthrough)); > + gcc_fallthrough (); > > UNORDERED_COMPARISON(UNGE, lt) > #undef UNORDERED_COMPARISON > > On Tue, Mar 14, 2017 at 2:22 AM, Palmer Dabbelt <pal...@dabbelt.com> wrote: >> On Mon, 13 Mar 2017 10:50:28 PDT (-0700), l...@redhat.com wrote: >

Re: [BUILDROBOT] RISC-V: ‘profile_probability’ has not been declared

On Thu, 13 Jul 2017 13:43:52 PDT (-0700), l...@redhat.com wrote: > On 07/13/2017 02:39 PM, Jan-Benedict Glaw wrote: >> Hi Jan, >> hi Kito, Palmer and Andrew! >> >> On Thu, 2017-06-29 14:27:41 +0200, Jan Hubicka wrote: >>> this is second step of the profile maintenance revamp. It

Re: [PATCH] [RISCV] Add RTEMS support

It appears to work for me: I can generate a simple no-op executable and link it with multilib. I don't know anything about RTEMS, so I'm just going to trust it'll actually work :). We're not going to have bandwidth to test this, but if you're interested there's some support for running the GCC

[PATCH] RISC-V: Don't built 64-bit multilibs on 32-bit targets

't add the 64-bit multilibs. This fixes the build, but has the disadvantage of making our 32-bit and 64-bit toolchains very different. gcc/ChanegLog: 2017-04-28 Palmer Dabbelt <pal...@dabbelt.com> * config/riscv/t-elf-multilib32: New file. * config/riscv/t-linux-multilib32:

[PATCH] RISC-V: Add Sign/Zero extend patterns for PIC loads

Loads on RISC-V are sign-extending by default, but we weren't telling GCC this in our PIC load patterns. This corrects the problem, and adds a zero-extending pattern as well. gcc/ChangeLog 2017-05-09 Palmer Dabbelt <pal...@dabbelt.com> * config/riscv/riscv.md (ZERO_EXTEN

Re: [PATCH] RISC-V: Don't built 64-bit multilibs on 32-bit targets

On Sun, 30 Apr 2017 16:38:35 PDT (-0700), jos...@codesourcery.com wrote: > On Sat, 29 Apr 2017, Richard Biener wrote: >> On April 29, 2017 3:59:27 AM GMT+02:00, Palmer Dabbelt <pal...@dabbelt.com> >> wrote: >> >We've been telling people that "riscv32-*"

Re: [PATCH] RISC-V: Add -mstrict-align option

On Mon, 01 May 2017 10:08:08 PDT (-0700), san...@codesourcery.com wrote: > On 05/01/2017 09:40 AM, Palmer Dabbelt wrote: >> [snip] >> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt >> index 0466bb2..0422e07 100644 >> --- a/gcc/config/ri

[PATCH] RISC-V: Add -mstrict-align option

ed_access to false. + (riscv_cpu_info_table): Add entry for optimize_size_tune_info. + (riscv_valid_lo_sum_p): Use TARGET_STRICT_ALIGN. + (riscv_option_override): Set riscv_slow_unaligned_access. + * doc/invoke.texi: Add -mstrict-align to RISC-V. + 2017-04-28 Palmer Dabbelt &

Re: [PATCH] RISC-V: Don't built 64-bit multilibs on 32-bit targets

On Mon, 01 May 2017 03:54:49 PDT (-0700), jos...@codesourcery.com wrote: > On Mon, 1 May 2017, Palmer Dabbelt wrote: > >> > Specifically, in such cases the GCC configure option is >> > --enable-target=all to enable 64-bit multilibs for a default-32-bit >> > targe

[PATCH] RISC-V: Unify indention in riscv.md

From: Kito Cheng This contains only whitespace changes. gcc/ChangeLog 2017-05-04 Kito Cheng * config/riscv/riscv.md: Unify indentation. --- gcc/ChangeLog | 4 + gcc/config/riscv/riscv.md | 559

[PATCH] RISC-V: Add -mstrict-align option

From: Andrew Waterman The RISC-V user ISA permits misaligned accesses, but they may trap and be emulated. That emulation software needs to be compiled assuming strict alignment. Even when strict alignment is not required, set SLOW_UNALIGNED_ACCESS based upon -mtune to avoid

Re: [PATCH] RISC-V: Add -mstrict-align option

On Thu, 04 May 2017 05:40:35 PDT (-0700), Palmer Dabbelt wrote: > From: Andrew Waterman <and...@sifive.com> > > The RISC-V user ISA permits misaligned accesses, but they may trap > and be emulated. That emulation software needs to be compiled assuming > strict alignment.

Re: [PATCH] RISC-V: Unify indention in riscv.md

On Thu, 04 May 2017 05:40:29 PDT (-0700), Palmer Dabbelt wrote: > From: Kito Cheng <kito.ch...@gmail.com> > > This contains only whitespace changes. > > gcc/ChangeLog > > 2017-05-04 Kito Cheng <kito.ch...@gmail.com> > > * config/riscv/riscv.md: Un

Re: [RFC][PATCH] Remove SLOW_BYTE_ACCESS

On Fri, 17 Nov 2017 11:01:21 PST (-0800), wilco.dijks...@arm.com wrote: Remove SLOW_BYTE_ACCESS given it's confusing, badly named, badly documented and used incorrectly. Although most targets define it as 1, there are several targets which confuse it (based on comments next to it) and set it to

Re: [patches] Re: [PATCH] RISC-V: Implement __umulsidi3, umul_ppmm and __muluw3

On Sun, 19 Nov 2017 23:31:56 PST (-0800), ja...@redhat.com wrote: On Sun, Nov 19, 2017 at 08:53:00PM -0800, Jim Wilson wrote: > 2017-11-24 Kito Cheng > > * longlong.h [__riscv] (__umulsidi3): Define. > [__riscv] (umul_ppmm) Likewise. > [__riscv]

Re: [patches] Re: [PATCH] RISC-V: Add Jim Wilson as a maintainer

On Tue, 07 Nov 2017 09:53:12 PST (-0800), Palmer Dabbelt wrote: On Tue, 07 Nov 2017 09:47:37 PST (-0800), Jim Wilson wrote: On Mon, Nov 6, 2017 at 6:39 PM, Palmer Dabbelt <pal...@dabbelt.com> wrote: +riscv port Jim Wilson <j...@sifive.com> It is

[PATCH] RISC-V: Implement __umulsidi3, umul_ppmm and __muluw3

From: Kito Cheng 2017-11-17 Kito Cheng * longlong.h [__riscv] (__umulsidi3): Define. [__riscv] (umul_ppmm) Likewise. [__riscv] (__muluw3) Likewise. --- include/longlong.h | 50

Re: [PATCH] RISC-V: Handle non-legitimate address in riscv_legitimize_move

Committed. On Thu, 02 Nov 2017 09:03:19 PDT (-0700), Palmer Dabbelt wrote: > From: Kito Cheng <kito.ch...@gmail.com> > > GCC may generate non-legitimate address due to we allow some > load/store with non-legitimate address in pic.md. > > gcc/ChangeLog > > 20

Re: [PATCH] RISC-V: Document the medlow and medany code models

On Wed, 01 Nov 2017 14:59:43 PDT (-0700), jos...@codesourcery.com wrote: > On Tue, 31 Oct 2017, Palmer Dabbelt wrote: > >> +between absolute addresses -2 GiB and +2 GiB. Programs can be statically or > > That should be @minus{}2 GiB, to get a minus sign instead of a hyphen

Re: [PATCH] RISC-V: Document the medlow and medany code models

On Wed, 01 Nov 2017 15:07:59 PDT (-0700), jos...@codesourcery.com wrote: > On Wed, 1 Nov 2017, Palmer Dabbelt wrote: > >> On Wed, 01 Nov 2017 14:59:43 PDT (-0700), jos...@codesourcery.com wrote: >> > On Tue, 31 Oct 2017, Palmer Dabbelt wrote: >> > >> >>

[PATCH] RISC-V: Emit "i" suffix for instructions with immediate operands

From: Michael Clark This changes makes GCC asm output use instruction names that are consistent with the RISC-V ISA manual. The assembler accepts immediate-operand instructions without the "i" suffix, so this all worked before, it's just a bit cleaner to match the ISA

[PATCH] RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune

From: Andrew Waterman 2017-11-03 Andrew Waterman * config/riscv/riscv.c (riscv_option_override): Conditionally set TARGET_STRICT_ALIGN based upon -mtune argument. --- gcc/config/riscv/riscv.c | 10 +++--- 1 file changed, 7

[PATCH] RISC-V: Set SLOW_BYTE_ACCESS=1

From: Andrew Waterman When implementing the RISC-V port, I took the name of this macro at face value. It appears we were mistaken in what this means, here's a quote from the SPARC port that better describes what SLOW_BYTE_ACCESS does /* Nonzero if access to memory by

[PATCH] RISC-V: Define MUSL_DYNAMIC_LINKER for riscv

From: Michael Clark Use no suffix at all in the musl dynamic linker name for hard float ABI. Use -sf and -sp suffixes in musl dynamic linker name for soft float and single precision ABIs. The following table outlines the musl interpreter names for the RISC-V ABI names.

[PATCH] RISC-V: Handle non-legitimate address in riscv_legitimize_move

From: Kito Cheng GCC may generate non-legitimate address due to we allow some load/store with non-legitimate address in pic.md. gcc/ChangeLog 2017-11-02 Kito Cheng * config/riscv/riscv.c (riscv_legitimize_move): Handle

[PATCH] RISC-V: Add Jim Wilson as a maintainer

everyone use our proper email address. ChangeLog 2017-11-06 Palmer Dabbelt <pal...@sifive.com> * MAINTAINERS (RISC-V): Add Jim Wilson as a maintainer. Use my SiFive email address. --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAI

[PATCH] RISC-V: Fix build error

From: Kito Cheng - This build error was indroduced by "RISC-V: Implement movmemsi" and "RISC-V: Support -mpreferred-stack-boundary flag" gcc/ChangeLog 2017-11-07 Kito Cheng * config/riscv/riscv-protos.h

Re: [PATCH] RISC-V: Implement movmemsi

Committed. On Mon, 06 Nov 2017 17:31:05 PST (-0800), Palmer Dabbelt wrote: > From: Andrew Waterman <and...@sifive.com> > > Without this we aren't getting proper memcpy inlining on RISC-V systems, > which is particularly disastrous for Dhrystone performance on RV32IM > syste

Re: [PATCH] RISC-V: Fix build error

Committed. Thanks, Kito :). On Tue, 07 Nov 2017 15:20:05 PST (-0800), Palmer Dabbelt wrote: > From: Kito Cheng <kito.ch...@gmail.com> > > - This build error was indroduced by "RISC-V: Implement movmemsi" > and "RISC-V: Support -mpreferred-stack-boundary fl

Re: [PATCH] RISC-V: Document the medlow and medany code models

Committed. On Tue, 31 Oct 2017 23:37:04 PDT (-0700), Andrew Waterman wrote: > Thanks for caring enough about our patches to even notice the grammar :) > > On Tue, Oct 31, 2017 at 11:09 PM, Sandra Loosemore > wrote: >> On 10/31/2017 10:27 PM, Andrew Waterman wrote: >>>

[PATCH] RISC-V: Implement movmemsi

From: Andrew Waterman Without this we aren't getting proper memcpy inlining on RISC-V systems, which is particularly disastrous for Dhrystone performance on RV32IM systems. gcc/ChangeLog 2017-11-06 Andrew Waterman * config/riscv/riscv-protos.h

Re: [patches] Re: [PATCH] RISC-V: Add Jim Wilson as a maintainer

On Tue, 07 Nov 2017 09:47:37 PST (-0800), Jim Wilson wrote: > On Mon, Nov 6, 2017 at 6:39 PM, Palmer Dabbelt <pal...@dabbelt.com> wrote: >> >> +riscv port Jim Wilson <j...@sifive.com> >> >> > It is jimw not jim for the email

Re: [PATCH] RISC-V: Add Jim Wilson as a maintainer

On Tue, 07 Nov 2017 05:02:13 PST (-0800), dje@gmail.com wrote: > On Tue, Nov 7, 2017 at 2:14 AM, Jakub Jelinek <ja...@redhat.com> wrote: >> On Mon, Nov 06, 2017 at 06:39:20PM -0800, Palmer Dabbelt wrote: >>> Jim has recently started working at SiFive, where he'll be con

Re: [PATCH] RISC-V: Define MUSL_DYNAMIC_LINKER for riscv

Committed. On Mon, 06 Nov 2017 11:11:24 PST (-0800), Palmer Dabbelt wrote: > From: Michael Clark <michaeljcl...@mac.com> > > Use no suffix at all in the musl dynamic linker name for hard > float ABI. Use -sf and -sp suffixes in musl dynamic linker name > for soft float and

Re: [PATCH] RISC-V: Set SLOW_BYTE_ACCESS=1

Committed. On Fri, 03 Nov 2017 08:34:38 PDT (-0700), Palmer Dabbelt wrote: > From: Andrew Waterman <and...@sifive.com> > > When implementing the RISC-V port, I took the name of this macro at > face value. It appears we were mistaken in what this means, here's a > quot

Re: [PATCH] RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune

On Fri, 03 Nov 2017 09:14:10 PDT (-0700), Palmer Dabbelt wrote: > From: Andrew Waterman <and...@sifive.com> > > 2017-11-03 Andrew Waterman <and...@sifive.com> > > * config/riscv/riscv.c (riscv_option_override): Conditionally set > TARGET_STRICT_AL

Re: [PATCH] RISC-V: Emit "i" suffix for instructions with immediate operands

Committed, after adding a second space before the email and before the closing comment. On Fri, 03 Nov 2017 09:14:25 PDT (-0700), Palmer Dabbelt wrote: > From: Michael Clark <michaeljcl...@mac.com> > > This changes makes GCC asm output use instruction names that are > consiste

Re: [PATCH] RISC-V: Add Sign/Zero extend patterns for PIC loads

Committed. On Tue, 24 Oct 2017 10:55:46 PDT (-0700), Palmer Dabbelt wrote: > Loads on RISC-V are sign-extending by default, but we weren't telling > GCC this in our PIC load patterns. This corrects the problem, and adds > a zero-extending pattern as well. > > gcc/ChangeLog > &g

[PATCH] RISC-V: Add Sign/Zero extend patterns for PIC loads

Loads on RISC-V are sign-extending by default, but we weren't telling GCC this in our PIC load patterns. This corrects the problem, and adds a zero-extending pattern as well. gcc/ChangeLog 2017-10-24 Palmer Dabbelt <pal...@dabbelt.com> * config/riscv/riscv.md (ZERO_EXTEN

[PATCH] RISC-V: Document the medlow and medany code models

This documentation is patterned off the aarch64 -mcmodel documentation. gcc/ChangeLog: 2017-10-31 Palmer Dabbelt <pal...@dabbelt.com> * doc/invoke.texi (RISC-V Options): Explicitly name the medlow and medany code models, and describe what they do. --- gcc/doc/invoke.tex

Re: libgo patch committed: Add riscv and js/wasm

On Mon, 11 Jun 2018 12:16:39 PDT (-0700), i...@golang.org wrote: This libgo patch add riscv and js/wasm as known targets. This incorporates cut down versions of https://golang.org/cl/102835 and https://golang.org/cl/106256 from the master sources. This will tell the go/build to skip files with

Re: libgo patch committed: Add riscv and js/wasm

On Mon, 11 Jun 2018 20:46:01 PDT (-0700), i...@golang.org wrote: On Mon, Jun 11, 2018 at 12:22 PM, Palmer Dabbelt wrote: On Mon, 11 Jun 2018 12:16:39 PDT (-0700), i...@golang.org wrote: This libgo patch add riscv and js/wasm as known targets. This incorporates cut down versions of https

[PATCH] RISC-V: Correct and improve the "-mabi" documentation

or finding the bug! PR target/82717: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 gcc/ChangeLog 2017-10-26 Palmer Dabbelt <pal...@dabbelt.com> PR target/82717 * doc/invoke.texi (RISC-V) <-mabi>: Correct and improve. --- gcc/doc/invoke.texi | 23 +

Re: [PATCH] RISC-V: Correct and improve the "-mabi" documentation

Committed. On Thu, 26 Oct 2017 09:45:07 PDT (-0700), Palmer Dabbelt wrote: > The documentation for the "-mabi" argument on RISC-V was incorrect. We > chose to treat this as a documentation bug rather than a code bug, and > to make the documentation match what

Re: Mising Patch #2 from the RISC-V v3 Submission

On Mon, 12 Feb 2018 15:18:39 PST (-0800), Jim Wilson wrote: On 02/12/2018 03:23 AM, Andreas Schwab wrote: On Feb 06 2017, Palmer Dabbelt <pal...@dabbelt.com> wrote: +/* Because RISC-V only has word-sized atomics, it requries libatomic where + others do not. So link libatomic by d

Re: [PATCH] Rewrite pic.md to improve medany and pic code size.

On Tue, 28 Aug 2018 19:21:23 PDT (-0700), Jim Wilson wrote: The pic.md file has patterns used only for the medany code model and for pic code. They match an unsplit 2-instruction address load pattern followed by a load or store instruction, and emit an assembler macro that expands to two

Re: [PATCH] Rewrite pic.md to improve medany and pic code size.

On Wed, 29 Aug 2018 09:52:00 PDT (-0700), Jim Wilson wrote: On Wed, Aug 29, 2018 at 9:22 AM, Palmer Dabbelt wrote: Thanks Jim -- I'm afraid at least part of this was my mess, as I had to go add in the ZERO_EXTEND_LOAD hackery to work around some bug in this file that I couldn't figure out how

Re: [PATCH] Update config.guess and config.sub

On Thu, 05 Jul 2018 05:00:20 PDT (-0700), sebastian.hu...@embedded-brains.de wrote: * config.guess: Sync with upstream version 2018-06-26. * config.sub: Sync with upstream version 2018-07-02. --- config.guess | 6 +++--- config.sub | 8 +++- 2 files changed, 10

Re: [PATCH] RISC-V: Add and document the "-mno-relax" option

On Fri, 02 Mar 2018 16:27:41 PST (-0800), Jim Wilson wrote: On 03/01/2018 01:26 PM, Palmer Dabbelt wrote: +@item -mrelax +@itemx -mno-relax +Take advantage of linker relaxations to reduce the number of instructions +required to materalize symbol addresses. materalize->material

[PATCH] RISC-V: Add and document the "-mno-relax" option

From: Palmer Dabbelt <pal...@sifive.com> RISC-V relies on aggressive linker relaxation to get good code size. As a result no text symbol addresses can be known until link time, which means that alignment must be handled during the link. This alignment pass is essentially just another

Re: [RFC] support --with-multilib-list=@/path/name

On Fri, 09 Nov 2018 07:07:06 PST (-0800), ol...@adacore.com wrote: Richard, Olivier tells me he talked to you briefly at the Cauldron about allowing custom multilib sets to be configured from custom Makefile fragments supplied at configure time, and that you was somewhat receptive to the idea.

Re: [PATCH] RISC-V: Add -malign-data= option.

On Tue, 25 Jun 2019 15:58:53 PDT (-0700), pins...@gmail.com wrote: On Tue, Jun 25, 2019 at 3:46 PM Ilia Diachkov wrote: Hello, This patch adds new machine specific option -malign-data={word,abi} to RISC-V port. The option switches alignment of global variables and constants of

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