On Mon, 17 Oct 2022 at 16:02, Prathamesh Kulkarni
wrote:
>
> On Mon, 10 Oct 2022 at 16:18, Prathamesh Kulkarni
> wrote:
> >
> > On Fri, 30 Sept 2022 at 21:38, Richard Sandiford
> > wrote:
> > >
> > > Richard Sandiford via Gcc-patches writes:
> &
On Wed, 26 Oct 2022 at 21:07, Richard Sandiford
wrote:
>
> Sorry for the slow response. I wanted to find some time to think
> about this a bit more.
>
> Prathamesh Kulkarni writes:
> > On Fri, 30 Sept 2022 at 21:38, Richard Sandiford
> > wrote:
> >>
&g
Hi,
The attached prototype patch extends fold_vec_perm to fold VEC_PERM_EXPR
in VLA manner, and currently handles the following cases:
(a) fixed len arg0, arg1 and fixed len sel.
(b) fixed len arg0, arg1 and vla sel
(c) vla arg0, arg1 and vla sel with arg0, arg1 being VECTOR_CST.
It seems to work
On Wed, 17 Aug 2022 at 17:01, Richard Biener wrote:
>
> On Tue, Aug 16, 2022 at 6:30 PM Richard Sandiford
> wrote:
> >
> > Prathamesh Kulkarni writes:
> > > On Tue, 9 Aug 2022 at 18:42, Richard Biener
> > > wrote:
> > >>
> > >> On
On Thu, 18 Aug 2022 at 18:14, Prathamesh Kulkarni
wrote:
>
> On Wed, 17 Aug 2022 at 17:01, Richard Biener
> wrote:
> >
> > On Tue, Aug 16, 2022 at 6:30 PM Richard Sandiford
> > wrote:
> > >
> > > Prathamesh Kulkarni writes:
> > > > On
On Wed, 17 Aug 2022 at 18:09, Prathamesh Kulkarni
wrote:
>
> Hi,
> The attached prototype patch extends fold_vec_perm to fold VEC_PERM_EXPR
> in VLA manner, and currently handles the following cases:
> (a) fixed len arg0, arg1 and fixed len sel.
> (b) fixed len arg0, arg1 and
On Thu, 18 Aug 2022 at 18:20, Prathamesh Kulkarni
wrote:
>
> On Thu, 18 Aug 2022 at 18:14, Prathamesh Kulkarni
> wrote:
> >
> > On Wed, 17 Aug 2022 at 17:01, Richard Biener
> > wrote:
> > >
> > > On Tue, Aug 16, 2022 at 6:30 PM Richard Sandi
On Mon, 29 Aug 2022 at 11:38, Prathamesh Kulkarni
wrote:
>
> On Wed, 17 Aug 2022 at 18:09, Prathamesh Kulkarni
> wrote:
> >
> > Hi,
> > The attached prototype patch extends fold_vec_perm to fold VEC_PERM_EXPR
> > in VLA manner, and currently handles the follow
On Mon, 29 Aug 2022 at 11:53, Prathamesh Kulkarni
wrote:
>
> On Thu, 18 Aug 2022 at 18:20, Prathamesh Kulkarni
> wrote:
> >
> > On Thu, 18 Aug 2022 at 18:14, Prathamesh Kulkarni
> > wrote:
> > >
> > > On Wed, 17 Aug 2022 at 17:01, Richard Biener
On Mon, 5 Sept 2022 at 14:39, Richard Biener wrote:
>
> On Mon, Sep 5, 2022 at 10:54 AM Prathamesh Kulkarni
> wrote:
> >
> > On Mon, 29 Aug 2022 at 11:53, Prathamesh Kulkarni
> > wrote:
> > >
> > > On Thu, 18 Aug 2022 at 18:20, Prathamesh Kulkarni
On Mon, 5 Sept 2022 at 15:51, Richard Sandiford
wrote:
>
> Sorry for the slow reply. I wrote a response a couple of weeks ago
> but I think it get lost in a machine outage.
>
> Prathamesh Kulkarni writes:
> > Hi,
> > The attached prototype patch extends fold_vec
On Mon, 27 Dec 2021 at 15:54, Prathamesh Kulkarni
wrote:
>
> On Fri, 17 Dec 2021 at 17:03, Richard Sandiford
> wrote:
> >
> > Prathamesh Kulkarni writes:
> > > Hi,
> > > The patch folds:
> > > lhs = svld1rq ({-1, -1, -1, ...}, &v[0])
> >
On Tue, 4 Jan 2022 at 19:12, Richard Sandiford
wrote:
>
> Richard Biener writes:
> > On Tue, 4 Jan 2022, Richard Sandiford wrote:
> >
> >> Richard Biener writes:
> >> > On Fri, 17 Dec 2021, Richard Sandiford wrote:
> >> >
> >> >>
On Tue, 3 May 2022 at 18:25, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Tue, 4 Jan 2022 at 19:12, Richard Sandiford
> > wrote:
> >>
> >> Richard Biener writes:
> >> > On Tue, 4 Jan 2022, Richard Sandiford wrote:
> >&g
On Mon, 9 May 2022 at 19:22, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Tue, 3 May 2022 at 18:25, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > On Tue, 4 Jan 2022 at 19:12, Richard Sandiford
>
On Fri, 6 May 2022 at 16:00, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> > b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> > index c24c0548724..1ef4ea2087b 100644
> > --- a/
On Wed, 11 May 2022 at 12:44, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Fri, 6 May 2022 at 16:00, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > diff --git a/gcc/config/aarch64/aarch64-sve-built
Hi,
The attached patch adds another parameter machine_mode op_mode to vec_perm_const
hook to specify mode of input operands. The motivation for doing this
is PR96463,
where we create vec_perm_expr of the form:
lhs = vec_perm_expr
where lhs and rhs have different vector types but same element type
(
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For now, it bails out if vmode != op_mode, in follow-up patch to
PR96463, I will add dup
as exception.
Bootstrapped+tested on aarch64-linux-gnu.
Does it look OK ?
Thanks,
Prathamesh
diff --git a/gcc/config/aarch64
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For rationale, please see:
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
OK to commit if bootstrap+test passes ?
Thanks,
Prathamesh
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For rationale, please see:
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
Bootstrapped+tested on x86_64-linux-gnu.
OK to commit ?
Thanks,
Prathamesh
diff --git a/gcc/config/i386/i386-expand.cc b/gc
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For rationale, please see:
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
OK to commit if bootstrap+test passes ?
Thanks,
Prathamesh
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For rationale, please see:
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
Unfortunately, I am not sure how to cross test this patch.
make all-gcc stage-1 seems to build fine.
Is it OK to commit the
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For rationale, please see:
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
Unfortunately, I am not sure how to cross test this patch.
make all-gcc stage-1 seems to build fine.
Is it OK to commit the
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For rationale, please see:
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
Unfortunately, I am not sure how to cross test this patch.
make all-gcc stage-1 seems to build fine.
Is it OK to commit the
Hi,
The attached patch adjusts vec_perm_const hook to accommodate the new parameter.
For rationale, please see:
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595128.html
Unfortunately, I am not sure how to cross test this patch.
make all-gcc stage-1 seems to build fine.
Is it OK to commit the
On Wed, 18 May 2022 at 17:27, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi,
> > The attached patch adds another parameter machine_mode op_mode to
> > vec_perm_const
> > hook to specify mode of input operands. The motivation for doing this
>
Hi Richard,
The attached patch addresses formatting nits for affected targets.
Tested with make all-gcc stage1 (except for gcn).
Sorry if this sounds like a naive question, but what target triplet
should I use to build gcn port ?
Thanks,
Prathamesh
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/
On Mon, 9 May 2022 at 21:21, Prathamesh Kulkarni
wrote:
>
> On Mon, 9 May 2022 at 19:22, Richard Sandiford
> wrote:
> >
> > Prathamesh Kulkarni writes:
> > > On Tue, 3 May 2022 at 18:25, Richard Sandiford
> > > wrote:
> > >>
> > >>
On Tue, 24 May 2022 at 11:50, Richard Biener via Gcc-patches
wrote:
>
> When facing multiple PHI defs and one feeding the other we can
> postpone processing uses of one and thus can proceed.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
>
> 2022-05-20 Richard Biener
>
>
On Mon, 23 May 2022 at 18:14, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Wed, 18 May 2022 at 17:27, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > Hi,
> >> > The attached patch adds anot
On Fri, 29 Apr 2022 at 19:44, Marek Polacek via Gcc-patches
wrote:
>
> This patch fixes crashes with invalid attributes. Arguably it could
> make sense to assert seen_error() too.
>
> Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk = GCC 13?
>
> PR c++/96637
>
> gcc/ChangeLog:
On Tue, 24 May 2022 at 14:50, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
> > index c5006afc00d..0a3c733ada9 100644
> > --- a/gcc/doc/tm.texi
> > +++ b/gcc/doc/tm.texi
> > @@ -6088,14 +6088,18 @@
On Thu, 2 Sept 2021 at 14:32, Christophe Lyon
wrote:
>
>
>
> On Tue, Aug 24, 2021 at 10:17 AM Kyrylo Tkachov
> wrote:
>>
>>
>>
>> > -Original Message-
>> > From: Prathamesh Kulkarni
>> > Sent: 24 August 2021 09:01
>> >
On Thu, 9 Sept 2021 at 15:38, Roger Sayle wrote:
>
>
> As observed by Jakub in comment #2 of PR 98865, the expression -(a>>63)
> is optimized in GENERIC but not in GIMPLE. Investigating further it
> turns out that this is one of a few transformations performed by
> fold_negate_expr in fold-const.
On Thu, 28 Oct 2021 at 21:33, Martin Sebor wrote:
>
> On 10/28/21 2:59 AM, Prathamesh Kulkarni via Gcc-patches wrote:
> > On Fri, 22 Oct 2021 at 14:41, Prathamesh Kulkarni
> > wrote:
> >>
> >> On Wed, 20 Oct 2021 at 15:05, Richard Sandiford
> >> w
On Thu, 4 Nov 2021 at 14:19, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Wed, 20 Oct 2021 at 15:05, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > On Tue, 19 Oct 2021 at 19:58, Richard Sandiford
&g
Hi,
The attached patch removes redundant check for number of loops in
pass_vectorize::execute,
since it only calls vectorize_loops, and in vectorize_loops, we
immediately bail out if no loops are present:
vect_loops_num = number_of_loops (cfun);
/* Bail out if there are no loops. */
if (vect
On Mon, 8 Nov 2021 at 23:24, Martin Jambor wrote:
>
> Hi,
>
> this patch introduces a helper function build_debug_expr_decl to build
> DEBUG_EXPR_DECL tree nodes in the most common way and replaces with a
> call of this function all code pieces which build such a DECL itself
> and sets its mode to
On Mon, 8 Nov 2021 at 16:42, Richard Biener wrote:
>
> On Mon, Nov 8, 2021 at 12:06 PM Prathamesh Kulkarni via Gcc-patches
> wrote:
> >
> > Hi,
> > The attached patch removes redundant check for number of loops in
> > pass_vectorize::execute,
> > sinc
On Tue, 9 Nov 2021 at 20:27, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Thu, 4 Nov 2021 at 14:19, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > On Wed, 20 Oct 2021 at 15:05, Richard Sandiford
&g
On Fri, 12 Nov 2021 at 01:12, Siddhesh Poyarekar wrote:
>
> Avoid going through another folding cycle and use the ignore flag to
> directly transform BUILT_IN_STPCPY_CHK to BUILT_IN_STRCPY when set,
> likewise for BUILT_IN_STPNCPY_CHK to BUILT_IN_STPNCPY.
>
> Dump the transformation in dump_file s
On Sat, 13 Nov 2021 at 02:00, Seija K. via Gcc-patches
wrote:
>
> diff --git a/gcc/ada/terminals.c b/gcc/ada/terminals.c
> index a2dd4895d48..25d9acda752 100644
> --- a/gcc/ada/terminals.c
> +++ b/gcc/ada/terminals.c
> @@ -609,8 +609,7 @@ __gnat_setup_communication (struct TTY_Process**
> process_
On Sun, 14 Nov 2021 at 02:07, David Malcolm via Gcc-patches
wrote:
>
> This patch adds two new attributes. The followup patch makes use of
> the attributes in -fanalyzer.
>
> gcc/c-family/ChangeLog:
> * c-attribs.c (attr_noreturn_exclusions): Add
> "returns_zero_on_failure" and "r
On Tue, 16 Nov 2021 at 03:42, David Malcolm wrote:
>
> On Mon, 2021-11-15 at 12:33 +0530, Prathamesh Kulkarni wrote:
> > On Sun, 14 Nov 2021 at 02:07, David Malcolm via Gcc-patches
> > wrote:
> > >
> > > This patch adds two new attributes. The followup patch
lr
-.L13:
- .align 3
-.L12:
- .short 0
- .short 0
- .short 0
- .short 0
.size test_vmul_n_16x8, .-test_vmul_n_16x8
Adjusted the test, to fix the failing tests.
OK to commit if testing passes ?
Thanks,
Prathamesh
2021-26-05 Prathamesh Kulkarni
On Wed, 26 May 2021 at 14:07, Marc Glisse wrote:
>
> On Wed, 26 May 2021, Prathamesh Kulkarni via Gcc-patches wrote:
>
> > The attached patch removes calls to builtins in vmul_n* (a, b) with __a *
> > __b.
>
> I am not familiar with neon, but are __a and __b unsigned h
On Mon, 31 May 2021 at 15:22, Prathamesh Kulkarni
wrote:
>
> On Wed, 26 May 2021 at 14:07, Marc Glisse wrote:
> >
> > On Wed, 26 May 2021, Prathamesh Kulkarni via Gcc-patches wrote:
> >
> > > The attached patch removes calls to builtins in vmul_n* (a, b) with _
tested on arm*-*-*.
OK to commit ?
Thanks,
Prathamesh
2021-06-01 Prathamesh Kulkarni
PR target/97906
* config/arm/iterators.md (NEON_VACMP): Remove.
* config/arm/neon.md (neon_vca): Use GLTE instead of GTGE
iterator.
(neon_vca_insn):
Hi,
As mentioned in PR, for the following test-case:
#include
bfloat16x4_t f1 (bfloat16_t a)
{
return vdup_n_bf16 (a);
}
bfloat16x4_t f2 (bfloat16_t a)
{
return (bfloat16x4_t) {a, a, a, a};
}
Compiling with arm-linux-gnueabi -O3 -mfpu=neon -mfloat-abi=softfp
-march=armv8.2-a+bf16+fp16 resu
On Mon, 31 May 2021 at 16:01, Prathamesh Kulkarni
wrote:
>
> On Mon, 31 May 2021 at 15:22, Prathamesh Kulkarni
> wrote:
> >
> > On Wed, 26 May 2021 at 14:07, Marc Glisse wrote:
> > >
> > > On Wed, 26 May 2021, Prathamesh Kulkarni via Gcc-patches wrote:
&
On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
wrote:
>
> Hi,
> As mentioned in PR, for following test-case:
>
> #include
>
> uint32x2_t f1(float32x2_t a, float32x2_t b)
> {
> return vabs_f32 (a) >= vabs_f32 (b);
> }
>
> uint32x2_t f2(float32x2_t a, fl
both produce vceq.f32 with -ffast-math.
Thanks,
Prathamesh
2021-06-09 Prathamesh Kulkarni
* config/arm/arm_neon.h (vceq_s8): Replace builtin with __a == __b.
(vceq_s16): Likewise.
(vceq_s32): Likewise.
(vceq_u8): Likewise.
(vceq_u16): Likewise
On Fri, 4 Jun 2021 at 13:15, Christophe Lyon wrote:
>
> On Fri, 4 Jun 2021 at 09:27, Prathamesh Kulkarni via Gcc-patches
> wrote:
> >
> > Hi,
> > As mentioned in PR, for the following test-case:
> >
> > #include
> >
> > bfloat16x4_t
On Mon, 7 Jun 2021 at 12:45, Prathamesh Kulkarni
wrote:
>
> On Mon, 31 May 2021 at 16:01, Prathamesh Kulkarni
> wrote:
> >
> > On Mon, 31 May 2021 at 15:22, Prathamesh Kulkarni
> > wrote:
> > >
> > > On Wed, 26 May 2021 at 14:07, Marc Gliss
On Mon, 7 Jun 2021 at 12:46, Prathamesh Kulkarni
wrote:
>
> On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
> wrote:
> >
> > Hi,
> > As mentioned in PR, for following test-case:
> >
> > #include
> >
> > uint32x2_t f1(float32x2_t a, float32x2_
On Wed, 9 Jun 2021 at 14:49, Prathamesh Kulkarni
wrote:
>
> Hi,
> The attached patch replaces calls to _builtin_neon_vceq (a, b) with a
> == b
> for integral variants, and for fp variants it gates the equality
> comparison on __FAST_MATH__ because for fp variants a == b result
On Wed, 9 Jun 2021 at 15:58, Prathamesh Kulkarni
wrote:
>
> On Fri, 4 Jun 2021 at 13:15, Christophe Lyon
> wrote:
> >
> > On Fri, 4 Jun 2021 at 09:27, Prathamesh Kulkarni via Gcc-patches
> > wrote:
> > >
> > > Hi,
> > > As mentioned in
Hi,
In gimple_expand_vec_cond_expr:
icode = get_vcond_icode (mode, cmp_op_mode, unsignedp);
if (icode == CODE_FOR_nothing)
{
if (tcode == LT_EXPR
&& op0a == op0)
{
/* A VEC_COND_EXPR condition could be folded from EQ_EXPR/NE_EXPR
into a consta
Hi,
As mentioned in PR, for the following test-case:
typedef unsigned char uint8_t;
static inline uint8_t
x264_clip_uint8(uint8_t x)
{
uint8_t t = -x;
uint8_t t1 = x & ~63;
return (t1 != 0) ? t : x;
}
void
mc_weight(uint8_t *restrict dst, uint8_t *restrict src, int n)
{
for (int x = 0; x
On Fri, 8 Oct 2021 at 21:19, Richard Sandiford
wrote:
>
> Thanks for looking at this.
>
> Prathamesh Kulkarni writes:
> > Hi,
> > As mentioned in PR, for the following test-case:
> >
> > typedef unsigned char uint8_t;
> >
> > sta
On Mon, 11 Oct 2021 at 20:42, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Fri, 8 Oct 2021 at 21:19, Richard Sandiford
> > wrote:
> >>
> >> Thanks for looking at this.
> >>
> >> Prathamesh Kulkarni writes:
> >&g
On Wed, 13 Oct 2021 at 13:26, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Mon, 11 Oct 2021 at 20:42, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > On Fri, 8 Oct 2021 at 21:19, Richard Sandiford
>
Hi Richard,
As suggested in PR, I have attached WIP patch that adds two patterns
to match.pd:
erfc(x) --> 1 - erf(x) if canonicalize_math_p() and,
1 - erf(x) --> erfc(x) if !canonicalize_math_p().
This works to remove call to erfc for the following test:
double f(double x)
{
double g(double, dou
On Mon, 18 Oct 2021 at 14:34, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c
> > b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c
> > index 4604365fbef..cedc5b7c549 100644
> >
Hi,
The attached patch emits a more verbose diagnostic for target attribute that
is an architecture extension needing a leading '+'.
For the following test,
void calculate(void) __attribute__ ((__target__ ("sve")));
With patch, the compiler now emits:
102376.c:1:1: error: arch extension ‘sve’ sho
On Mon, 18 Oct 2021 at 16:18, Richard Biener wrote:
>
> On Mon, 18 Oct 2021, Prathamesh Kulkarni wrote:
>
> > Hi Richard,
> > As suggested in PR, I have attached WIP patch that adds two patterns
> > to match.pd:
> > erfc(x) --> 1 - erf(x) if canonicalize_mat
On Mon, 18 Oct 2021 at 17:10, Richard Biener wrote:
>
> On Mon, 18 Oct 2021, Prathamesh Kulkarni wrote:
>
> > On Mon, 18 Oct 2021 at 16:18, Richard Biener wrote:
> > >
> > > On Mon, 18 Oct 2021, Prathamesh Kulkarni wrote:
> > >
> > > > Hi Ri
Hi,
The attached patch removes "-mcpu=generic+sve" from dg-options,
because it conflicts
with -march=armv8.3-a+sve, and resulted in:
cc1: warning: switch '-mcpu=generic+sve' conflicts with
'-march=armv8.3-a+sve' switch^M
FAIL: gcc.target/aarch64/sve/pr93183.c (test for excess errors)
Excess errors
On Mon, 18 Oct 2021 at 17:23, Richard Biener wrote:
>
> On Mon, 18 Oct 2021, Prathamesh Kulkarni wrote:
>
> > On Mon, 18 Oct 2021 at 17:10, Richard Biener wrote:
> > >
> > > On Mon, 18 Oct 2021, Prathamesh Kulkarni wrote:
> > >
> > > &g
On Tue, 19 Oct 2021 at 13:32, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi,
> > The attached patch removes "-mcpu=generic+sve" from dg-options,
> > because it conflicts
> > with -march=armv8.3-a+sve, and resulted in:
> >
> >
On Tue, 19 Oct 2021 at 13:02, Richard Biener wrote:
>
> On Tue, Oct 19, 2021 at 9:03 AM Prathamesh Kulkarni via Gcc-patches
> wrote:
> >
> > On Mon, 18 Oct 2021 at 17:23, Richard Biener wrote:
> > >
> > > On Mon, 18 Oct 2021, Prathamesh Kulkarni wrote:
>
On Tue, 19 Oct 2021 at 19:58, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi,
> > The attached patch emits a more verbose diagnostic for target attribute that
> > is an architecture extension needing a leading '+'.
> >
> > F
On Tue, 19 Oct 2021 at 16:55, Richard Biener wrote:
>
> On Tue, 19 Oct 2021, Prathamesh Kulkarni wrote:
>
> > On Tue, 19 Oct 2021 at 13:02, Richard Biener
> > wrote:
> > >
> > > On Tue, Oct 19, 2021 at 9:03 AM Prathamesh Kulkarni via Gcc-patches
> >
On Wed, 20 Oct 2021 at 18:21, Richard Biener wrote:
>
> On Wed, 20 Oct 2021, Prathamesh Kulkarni wrote:
>
> > On Tue, 19 Oct 2021 at 16:55, Richard Biener wrote:
> > >
> > > On Tue, 19 Oct 2021, Prathamesh Kulkarni wrote:
> > >
> > > > On Tue
On Wed, 20 Oct 2021 at 15:05, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Tue, 19 Oct 2021 at 19:58, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > Hi,
> >> > The attached patch emits
On Fri, 22 Oct 2021 at 14:56, Richard Biener wrote:
>
> On Fri, 22 Oct 2021, Prathamesh Kulkarni wrote:
>
> > On Wed, 20 Oct 2021 at 18:21, Richard Biener wrote:
> > >
> > > On Wed, 20 Oct 2021, Prathamesh Kulkarni wrote:
> > >
> > > &g
On Fri, 22 Oct 2021 at 14:41, Prathamesh Kulkarni
wrote:
>
> On Wed, 20 Oct 2021 at 15:05, Richard Sandiford
> wrote:
> >
> > Prathamesh Kulkarni writes:
> > > On Tue, 19 Oct 2021 at 19:58, Richard Sandiford
> > > wrote:
> > >>
> >
Hi Kyrill,
I assume this patch is OK to commit after bootstrap+testing ?
Thanks,
Prathamesh
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index f42a15f7912..41b596b5fc6 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -8384,21 +8384,25 @@ __extension__
Hi,
This patch replaces builtins with __a * __b for signed variants of
vmul_n intrinsics.
As discussed earlier, the patch has issue if __a * __b overflows, and
whether we wish to leave
that as UB.
Thanks,
Prathamesh
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 41b596b5f
On Thu, 1 Jul 2021 at 16:26, Prathamesh Kulkarni
wrote:
>
> On Wed, 30 Jun 2021 at 20:51, Christophe LYON
> wrote:
> >
> >
> > On 29/06/2021 12:46, Prathamesh Kulkarni wrote:
> > > On Mon, 28 Jun 2021 at 14:48, Christophe LYON
> > > wrote:
> >
On Tue, 6 Jul 2021 at 13:33, Kyrylo Tkachov wrote:
>
>
>
> > -Original Message-
> > From: Prathamesh Kulkarni
> > Sent: 06 July 2021 08:06
> > To: Christophe LYON
> > Cc: Kyrylo Tkachov ; gcc Patches > patc...@gcc.gnu.org>
> >
On Mon, 5 Jul 2021 at 14:47, Prathamesh Kulkarni
wrote:
>
> Hi,
> This patch replaces builtins with __a * __b for signed variants of
> vmul_n intrinsics.
> As discussed earlier, the patch has issue if __a * __b overflows, and
> whether we wish to leave
> that as UB.
ping
ht
On Mon, 12 Jul 2021 at 15:23, Prathamesh Kulkarni
wrote:
>
> On Mon, 5 Jul 2021 at 14:47, Prathamesh Kulkarni
> wrote:
> >
> > Hi,
> > This patch replaces builtins with __a * __b for signed variants of
> > vmul_n intrinsics.
> > As discussed earlier, the
On Thu, 15 Jul 2021 at 14:47, Christophe Lyon
wrote:
>
> Hi Prathamesh,
>
> On Mon, Jul 5, 2021 at 11:25 AM Kyrylo Tkachov via Gcc-patches
> wrote:
>>
>>
>>
>> > -Original Message-
>> > From: Prathamesh Kulkarni
>> > Se
On Thu, 15 Jul 2021 at 16:46, Prathamesh Kulkarni
wrote:
>
> On Thu, 15 Jul 2021 at 14:47, Christophe Lyon
> wrote:
> >
> > Hi Prathamesh,
> >
> > On Mon, Jul 5, 2021 at 11:25 AM Kyrylo Tkachov via Gcc-patches
> > wrote:
> >>
> >>
>
Hi,
The attached patch removes calls to builtins from vshl_n intrinsics,
and replacing them
with left shift operator. The patch passes bootstrap+test on
arm-linux-gnueabihf.
Altho, I noticed, that the patch causes 3 extra registers to spill
using << instead
of the builtin for vshl_n.c. Could that
On Thu, 22 Jul 2021 at 16:03, Richard Earnshaw
wrote:
>
>
>
> On 22/07/2021 08:45, Prathamesh Kulkarni via Gcc-patches wrote:
> > Hi,
> > The attached patch removes calls to builtins from vshl_n intrinsics,
> > and replacing them
> > with left shift operator
On Thu, 22 Jul 2021 at 17:28, Richard Earnshaw
wrote:
>
>
>
> On 22/07/2021 12:32, Prathamesh Kulkarni wrote:
> > On Thu, 22 Jul 2021 at 16:03, Richard Earnshaw
> > wrote:
> >>
> >>
> >>
> >> On 22/07/2021 08:45, Prathamesh Kulkar
On Thu, 22 Jul 2021 at 20:29, Richard Earnshaw
wrote:
>
>
>
> On 22/07/2021 14:47, Prathamesh Kulkarni via Gcc-patches wrote:
> > On Thu, 22 Jul 2021 at 17:28, Richard Earnshaw
> > wrote:
> >>
> >>
> >>
> >> On 22/07/2021 12:32, P
On Fri, 23 Jul 2021 at 15:02, Richard Earnshaw
wrote:
>
> On 23/07/2021 08:04, Prathamesh Kulkarni via Gcc-patches wrote:
> > On Thu, 22 Jul 2021 at 20:29, Richard Earnshaw
> > wrote:
> >>
> >>
> >>
> >> On 22/07/2021 14:47, Prathamesh Kulkar
On Sun, 25 Jul 2021 at 16:03, Ankur Saini via Gcc-patches
wrote:
>
> Here is the new patch after fixing all the issues pointed out in the previous
> version.
Just a nitpick:
+/* call_string::element_t's inequality operator. */
+bool
+call_string::element_t::operator!= (const call_string::elemen
:
ldrdr0, [r0]
bx lr
I assume the code-gen after patch is correct, since it loads two
consecutive words from [r0] into r0 and r1 ?
Bootstrapped+tested on arm-linux-gnueabihf.
OK to commit ?
Thanks,
Prathamesh
2021-07-27 Prathamesh Kulkarni
PR target/66791
Hi,
The attached patch replaces builtins in vld1_dup intrinsics with call
to corresponding vdup_n intrinsic and removes entry for vld1_dup from
arm_neon_builtins.def.
Bootstrapped+tested on arm-linux-gnueabihf.
OK to commit ?
Thanks,
Prathamesh
gcc/ChangeLog:
PR target/66791
* con
On Thu, 29 Jul 2021 at 14:57, Kyrylo Tkachov wrote:
>
> Hi Prathamesh,
>
> > -Original Message-
> > From: Prathamesh Kulkarni
> > Sent: 26 July 2021 22:24
> > To: gcc Patches ; Kyrylo Tkachov
> > ; Richard Earnshaw
> >
> > Subject:
On Tue, 27 Apr 2021 at 17:02, Christophe Lyon via Gcc-patches
wrote:
>
> Support for vadd has been present for a while, but it was lacking a
> test.
>
> 2021-04-22 Christophe Lyon
>
> gcc/testsuite/
> * gcc.target/arm/simd/mve-vadd-1.c: New.
> ---
> gcc/testsuite/gcc.target/arm
On Tue, 27 Apr 2021 at 19:19, Richard Biener wrote:
>
> DSE performs a backwards walk over stmts removing stores but it
> leaves removing resulting dead SSA defs to later passes. This
> eats into its own alias walking budget if the removed stores kept
> loads live. The following patch adds remov
On Tue, 4 May 2021 at 07:30, Alexandre Oliva wrote:
>
> On May 3, 2021, Richard Biener wrote:
>
> > On Fri, Apr 30, 2021 at 4:42 PM Jeff Law wrote:
> >>
> >>
> >> On 4/28/2021 10:26 PM, Alexandre Oliva wrote:
> >> > On Feb 22, 2021, Richard Biener wrote:
> >> >
> >> >> On Fri, Feb 19, 2021 at
On Fri, 5 Feb 2021 at 15:42, Kyrylo Tkachov wrote:
>
> Hi Prathamesh,
>
> > -Original Message-
> > From: Prathamesh Kulkarni
> > Sent: 05 February 2021 09:53
> > To: gcc Patches ; Kyrylo Tkachov
> >
> > Subject: [PR97903][ARM] Missed optimiz
Hi,
The attached patch replaces __builtin_neon_vtst* (a, b) with (a & b) != 0.
Bootstrapped and tested on arm-linux-gnueabihf and cross-tested on arm*-*-*.
OK to commit ?
Thanks,
Prathamesh
vtst-1.diff
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