Re: [PATCH] Fix improper combiner optimization of mixed mode vector/scalar expressions (PR 79365)
Thanks Segher. I will address your comments and repost for GCC 8. > What is this for? It isn't triggered by the testcase in the PR. It was triggered by our strcmp code, but I didn't have a simple test case for it. I will try to generate one. Walter
Re: [PATCH] Fix improper combiner optimization of mixed mode vector/scalar expressions (PR 79365)
On 2/3/2017 3:03 PM, Walter Lee wrote: Hi, In looking at PR 79365 I found that the problem is actually in the combiner. The combiner sometimes applies scalar optimizations to vector context where they are invalid. i.e. (a > b) >> 1 can optimize to 0 if ">" is a scalar op but not if it is a vector op. The reason this shows up on tile* and not other architectures is because tile* uses the same register file for both scalars and vectors, so the combiner sees these mixed mode expressions on tile* that would go through memory on other architectures. I have found two places where this improper optimization occurs. Patch below. Ok to commit? I forgot to mention this fix has been validated on TILEPro/TILE-Gx. I also sanity checked it against x86. Thanks, Walter
[PATCH] Fix improper combiner optimization of mixed mode vector/scalar expressions (PR 79365)
Hi, In looking at PR 79365 I found that the problem is actually in the combiner. The combiner sometimes applies scalar optimizations to vector context where they are invalid. i.e. (a > b) >> 1 can optimize to 0 if ">" is a scalar op but not if it is a vector op. The reason this shows up on tile* and not other architectures is because tile* uses the same register file for both scalars and vectors, so the combiner sees these mixed mode expressions on tile* that would go through memory on other architectures. I have found two places where this improper optimization occurs. Patch below. Ok to commit? Thanks, Walter diff --git a/gcc/combine.c b/gcc/combine.c index 28133ff..8f2615e 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -7267,6 +7267,7 @@ expand_field_assignment (const_rtx x) else if (GET_CODE (SET_DEST (x)) == SUBREG /* We need SUBREGs to compute nonzero_bits properly. */ && nonzero_sign_valid + && !VECTOR_MODE_P (GET_MODE (SET_DEST (x))) && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x @@ -13030,6 +13031,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data) record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); else if (GET_CODE (setter) == SET && GET_CODE (SET_DEST (setter)) == SUBREG + && !VECTOR_MODE_P (GET_MODE (SET_DEST (setter))) && SUBREG_REG (SET_DEST (setter)) == dest && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD && subreg_lowpart_p (SET_DEST (setter))) -- 2.7.2
[PATCH, committed] TILEPro/TILE-Gx: add blockage to avoid bad scheduler + dwarf interaction (PR target/78862)
This patch fixes PR target/78862. Add blockage to prevent the
scheduler from reordering a LR save with a subsequent instruction that
changes the CFA register. This trips up the dwarf generating logic.
Bootstrapped and tested on TILEPro/TILE-Gx hardware, also backported
to GCC 6.
* config/tilegx/tilegx.md (tilegx_expand_prologue): Add blockage
after initial stackframe link reg save.
* config/tilepro/tilepro.md (tilepro_expand_prologue): Likewise.
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index b04e708..d8ca14b 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -3998,8 +3998,11 @@ tilegx_expand_prologue (void)
/* Save lr first in its special location because code after this
might use the link register as a scratch register. */
if (df_regs_ever_live_p (TILEGX_LINK_REGNUM) || crtl->calls_eh_return)
-FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
- stack_pointer_rtx, stack_pointer_rtx, 0));
+{
+ FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
+stack_pointer_rtx, stack_pointer_rtx, 0));
+ emit_insn (gen_blockage ());
+}
if (total_size == 0)
{
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index b16ad38..aa1bb1c 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -3533,8 +3533,11 @@ tilepro_expand_prologue (void)
/* Save lr first in its special location because code after this
might use the link register as a scratch register. */
if (df_regs_ever_live_p (TILEPRO_LINK_REGNUM) || crtl->calls_eh_return)
-FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
- stack_pointer_rtx, stack_pointer_rtx, 0));
+{
+ FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
+stack_pointer_rtx, stack_pointer_rtx, 0));
+ emit_insn (gen_blockage ());
+}
if (total_size == 0)
{
--
2.7.2
[PATCH, committed] TILEPro/TILE-Gx: add trap patterns
This patch adds a trap pattern to TILEPro/Tile-Gx. The pattern emits an instruction bundle that causes a SIGABRT. Bootstrapped and tested on TILEPro/TILE-Gx hardware, also backported to GCC 6. * config/tilegx/tilegx.md (trap): New pattern. * config/tilepro/tilepro.md (trap): Likewise. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8e2bbdf..259eb02 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2016-11-22 Walter Lee <w...@tilera.com> + * config/tilegx/tilegx.md (trap): New pattern. + * config/tilepro/tilepro.md (trap): Likewise. + +2016-11-22 Walter Lee <w...@tilera.com> + * config/tilegx/tilegx.md (*zero_extract): Use define_insn_and_split instead of define_insn; Handle pos + size > 64. diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 3ad5a87..eccdd28 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -2773,6 +2773,12 @@ "nop" [(set_attr "type" "Y01")]) +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "raise; moveli zero, 6" + [(set_attr "type" "cannot_bundle")]) + ^L ;; ;; Conditional branches diff --git a/gcc/config/tilepro/tilepro.md b/gcc/config/tilepro/tilepro.md index 6493b06..d1536ed 100644 --- a/gcc/config/tilepro/tilepro.md +++ b/gcc/config/tilepro/tilepro.md @@ -1578,6 +1578,12 @@ "nop" [(set_attr "type" "Y01")]) +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "raise; moveli zero, 6" + [(set_attr "type" "cannot_bundle")]) + ^L ;; ;; Conditional branches
[PATCH, committed] TILE-Gx: fix zero_extract/sign_extract patterns
This patch fixes the zero_extract/sign_extract patterns so that they
properly handle the case when pos + size > number of bits in a word.
Bootstrapped and tested on TILE-Gx hardware, also backported to GCC 6.
* config/tilegx/tilegx.md (*zero_extract): Use
define_insn_and_split instead of define_insn; Handle pos +
size > 64.
(*sign_extract): Likewise.
diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index 55c345c..3ad5a87 100644
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -1237,7 +1237,7 @@
"ld_tls\t%0, %1, tls_ie_load(%2)"
[(set_attr "type" "X1_2cycle")])
-(define_insn "*zero_extract"
+(define_insn_and_split "*zero_extract"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
(zero_extract:I48MODE
(match_operand:I48MODE 1 "reg_or_0_operand" "r")
@@ -1245,6 +1245,18 @@
(match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
""
"bfextu\t%0, %r1, %3, %3+%2-1"
+ "&& reload_completed"
+ [(set (match_dup 0) (zero_extract:I48MODE
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)))]
+{
+ HOST_WIDE_INT bit_width = INTVAL (operands[2]);
+ HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
+
+ if (bit_offset + bit_width > 64)
+operands[2] = GEN_INT (64 - bit_offset);
+}
[(set_attr "type" "X0")])
(define_insn "*sign_extract_low32"
@@ -1256,7 +1268,7 @@
"INTVAL (operands[3]) == 0 && INTVAL (operands[2]) == 32"
"addxi\t%0, %r1, 0")
-(define_insn "*sign_extract"
+(define_insn_and_split "*sign_extract"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
(sign_extract:I48MODE
(match_operand:I48MODE 1 "reg_or_0_operand" "r")
@@ -1264,6 +1276,18 @@
(match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
""
"bfexts\t%0, %r1, %3, %3+%2-1"
+ "&& reload_completed"
+ [(set (match_dup 0) (sign_extract:I48MODE
+ (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)))]
+{
+ HOST_WIDE_INT bit_width = INTVAL (operands[2]);
+ HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
+
+ if (bit_offset + bit_width > 64)
+operands[2] = GEN_INT (64 - bit_offset);
+}
[(set_attr "type" "X0")])
[PATCH, committed] TILEPro: link against libgcc.a when creating shared libraries
This patch forces gcc to link against libgcc.a when creating shared
libraries, needed for 64-bit multiplies.
Bootstrapped and tested on tilepro hardware, also backported to GCC 6.
2016-11-18 Walter Lee <w...@tilera.com>
* config.host (tilepro*-*-linux*): Add t-slibgcc-libgcc.
diff --git a/libgcc/config.host b/libgcc/config.host
index 64beb21..e7e5413 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1267,7 +1267,7 @@ tilegx*-*-linux*)
md_unwind_header=tilepro/linux-unwind.h
;;
tilepro*-*-linux*)
- tmake_file="${tmake_file} tilepro/t-crtstuff t-softfp-sfdf t-softfp
tilepro/t-tilepro"
+ tmake_file="${tmake_file} tilepro/t-crtstuff t-softfp-sfdf t-softfp
tilepro/t-tilepro t-slibgcc-libgcc"
md_unwind_header=tilepro/linux-unwind.h
;;
v850*-*-*)
[PATCH, committed] TILEPro: link against libgcc.a when creating shared libraries
This patch forces gcc to link against libgcc.a when creating shared
libraries, needed for 64-bit multiplies.
Bootstrapped and tested on tilepro hardware, also backported to GCC 6.
2016-11-18 Walter Lee <w...@tilera.com>
* config.host (tilepro*-*-linux*): Add t-slibgcc-libgcc.
diff --git a/libgcc/config.host b/libgcc/config.host
index 64beb21..e7e5413 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1267,7 +1267,7 @@ tilegx*-*-linux*)
md_unwind_header=tilepro/linux-unwind.h
;;
tilepro*-*-linux*)
- tmake_file="${tmake_file} tilepro/t-crtstuff t-softfp-sfdf t-softfp
tilepro/t-tilepro"
+ tmake_file="${tmake_file} tilepro/t-crtstuff t-softfp-sfdf t-softfp
tilepro/t-tilepro t-slibgcc-libgcc"
md_unwind_header=tilepro/linux-unwind.h
;;
v850*-*-*)
[PATCH, committed] TILE-Gx: fix barrier bundling
This patch fixes a bundling bug. When there are consecutive barriers,
the end-of-bundle marker of the last barrier is getting dropped.
Bootstrapped and tested on tilegx hardware, also backported to GCC 6.
2016-11-18 Walter Lee <w...@tilera.com>
* config/tilegx/tilegx.c (tilegx_gen_bundles): Preserve
end-of-bundle marker for consecutive barriers.
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index 76a7455..0403e8e 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -4469,8 +4469,7 @@ tilegx_gen_bundles (void)
rtx_insn *end = NEXT_INSN (BB_END (bb));
prev = NULL;
- for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn;
- prev = insn, insn = next)
+ for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
{
next = next_insn_to_bundle (NEXT_INSN (insn), end);
@@ -4506,7 +4505,11 @@ tilegx_gen_bundles (void)
PUT_MODE (prev, QImode);
}
delete_insn (insn);
+
+// Note: prev remains the same for next iteration.
}
+ else
+prev = insn;
}
}
}
[PATCH, committed] TILE-Gx: fix clzsi2 for big-endian
This patch fixes the clzsi2 pattern, which was broken for big-endian.
Bootstrapped and tested on tilegx hardware, also backported to GCC 6.
2016-11-18 Walter Lee <w...@tilera.com>
* config/tilegx/tilegx.md (clzsi2): Fix for big-endian.
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -1798,19 +1798,20 @@
[(set_attr "type" "Y0")])
(define_expand "clzsi2"
- [(set (match_dup 2)
- (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" "")))
- (set (match_dup 2)
- (ashift:DI (match_dup 2)
- (const_int 32)))
- (set (match_dup 2)
- (clz:DI (match_dup 2)))
- (set (match_operand:SI 0 "register_operand" "")
- (subreg:SI (match_dup 2) 0))]
- ""
- {
- operands[2] = gen_reg_rtx (DImode);
- })
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (clz:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))]
+ ""
+ {
+rtx tmp1 = gen_reg_rtx (DImode);
+rtx tmp2 = gen_reg_rtx (DImode);
+rtx tmp3 = gen_reg_rtx (DImode);
+
+emit_insn (gen_zero_extendsidi2 (tmp1, operands[1]));
+emit_insn (gen_ashldi3 (tmp2, tmp1, (GEN_INT (32;
+emit_insn (gen_clzdi2 (tmp3, tmp2));
+emit_move_insn (operands[0], gen_lowpart (SImode, tmp3));
+DONE;
+ })
(define_insn "ctz2"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
[PATCH, committed] TILEPro/TILE-Gx: remove linux header dependencies
This patch removes the build dependencies on linux headers, by
defining a few definitions that we need from those headers.
libgcc/ChangeLog:
2016-06-28 Walter Lee <w...@tilera.com>
* config/tilepro/atomic.h: Do not include arch/spr_def.h and
asm/unistd.h.
(SPR_CMPEXCH_VALUE): Define for tilegx.
(__NR_FAST_cmpxchg): Define for tilepro.
(__NR_FAST_atomic_update): Define for tilepro.
(__NR_FAST_cmpxchg64): Define for tilepro.
gcc/ChangeLog:
2016-06-28 Walter Lee <w...@tilera.com>
* config/tilegx/linux.h: Do not include arch/icache.h
(CLEAR_INSN_CACHE): Provide inlined definition directly.
* config/tilepro/linux.h: Do not include arch/icache.h
(CLEAR_INSN_CACHE): Provide inlined definition directly.
Index: libgcc/config/tilepro/atomic.h
===
--- libgcc/config/tilepro/atomic.h(revision 237823)
+++ libgcc/config/tilepro/atomic.h(working copy)
@@ -93,9 +93,11 @@
#endif
#ifdef __tilegx__
-#include
+#define SPR_CMPEXCH_VALUE 0x2780
#else
-#include
+#define __NR_FAST_cmpxchg-1
+#define __NR_FAST_atomic_update-2
+#define __NR_FAST_cmpxchg64-3
#endif
Index: gcc/config/tilegx/linux.h
===
--- gcc/config/tilegx/linux.h(revision 237823)
+++ gcc/config/tilegx/linux.h(working copy)
@@ -55,12 +55,23 @@
/* For __clear_cache in libgcc2.c. */
#ifdef IN_LIBGCC2
-#include
-
/* Use the minimum page size of 4K. Alternatively we can call
- getpagesize() but it introduces a libc dependence. */
+ getpagesize() but it introduces a libc dependence.
+ See Linux arch/tile/include/uapi/arch/icache.h for more commentary. */
#undef CLEAR_INSN_CACHE
-#define CLEAR_INSN_CACHE(beg, end) invalidate_icache (beg, end - beg, 4096)
+#define CLEAR_INSN_CACHE(BEG, END) \
+{ \
+ long size = (long) (END) - (long) (BEG); \
+ if (size) \
+{ \
+ const char *p = (const char *) ((unsigned long) (BEG) & -64L);\
+ const char *end = p + (size < 4096 ? size : 4096) - 1;\
+ __insn_mf (); \
+ for (; p <= end; p += 64) \
+__insn_icoh (p);\
+ __insn_drain (); \
+} \
+}
#else
Index: gcc/config/tilepro/linux.h
===
--- gcc/config/tilepro/linux.h(revision 237823)
+++ gcc/config/tilepro/linux.h(working copy)
@@ -47,12 +47,31 @@
/* For __clear_cache in libgcc2.c. */
#ifdef IN_LIBGCC2
-#include
-
-/* Use the minimum page size of 4K. Alternatively we can call getpagesize()
- but it introduces a libc dependence. */
+/* Use the minimum page size of 4K. Alternatively we can call
+ getpagesize() but it introduces a libc dependence.
+ See Linux arch/tile/include/uapi/arch/icache.h for more commentary. */
#undef CLEAR_INSN_CACHE
-#define CLEAR_INSN_CACHE(beg, end) invalidate_icache (beg, end - beg, 4096)
+#define CLEAR_INSN_CACHE(BEG, END) \
+{ \
+ long size = (long) (END) - (long) (BEG); \
+ if (size) \
+{ \
+ const char *start = (const char *) ((unsigned long) (BEG) & -64L);\
+ const char *end = start + (size < 16384 ? size : 16384) - 1; \
+ long num_passes = 4; \
+ __insn_mf (); \
+ do\
+ { \
+const char *p; \
+for (p = start; p <= end; p += 64) \
+ __insn_icoh (p); \
+start += 4096; \
+end += 4096;\
+ } \
+ while (--num_passes > 0);
[PATCH, committed] TILE-Gx: Use CXX_FOR_BUILD to compile c++ source.
This patch uses g++ instead of gcc to compile a c++ source file. The GNU buildbot is currently failing with a c++ related link error that I have not been able to reproduce; I'm hoping using g++ will fix the issue. 2016-02-12 Walter Lee <w...@tilera.com> * config/tilepro/t-tilepro: Replace CC_FOR_BUILD with CXX_FOR_BUILD. * config/tilegx/t-tilegx: Likewise. Index: gcc/config/tilegx/t-tilegx === --- gcc/config/tilegx/t-tilegx(revision 233352) +++ gcc/config/tilegx/t-tilegx(working copy) @@ -12,7 +12,7 @@ tilegx-c.o: $(srcdir)/config/tilegx/tile $(srcdir)/config/tilegx/mul-tables.c: \ $(srcdir)/config/tilepro/gen-mul-tables.cc -$(CC_FOR_BUILD) $(BUILD_CPPFLAGS) -O2 -o gen-mul-tables -lstdc++ $<; +$(CXX_FOR_BUILD) $(BUILD_CPPFLAGS) -O2 -o gen-mul-tables $<; ./gen-mul-tables > $@ mul-tables.o: $(srcdir)/config/tilegx/mul-tables.c \ Index: gcc/config/tilepro/t-tilepro === --- gcc/config/tilepro/t-tilepro(revision 233352) +++ gcc/config/tilepro/t-tilepro(working copy) @@ -5,8 +5,8 @@ tilepro-c.o: $(srcdir)/config/tilepro/ti $(srcdir)/config/tilepro/mul-tables.c: \ $(srcdir)/config/tilepro/gen-mul-tables.cc -$(CC_FOR_BUILD) $(BUILD_CPPFLAGS) -O2 -DTILEPRO \ - -o gen-mul-tables -lstdc++ $<; +$(CXX_FOR_BUILD) $(BUILD_CPPFLAGS) -O2 -DTILEPRO \ + -o gen-mul-tables $<; ./gen-mul-tables > $@
Re: [PATCH] Fix tilegx libgcc with multilib
Hi Bernd. Thanks for looking into that. Your patch looks good and I have checked it in myself. Walter On 1/1/2016 4:31 PM, Bernd Edlinger wrote: Hi Walter, while playing with the tilegx cross compiler I noticed another defect. Currently building a tilegx cross compiler fails in libgcc multilib configuration, because of the following static assert in _FP_FROM_INT: _FP_STATIC_ASSERT ((rsize) <= 2 * _FP_W_TYPE_SIZE,\ "rsize too large");\ previously that macro used to abort at run-time. This happens apparently in all float to ti-int conversions in the 32-bit target configuration. So I assume that softfp_int_modes should only contain ti for 64-bit target configurations. The following patch makes the multilib libgcc build succeed for me, but I can not test if the result is actually usable. Really AFAICT these machines must be pretty cool, but I don't own one... Thanks Bernd.
[PATCH, committed] TILE-Gx: Fix softfp build error.
This patch removes ti from softfp_int_modes for 32-bit config, to fix a
compile-time assert failure.
2016-02-12 Walter Lee <w...@tilera.com>
* config.host (tilegx*-*-linux*): remove ti from
softfp_int_modes for 32-bit configs.
Index: libgcc/config.host
===
--- libgcc/config.host (revision 233388)
+++ libgcc/config.host (working copy)
@@ -1277,7 +1277,10 @@ tic6x-*-elf)
unwind_header=config/c6x/unwind-c6x.h
;;
tilegx*-*-linux*)
- tmake_file="${tmake_file} tilegx/t-crtstuff t-softfp-sfdf
tilegx/t-softfp t-softfp tilegx/t-tilegx"
+ if test "${host_address}" = 64; then
+ tmake_file="${tmake_file} tilegx/t-softfp"
+ fi
+ tmake_file="${tmake_file} tilegx/t-crtstuff t-softfp-sfdf
t-softfp tilegx/t-tilegx"
md_unwind_header=tilepro/linux-unwind.h
;;
tilepro*-*-linux*)
Re: [PATCH] Fix pr68917 ICE on __builtin_clz for tilegx
On 12/27/2015 2:38 PM, Bernd Edlinger wrote: > Hi, > > due to more thorough checks in the middle end the builtin clz instruction > causes now an ICE on the tilegx target. > > I have built a tilegx-cross-comiler and inspected the generated code > to verify that the patch works. > > Is is OK for trunk? Looks good to me. Thanks. Walter
Re: [patch] Fix tilepro includes
On 12/8/2014 11:23 AM, Jan-Benedict Glaw wrote: On Fri, 2014-11-21 08:45:11 -0500, Andrew MacLeod amacl...@redhat.com wrote: During the flattening of optabs.h, I updated all the config/* files which were affected. I've been getting spurious failures with config-list.mk where my changes would disappear and tracked down why. I was blissfully unaware that the tilepro ports mul-tables.c file is actually generated from gen-mul-tables.cc. This patch fixes the include issue by adding #include insn-codes.h to the generated files. I also added a comment indicating these are generated files, and to make changes in the generator. This allows all the tile* ports to compile properly again. OK for trunk? Seems this wasn't ever ACKed or applied up to now? I'm still seeing compilation errors for the tile targets, see eg. http://toolchain.lug-owl.de/buildbot/show_build_details.php?id=382169 Sorry about that. Looks good to me. Walter
[PATCH] TILE-Gx: big endian support
This patch adds support for big endian on tilegx. It's been tested on
tilegx hardware.
Most of the changes are of course in target-specific files, but I have
to touch a few shared files to support the big endian triplets. I've
split up the changes to shared/non-shared files. Can someone approve
the shared files changes? I've inlined the shared files changes for
convenience, and included the target-specific changes as an
attachment.
Thanks,
Walter
Shared files changes:
/:
* configure.ac (tilepro-*-*) Change to tilepro*-*-*.
(tilegx-*-*): Change to tilegx*-*-*.
* configure: Regenerate.
contrib/:
* config-list.mk (tilegxbe-linux-gnu): Add tilegx big endian
target.
gcc/:
* config.gcc (tilepro-*-*): Change to tilepro*-*-*.
(tilegx-*-linux*): Change to tilegx*-*-linux*; Support tilegxbe
triplet.
* doc/install.texi: Document tilegxbe-linux.
* doc/invoke.texi: Document -mbig-endian and -mlittle-endian.
libcpp/:
* configure.ac: Change tilepro triplet to tilepro*.
* configure: Regenerate.
libgcc/:
* config.host: Support tilegx* and tilepro* triplets.
Target-specific changes:
gcc/:
* common/config/tilegx/tilegx-common.c
(TARGET_DEFAULT_TARGET_FLAGS): Define.
* config/tilegx/linux.h (ASM_SPEC): Add endian_spec.
(LINK_SPEC): Ditto.
* config/tilegx/sync.md (atomic_test_and_set): Handle big endian.
* config/tilegx/tilegx.c (tilegx_return_in_msb): New.
(tilegx_gimplify_va_arg_expr): Handle big endian.
(tilegx_expand_unaligned_load): Ditto.
(tilegx_expand_unaligned_store): Ditto.
(TARGET_RETURN_IN_MSB): New.
* config/tilegx/tilegx.h (TARGET_DEFAULT): New.
(TARGET_ENDIAN_DEFAULT): New.
(TARGET_BIG_ENDIAN): Handle big endian.
(BYTES_BIG_ENDIAN): Ditto.
(WORDS_BIG_ENDIAN): Ditto.
(FLOAT_WORDS_BIG_ENDIAN): Ditto.
(ENDIAN_SPEC): New.
(EXTRA_SPECS): New.
* config/tilegx/tilegx.md (extv): Handle big endian.
(extzv): Ditto.
(insn_stn): Ditto.
(insn_stn_addbitsuffix): Ditto.
(insn_stntn): Ditto.
(insn_stntn_addbitsuffix):Ditto.
(vec_interleave_highv8qi): Handle big endian.
(vec_interleave_highv8qi_be): New.
(vec_interleave_highv8qi_le): New.
(insn_v1int_h): Handle big endian.
(vec_interleave_lowv8qi): Handle big endian.
(vec_interleave_lowv8qi_be): New.
(vec_interleave_lowv8qi_le): New.
(insn_v1int_l): Handle big endian.
(vec_interleave_highv4hi): Handle big endian.
(vec_interleave_highv4hi_be): New.
(vec_interleave_highv4hi_le): New.
(insn_v2int_h): Handle big endian.
(vec_interleave_lowv4hi): Handle big endian.
(vec_interleave_lowv4hi_be): New.
(vec_interleave_lowv4hi_le): New.
(insn_v2int_l): Handle big endian.
(vec_interleave_highv2si): Handle big endian.
(vec_interleave_highv2si_be): New.
(vec_interleave_highv2si_le): New.
(insn_v4int_h): Handle big endian.
(vec_interleave_lowv2si): Handle big endian.
(vec_interleave_lowv2si_be): New.
(vec_interleave_lowv2si_le): New.
(insn_v4int_l): Handle big endian.
* config/tilegx/tilegx.opt (mbig-endian): New option.
(mlittle-endian): New option.
libgcc/:
* config/tilegx/sfp-machine32.h (__BYTE_ORDER): Handle big endian.
* config/tilegx/sfp-machine64.h (__BYTE_ORDER): Handle big endian.
diff --git a/configure b/configure
index 749a35e..57be424 100755
--- a/configure
+++ b/configure
@@ -3815,7 +3815,7 @@ case ${target} in
tic6x-*-*)
noconfigdirs=$noconfigdirs sim
;;
- tilepro-*-* | tilegx-*-*)
+ tilepro*-*-* | tilegx*-*-*)
noconfigdirs=$noconfigdirs sim
;;
v810-*-*)
diff --git a/configure.ac b/configure.ac
index b24b33d..aaeb966 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1145,7 +1145,7 @@ case ${target} in
tic6x-*-*)
noconfigdirs=$noconfigdirs sim
;;
- tilepro-*-* | tilegx-*-*)
+ tilepro*-*-* | tilegx*-*-*)
noconfigdirs=$noconfigdirs sim
;;
v810-*-*)
diff --git a/contrib/config-list.mk b/contrib/config-list.mk
index f2d441b..4345487 100644
--- a/contrib/config-list.mk
+++ b/contrib/config-list.mk
@@ -66,7 +66,8 @@ LIST = aarch64-elf aarch64-linux-gnu \
sparc-leon3-linux-gnuOPT-enable-target=all sparc-netbsdelf \
sparc64-sun-solaris2.10OPT-with-gnu-ldOPT-with-gnu-asOPT-enable-threads=posix \
sparc-wrs-vxworks sparc64-elf sparc64-rtems sparc64-linux sparc64-freebsd6 \
- sparc64-netbsd sparc64-openbsd spu-elf tilegx-linux-gnu tilepro-linux-gnu \
+ sparc64-netbsd sparc64-openbsd spu-elf \
+ tilegx-linux-gnu tilegxbe-linux-gnu tilepro-linux-gnu \
v850e-elf v850-elf vax-linux-gnu \
vax-netbsdelf vax-openbsd x86_64-apple-darwin \
x86_64-pc-linux-gnuOPT-with-fpmath=avx \
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c3124be..bbc2611 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -494,7 +494,7 @@ tilegx*-*-*)
cpu_type=tilegx
need_64bit_hwint=yes
;;
-tilepro-*-*)
+tilepro*-*-*)
cpu_type=tilepro
[PATCH] TILE-Gx: add release note on tilegx big endian support in wwwdocs
Here is a release note item for big endian support on tilegx. Ok to
commit once that change is approved?
--- gcc-4.9/changes.html28 Jan 2014 23:57:49 - 1.54
+++ gcc-4.9/changes.html30 Jan 2014 20:46:32 -
@@ -494,6 +494,12 @@ auto incr = [](auto x) { return x++; };
will result in a warning and will not influence code generation./li
/ul
+h3 id=tilegxTILE-Gx/h3
+
+ ul
+liAdded support for big endian./li
+ /ul
+
!--
h2Documentation improvements/h2
--
[committed] TILEPro: fix ctzdi2, clzdi2, and ffsdi2 patterns.
This patch fixes the predicates for the ctzdi2, clzdi2, and ffsdi2.
reg_or_0_operand is a 32-bit predicate so it will never match a DI
operand. It's sufficient to use register_operand.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9306621..b5487ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
2014-01-25 Walter Lee w...@tilera.com
+ * config/tilepro/tilepro.md (ctzdi2): Use register_operand
+ predicate.
+ (clzdi2): Ditto.
+ (ffsdi2): Ditto.
+
+2014-01-25 Walter Lee w...@tilera.com
+
* config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New.
(TARGET_EXPAND_TO_RTL_HOOK): Define.
diff --git a/gcc/config/tilepro/tilepro.md b/gcc/config/tilepro/tilepro.md
index adf49ba..314dd90 100644
--- a/gcc/config/tilepro/tilepro.md
+++ b/gcc/config/tilepro/tilepro.md
@@ -795,7 +795,7 @@
(define_expand ctzdi2
[(set (match_operand:DI 0 register_operand )
- (ctz:DI (match_operand:DI 1 reg_or_0_operand )))]
+ (ctz:DI (match_operand:DI 1 register_operand )))]
{
rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result;
@@ -823,7 +823,7 @@
(define_expand clzdi2
[(set (match_operand:DI 0 register_operand )
- (clz:DI (match_operand:DI 1 reg_or_0_operand )))]
+ (clz:DI (match_operand:DI 1 register_operand )))]
{
rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result;
@@ -851,7 +851,7 @@
(define_expand ffsdi2
[(set (match_operand:DI 0 register_operand )
- (ffs:DI (match_operand:DI 1 reg_or_0_operand )))]
+ (ffs:DI (match_operand:DI 1 register_operand )))]
{
rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond;
[committed] TILE-Gx/TILEPro: prefetch scheduling fix.
This patch marks the prefetch intrinsics as scheduling barriers. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b5487ae..39543a1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2014-01-25 Walter Lee w...@tilera.com + * config/tilegx/tilegx.c (tilegx_expand_builtin): Set + PREFETCH_SCHEDULE_BARRIER_P to true for prefetches. + * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto. + +2014-01-25 Walter Lee w...@tilera.com + * config/tilepro/tilepro.md (ctzdi2): Use register_operand predicate. (clzdi2): Ditto. diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c index 85a46f7..c168621 100644 --- a/gcc/config/tilegx/tilegx.c +++ b/gcc/config/tilegx/tilegx.c @@ -3570,6 +3570,12 @@ tilegx_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) +PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid) diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c index 615d490..74f8800 100644 --- a/gcc/config/tilepro/tilepro.c +++ b/gcc/config/tilepro/tilepro.c @@ -3184,6 +3184,12 @@ tilepro_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) +PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid)
[committed] TILE-Gx/TILEPro: define __GCC_HAVE_SYNX_COMPARE_AND_SWAP_n
The patch defines __GCC_HAVE_SYNX_COMPARE_AND_SWAP_n for those that
are provided in libgcc.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3a84318..5d7adb7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
2014-01-25 Walter Lee w...@tilera.com
+ * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins):
+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}.
+ * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins):
+ Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}.
+
+2014-01-25 Walter Lee w...@tilera.com
+
* config/tilegx/tilegx.c (tilegx_function_arg): Start 16-byte
arguments on even registers.
(tilegx_function_arg_advance): Ditto.
diff --git a/gcc/config/tilegx/tilegx-c.c b/gcc/config/tilegx/tilegx-c.c
index 909659b..e71965c 100644
--- a/gcc/config/tilegx/tilegx-c.c
+++ b/gcc/config/tilegx/tilegx-c.c
@@ -47,6 +47,9 @@ tilegx_cpu_cpp_builtins (struct cpp_reader *pfile)
if (TARGET_32BIT)
builtin_define (__tilegx32__);
+ builtin_define (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1);
+ builtin_define (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2);
+
TILEGX_CPU_CPP_ENDIAN_BUILTINS ();
GNU_USER_TARGET_OS_CPP_BUILTINS ();
}
diff --git a/gcc/config/tilepro/tilepro-c.c b/gcc/config/tilepro/tilepro-c.c
index dc2e3d0..4fd0337 100644
--- a/gcc/config/tilepro/tilepro-c.c
+++ b/gcc/config/tilepro/tilepro-c.c
@@ -44,6 +44,11 @@ tilepro_cpu_cpp_builtins (struct cpp_reader *pfile)
builtin_define (__tile_chip__=1);
builtin_define (__tile_chip_rev__=0);
+ builtin_define (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1);
+ builtin_define (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2);
+ builtin_define (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4);
+ builtin_define (__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8);
+
TILEPRO_CPU_CPP_ENDIAN_BUILTINS ();
GNU_USER_TARGET_OS_CPP_BUILTINS ();
}
[committed] TILE-Gx: implement 16-byte alignment for __int128 types.
This patch implements 16-byte alignment for __int128 types. In
particular:
- the stack is aligned to 16 bytes.
- objects of type __int128 will have 16-byte alignment.
- __int128 fields in structure have 16-byte alignment.
- __int128 function arguments: if they are in registers they will
always start with a even register. if they are in memory they will
have 16-byte alignment.
- stack slots will have 16-byte alignment.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c4a449e..dd93134 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,15 @@
2014-01-25 Walter Lee w...@tilera.com
+ * config/tilegx/tilegx.c (tilegx_function_arg): Start 16-byte
+ arguments on even registers.
+ (tilegx_gimplify_va_arg_expr): Align 16-byte var args to
+ STACK_BOUNDARY.
+ * config/tilegx/tilegx.h (STACK_BOUNDARY): Change to 16 bytes.
+ (BIGGEST_ALIGNMENT): Ditto.
+ (BIGGEST_FIELD_ALIGNMENT): Ditto.
+
+2014-01-25 Walter Lee w...@tilera.com
+
* config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier
insns after bundles have been formed.
* config/tilegx/tilegx.md (tile_network_barrier): Update
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index 7694e31..f3c68e3 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -220,10 +220,18 @@ tilegx_function_arg (cumulative_args_t cum_v,
CUMULATIVE_ARGS cum = *get_cumulative_args (cum_v);
int byte_size = ((mode == BLKmode)
? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
+ bool doubleword_aligned_p;
if (cum = TILEGX_NUM_ARG_REGS)
return NULL_RTX;
+ /* See whether the argument has doubleword alignment. */
+ doubleword_aligned_p =
+tilegx_function_arg_boundary (mode, type) BITS_PER_WORD;
+
+ if (doubleword_aligned_p)
+cum += cum 1;
+
/* The ABI does not allow parameters to be passed partially in reg
and partially in stack. */
if ((cum + (byte_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
@@ -245,6 +253,14 @@ tilegx_function_arg_advance (cumulative_args_t cum_v,
int byte_size = ((mode == BLKmode)
? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
int word_size = (byte_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ bool doubleword_aligned_p;
+
+ /* See whether the argument has doubleword alignment. */
+ doubleword_aligned_p =
+tilegx_function_arg_boundary (mode, type) BITS_PER_WORD;
+
+ if (doubleword_aligned_p)
+*cum += *cum 1;
/* If the current argument does not fit in the pretend_args space,
skip over it. */
@@ -417,7 +433,7 @@ tilegx_setup_incoming_varargs (cumulative_args_t cum,
generates code equivalent to:
-paddedsize = (sizeof(TYPE) + 3) -4;
+paddedsize = (sizeof(TYPE) + 7) -8;
if ( (VALIST.__args + paddedsize VALIST.__skip)
(VALIST.__args = VALIST.__skip))
addr = VALIST.__skip + STACK_POINTER_OFFSET;
@@ -457,9 +473,23 @@ tilegx_gimplify_va_arg_expr (tree valist, tree type,
gimple_seq *pre_p,
size = int_size_in_bytes (type);
rsize = ((size + UNITS_PER_WORD - 1) / UNITS_PER_WORD) * UNITS_PER_WORD;
- /* Assert alignment assumption. */
- gcc_assert (STACK_BOUNDARY == PARM_BOUNDARY);
+ /* If the alignment of the type is greater than the default for a
+ parameter, align to the STACK_BOUNDARY. */
+ if (TYPE_ALIGN (type) PARM_BOUNDARY)
+{
+ /* Assert the only case we generate code for: when
+stack boundary = 2 * parm boundary. */
+ gcc_assert (STACK_BOUNDARY == PARM_BOUNDARY * 2);
+
+ tmp = build2 (BIT_AND_EXPR, sizetype,
+ fold_convert (sizetype, unshare_expr (args)),
+ size_int (PARM_BOUNDARY / 8));
+ tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
+ unshare_expr (args), tmp);
+ gimplify_assign (unshare_expr (args), tmp, pre_p);
+}
+
/* Build conditional expression to calculate addr. The expression
will be gimplified later. */
tmp = fold_build_pointer_plus_hwi (unshare_expr (args), rsize);
diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h
index 68f466c..9eab51e 100644
--- a/gcc/config/tilegx/tilegx.h
+++ b/gcc/config/tilegx/tilegx.h
@@ -59,9 +59,9 @@
#define UNITS_PER_WORD 8
#define PARM_BOUNDARY BITS_PER_WORD
-#define STACK_BOUNDARY 64
+#define STACK_BOUNDARY 128
#define FUNCTION_BOUNDARY 64
-#define BIGGEST_ALIGNMENT 64
+#define BIGGEST_ALIGNMENT 128
#define STRICT_ALIGNMENT 1
#define INT_TYPE_SIZE 32
@@ -74,7 +74,7 @@
#define PCC_BITFIELD_TYPE_MATTERS 1
#define FASTEST_ALIGNMENT 64
-#define BIGGEST_FIELD_ALIGNMENT 64
+#define BIGGEST_FIELD_ALIGNMENT 128
#define WIDEST_HARDWARE_FP_SIZE 64
/* Unaligned moves trap and are very slow. */
[committed] TILEPro/TILE-Gx: fix atomic_nand_and_fetch in libgcc.
This patch fixes a bug in the atomic_nand_fetch routine in libgcc.
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index cb6885e..56c58dd 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,10 @@
+2014-01-25 Walter Lee w...@tilera.com
+
+ * config/tilepro/atomic.c (__atomic_do_and_fetch): Add
+ a prefix op argument.
+ (__atomic_nand_fetch_4): Add prefix op.
+ (__atomic_nand_fetch_8): Ditto.
+
2014-01-21 Baruch Siach ba...@tkos.co.il
* config.host (tmake_file): add t-slibgcc-libgcc for xtensa*-*-linux*.
diff --git a/libgcc/config/tilepro/atomic.c b/libgcc/config/tilepro/atomic.c
index b3458ae..9919323 100644
--- a/libgcc/config/tilepro/atomic.c
+++ b/libgcc/config/tilepro/atomic.c
@@ -85,27 +85,29 @@ __atomic_fetch_and_do (long long, 8, or)
__atomic_fetch_and_do (long long, 8, and)
__atomic_fetch_and_do (long long, 8, xor)
__atomic_fetch_and_do (long long, 8, nand)
-#define __atomic_do_and_fetch(type, size, opname, op) \
+
+#define __atomic_do_and_fetch(type, size, opname, op, op2) \
type \
__atomic_##opname##_fetch_##size(type* p, type i, int model) \
{ \
pre_atomic_barrier(model); \
- type rv = arch_atomic_##opname(p, i) op i; \
+ type rv = op2 (arch_atomic_##opname(p, i) op i); \
post_atomic_barrier(model); \
return rv; \
}
-__atomic_do_and_fetch (int, 4, add, +)
-__atomic_do_and_fetch (int, 4, sub, -)
-__atomic_do_and_fetch (int, 4, or, |)
-__atomic_do_and_fetch (int, 4, and, )
-__atomic_do_and_fetch (int, 4, xor, |)
-__atomic_do_and_fetch (int, 4, nand, )
-__atomic_do_and_fetch (long long, 8, add, +)
-__atomic_do_and_fetch (long long, 8, sub, -)
-__atomic_do_and_fetch (long long, 8, or, |)
-__atomic_do_and_fetch (long long, 8, and, )
-__atomic_do_and_fetch (long long, 8, xor, |)
-__atomic_do_and_fetch (long long, 8, nand, )
+__atomic_do_and_fetch (int, 4, add, +, )
+__atomic_do_and_fetch (int, 4, sub, -, )
+__atomic_do_and_fetch (int, 4, or, |, )
+__atomic_do_and_fetch (int, 4, and, , )
+__atomic_do_and_fetch (int, 4, xor, |, )
+__atomic_do_and_fetch (int, 4, nand, , ~)
+__atomic_do_and_fetch (long long, 8, add, +, )
+__atomic_do_and_fetch (long long, 8, sub, -, )
+__atomic_do_and_fetch (long long, 8, or, |, )
+__atomic_do_and_fetch (long long, 8, and, , )
+__atomic_do_and_fetch (long long, 8, xor, |, )
+__atomic_do_and_fetch (long long, 8, nand, , ~)
+
#define __atomic_exchange_methods(type, size) \
bool \
__atomic_compare_exchange_##size(volatile type* ptr, type* oldvalp,\
@@ -129,6 +131,7 @@ __atomic_exchange_##size(volatile type* ptr, type val, int
model) \
post_atomic_barrier(model); \
return retval; \
}
+
__atomic_exchange_methods (int, 4)
__atomic_exchange_methods (long long, 8)
@@ -137,6 +140,7 @@ __atomic_exchange_methods (long long, 8)
desired subword piece, then compare-and-exchange it into place. */
#define u8 unsigned char
#define u16 unsigned short
+
#define __atomic_subword_cmpxchg(type, size) \
\
bool \
@@ -161,8 +165,10 @@ __atomic_compare_exchange_##size(volatile type* ptr, type*
guess, \
*guess = oldval; \
return success; \
}
+
__atomic_subword_cmpxchg (u8, 1)
__atomic_subword_cmpxchg (u16, 2)
+
/* For the atomic-update subword methods, we use the same approach as
above, but we retry until we succeed if the compare-and-exchange
fails. */
@@ -185,36 +191,42 @@ proto
\
} while (__builtin_expect(xword != oldword, 0)); \
bottom \
}
+
#define __atomic_subword_fetch(type, funcname, expr, retval) \
__atomic_subword(type, \
type __atomic_ ## funcname(volatile type *ptr, type i, int
model), \
pre_atomic_barrier(model);, \
expr,\
post_atomic_barrier(model); return retval;)
+
__atomic_subword_fetch (u8, fetch_add_1, oldval + i, oldval)
__atomic_subword_fetch (u8, fetch_sub_1, oldval - i, oldval)
__atomic_subword_fetch (u8, fetch_or_1, oldval | i, oldval)
__atomic_subword_fetch (u8
[committed] TILE-Gx: fix atomic_fetch_sub pattern.
This patch fixes a bug in the atomic_fetch_sub pattern. The negation
is wrong and a register was getting clobbered.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5d7adb7..15e9194 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2014-01-25 Walter Lee w...@tilera.com
+ * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and
+ avoid clobbering a live register.
+
+2014-01-25 Walter Lee w...@tilera.com
+
* config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins):
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}.
* config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins):
diff --git a/gcc/config/tilegx/sync.md b/gcc/config/tilegx/sync.md
index 5860257..3d93493 100644
--- a/gcc/config/tilegx/sync.md
+++ b/gcc/config/tilegx/sync.md
@@ -150,15 +150,22 @@
(match_operand:SI 3 const_int_operand )] ;; model
{
+ rtx addend;
enum memmodel model = (enum memmodel) INTVAL (operands[3]);
if (operands[2] != const0_rtx)
-emit_move_insn (operands[2], gen_rtx_NEG (MODEmode, operands[2]));
+{
+ addend = gen_reg_rtx (MODEmode);
+ emit_move_insn (addend,
+ gen_rtx_MINUS (MODEmode, const0_rtx, operands[2]));
+}
+ else
+addend = operands[2];
tilegx_pre_atomic_barrier (model);
emit_insn (gen_atomic_fetch_add_baremode (operands[0],
operands[1],
- operands[2]));
+ addend));
tilegx_post_atomic_barrier (model);
DONE;
})
[committed] TILE-Gx: bundling fix for stack protector patterns.
This patch fixes a bundling bug with code that uses stack protector.
A barrier (which emits nothing) may be scheduled in the same bundle as
a stack protector sequence -- when that happens the bundle markers
would be emitted incorrectly. The fix is to just delete these barrier
insns after bundles have been formed.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 39543a1..7c8fa86 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
2014-01-25 Walter Lee w...@tilera.com
+ * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier
+ insns before bundling.
+ * config/tilegx/tilegx.md (tile_network_barrier): Update
+ comment.
+
+2014-01-25 Walter Lee w...@tilera.com
+
* config/tilegx/tilegx.c (tilegx_expand_builtin): Set
PREFETCH_SCHEDULE_BARRIER_P to true for prefetches.
* config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto.
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index c168621..7694e31 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -4401,10 +4401,12 @@ tilegx_gen_bundles (void)
basic_block bb;
FOR_EACH_BB_FN (bb, cfun)
{
- rtx insn, next;
+ rtx insn, next, prev;
rtx end = NEXT_INSN (BB_END (bb));
- for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
+ prev = NULL_RTX;
+ for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn;
+ prev = insn, insn = next)
{
next = next_insn_to_bundle (NEXT_INSN (insn), end);
@@ -4429,6 +4431,18 @@ tilegx_gen_bundles (void)
PUT_MODE (insn, SImode);
}
}
+
+ /* Delete barrier insns, because they can mess up the
+emitting of bundle braces. If it is end-of-bundle, then
+the previous insn must be marked end-of-bundle. */
+ if (get_attr_type (insn) == TYPE_NOTHING) {
+ if (GET_MODE (insn) == QImode prev != NULL
+GET_MODE (prev) == SImode)
+ {
+ PUT_MODE (prev, QImode);
+ }
+ delete_insn (insn);
+ }
}
}
}
diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index 1e82abc..c8c7af6 100644
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -5171,10 +5171,8 @@
;; Network intrinsics
-;; Note the pseudo text is handled specially by the
-;; asm_output_opcode routine. If the output is an empty string, the
-;; instruction would bypass the asm_output_opcode routine, bypassing
-;; the bundle handling code.
+;; Note the this barrier is of type nothing, which is deleted after
+;; the final scheduling pass so that nothing is emitted for it.
(define_insn tilegx_network_barrier
[(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]
[committed] TILEPro/TILE-Gx: fix include file issue in atomic.c.
This patch fixes an include file issue in atomic.c. It should include tconfig.h instead of config.h and system.h. Also define bool explicitly. diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 2504076..0ae676f 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,5 +1,11 @@ 2014-01-25 Walter Lee w...@tilera.com + * config/tilepro/atomic.c: Include tconfig.h. Don't include + config.h or system.h. + (bool) Define. + +2014-01-25 Walter Lee w...@tilera.com + * config/tilepro/atomic.c (pre_atomic_barrier): Mark inline. (post_atomic_barrier): Ditto. (__fetch_and_do): New macro. diff --git a/libgcc/config/tilepro/atomic.c b/libgcc/config/tilepro/atomic.c index 2df73b5..66ef8fd 100644 --- a/libgcc/config/tilepro/atomic.c +++ b/libgcc/config/tilepro/atomic.c @@ -21,11 +21,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see http://www.gnu.org/licenses/. */ -#include config.h -#include system.h +#include tconfig.h #include coretypes.h #include atomic.h +#define bool unsigned char + /* This code should be inlined by the compiler, but for now support it as out-of-line methods in libgcc. */
[committed] TILEPro/TILE-Gx: fix atomic.c for big endian.
This patch fixes atomic.c for big endian configurations.
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 56c58dd..bcd6cb1 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,5 +1,11 @@
2014-01-25 Walter Lee w...@tilera.com
+ * config/tilepro/atomic.c (BIT_OFFSET): Define.
+ (__atomic_subword_cmpxchg): Use BIT_OFFSET.
+ (__atomic_subword): Ditto.
+
+2014-01-25 Walter Lee w...@tilera.com
+
* config/tilepro/atomic.c (__atomic_do_and_fetch): Add
a prefix op argument.
(__atomic_nand_fetch_4): Add prefix op.
diff --git a/libgcc/config/tilepro/atomic.c b/libgcc/config/tilepro/atomic.c
index 9919323..2ad114a 100644
--- a/libgcc/config/tilepro/atomic.c
+++ b/libgcc/config/tilepro/atomic.c
@@ -135,6 +135,12 @@ __atomic_exchange_##size(volatile type* ptr, type val, int
model) \
__atomic_exchange_methods (int, 4)
__atomic_exchange_methods (long long, 8)
+#ifdef __LITTLE_ENDIAN__
+#define BIT_OFFSET(n, type) ((n) * 8)
+#else
+#define BIT_OFFSET(n, type) ((4 - sizeof(type) - (n)) * 8)
+#endif
+
/* Subword methods require the same approach for both TILEPro and
TILE-Gx. We load the background data for the word, insert the
desired subword piece, then compare-and-exchange it into place. */
@@ -150,7 +156,7 @@ __atomic_compare_exchange_##size(volatile type* ptr, type*
guess, \
{ \
pre_atomic_barrier(models); \
unsigned int *p = (unsigned int *)((unsigned long)ptr ~3UL); \
- const int shift = ((unsigned long)ptr 3UL) * 8;\
+ const int shift = BIT_OFFSET((unsigned long)ptr 3UL, type);
\
const unsigned int valmask = (1 (sizeof(type) * 8)) - 1; \
const unsigned int bgmask = ~(valmask shift); \
unsigned int oldword = *p; \
@@ -177,7 +183,7 @@ proto
\
{ \
top \
unsigned int *p = (unsigned int *)((unsigned long)ptr ~3UL); \
- const int shift = ((unsigned long)ptr 3UL) * 8;\
+ const int shift = BIT_OFFSET((unsigned long)ptr 3UL, type);
\
const unsigned int valmask = (1 (sizeof(type) * 8)) - 1; \
const unsigned int bgmask = ~(valmask shift); \
unsigned int oldword, xword = *p;\
[committed] TILEPro/TILE-Gx: add __sync intrinsics to libgcc.
This patch adds the legacy __sync intrinsics to libgcc, for backward
compatability.
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index bcd6cb1..2504076 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,5 +1,87 @@
2014-01-25 Walter Lee w...@tilera.com
+ * config/tilepro/atomic.c (pre_atomic_barrier): Mark inline.
+ (post_atomic_barrier): Ditto.
+ (__fetch_and_do): New macro.
+ (__atomic_fetch_and_do): Use __fetch_and_do.
+ (__sync_fetch_and_do): New macro.
+ (__sync_fetch_and_add_4): New function.
+ (__sync_fetch_and_sub_4): New function.
+ (__sync_fetch_and_or_4): New function.
+ (__sync_fetch_and_and_4): New function.
+ (__sync_fetch_and_xor_4): New function.
+ (__sync_fetch_and_nand_4): New function.
+ (__sync_fetch_and_add_8): New function.
+ (__sync_fetch_and_sub_8): New function.
+ (__sync_fetch_and_or_8): New function.
+ (__sync_fetch_and_and_8): New function.
+ (__sync_fetch_and_xor_8): New function.
+ (__sync_fetch_and_nand_8): New function.
+ (__do_and_fetch): New macro.
+ (__atomic_do_and_fetch): Use __do_and_fetch.
+ (__sync_do_and_fetch): New macro.
+ (__sync_add_and_fetch_4): New function.
+ (__sync_sub_and_fetch_4): New function.
+ (__sync_or_and_fetch_4): New function.
+ (__sync_and_and_fetch_4): New function.
+ (__sync_xor_and_fetch_4): New function.
+ (__sync_nand_and_fetch_4): New function.
+ (__sync_add_and_fetch_8): New function.
+ (__sync_sub_and_fetch_8): New function.
+ (__sync_or_and_fetch_8): New function.
+ (__sync_and_and_fetch_8): New function.
+ (__sync_xor_and_fetch_8): New function.
+ (__sync_nand_and_fetch_8): New function.
+ (__sync_exchange_methods): New macro.
+ (__sync_val_compare_and_swap_4): New function.
+ (__sync_bool_compare_and_swap_4): New function.
+ (__sync_lock_test_and_test_4): New function.
+ (__sync_val_compare_and_swap_8): New function.
+ (__sync_bool_compare_and_swap_8): New function.
+ (__sync_lock_test_and_test_8): New function.
+ (__subword_cmpxchg_body): New macro.
+ (__atomic_compare_exchange_1): Use __subword_cmpxchg_body.
+ (__atomic_compare_exchange_2): Ditto.
+ (__sync_subword_cmpxchg): New macro.
+ (__sync_val_compare_and_swap_1): New function.
+ (__sync_bool_compare_and_swap_1): New function.
+ (__sync_val_compare_and_swap_2): New function.
+ (__sync_bool_compare_and_swap_2): New function.
+ (__atomic_subword): Rename to ...
+ (__subword): ... New name.
+ (__atomic_subword_fetch): Use __subword.
+ (__sync_subword_fetch): New macro.
+ (__sync_fetch_and_add_1): New function.
+ (__sync_fetch_and_sub_1): New function.
+ (__sync_fetch_and_or_1): New function.
+ (__sync_fetch_and_and_1): New function.
+ (__sync_fetch_and_xor_1): New function.
+ (__sync_fetch_and_nand_1): New function.
+ (__sync_fetch_and_add_2): New function.
+ (__sync_fetch_and_sub_2): New function.
+ (__sync_fetch_and_or_2): New function.
+ (__sync_fetch_and_and_2): New function.
+ (__sync_fetch_and_xor_2): New function.
+ (__sync_fetch_and_nand_2): New function.
+ (__sync_add_and_fetch_1): New function.
+ (__sync_sub_and_fetch_1): New function.
+ (__sync_or_and_fetch_1): New function.
+ (__sync_and_and_fetch_1): New function.
+ (__sync_xor_and_fetch_1): New function.
+ (__sync_nand_and_fetch_1): New function.
+ (__sync_add_and_fetch_2): New function.
+ (__sync_sub_and_fetch_2): New function.
+ (__sync_or_and_fetch_2): New function.
+ (__sync_and_and_fetch_2): New function.
+ (__sync_xor_and_fetch_2): New function.
+ (__sync_nand_and_fetch_2): New function.
+ (__atomic_subword_lock): Use __subword.
+ (__sync_subword_lock): New macro.
+ (__sync_lock_test_and_set_1): New function.
+ (__sync_lock_test_and_set_2): New function.
+
+2014-01-25 Walter Lee w...@tilera.com
+
* config/tilepro/atomic.c (BIT_OFFSET): Define.
(__atomic_subword_cmpxchg): Use BIT_OFFSET.
(__atomic_subword): Ditto.
diff --git a/libgcc/config/tilepro/atomic.c b/libgcc/config/tilepro/atomic.c
index 2ad114a..2df73b5 100644
--- a/libgcc/config/tilepro/atomic.c
+++ b/libgcc/config/tilepro/atomic.c
@@ -29,7 +29,7 @@
/* This code should be inlined by the compiler, but for now support
it as out-of-line methods in libgcc. */
-static void
+static inline void
pre_atomic_barrier (int model)
{
switch ((enum memmodel) model)
@@ -45,7 +45,7 @@ pre_atomic_barrier (int model)
return;
}
-static void
+static inline void
post_atomic_barrier (int model)
{
switch ((enum memmodel) model)
@@ -63,16 +63,21 @@ post_atomic_barrier (int model)
#define __unused __attribute__((unused))
-#define
[committed] TILEPro atomics.[c,h] fixes
This patch cleans up a few issues with atomic.h and atomic.c: remove a
few glibc include files to facilitate bootstrapping, but include
config.h in atomic.c. Add __extension__ where appropriate, and
replace int64_t with long long.
* config/tilepro/atomic.h: Don't include stdint.h or features.h.
Replace int64_t with long long. Add __extension__ where
appropriate.
* config/tilepro/atomic.c: Include config.h.
--- trunk/libgcc/config/tilepro/atomic.h2013/02/04 19:06:20 195731
+++ trunk/libgcc/config/tilepro/atomic.h2013/06/08 16:26:32 199855
@@ -92,8 +92,6 @@
compare-and-exchange routine, so may be potentially less efficient. */
#endif
-#include stdint.h
-#include features.h
#ifdef __tilegx__
#include arch/spr_def.h
#else
@@ -122,9 +120,9 @@
/* 64-bit integer compare-and-exchange. */
static __inline __attribute__ ((always_inline))
- int64_t arch_atomic_val_compare_and_exchange_8 (volatile int64_t * mem,
-int64_t oldval,
-int64_t newval)
+ long long arch_atomic_val_compare_and_exchange_8 (volatile long long
+ *mem, long long oldval,
+ long long newval)
{
#ifdef __tilegx__
__insn_mtspr (SPR_CMPEXCH_VALUE, oldval);
@@ -139,7 +137,7 @@
R04 (newval_lo), R05 (newval_hi),
m (*mem):r20, r21, r22, r23, r24, r25,
r26, r27, r28, r29, memory);
- return ((uint64_t) result_hi) 32 | result_lo;
+ return ((long long) result_hi) 32 | result_lo;
#endif
}
@@ -150,11 +148,11 @@
#define arch_atomic_val_compare_and_exchange(mem, o, n) \
- ({\
+ __extension__ ({ \
(__typeof(*(mem)))(__typeof(*(mem)-*(mem))) \
((sizeof(*(mem)) == 8) ? \
arch_atomic_val_compare_and_exchange_8( \
- (volatile int64_t*)(mem), (__typeof((o)-(o)))(o), \
+ (volatile long long*)(mem), (__typeof((o)-(o)))(o),\
(__typeof((n)-(n)))(n)) : \
(sizeof(*(mem)) == 4) ? \
arch_atomic_val_compare_and_exchange_4( \
@@ -164,7 +162,7 @@
})
#define arch_atomic_bool_compare_and_exchange(mem, o, n)\
- ({\
+ __extension__ ({ \
__typeof(o) __o = (o); \
__builtin_expect( \
__o == arch_atomic_val_compare_and_exchange((mem), __o, (n)), 1); \
@@ -174,7 +172,7 @@
/* Loop with compare_and_exchange until we guess the correct value.
Normally expr will be an expression using __old and __value. */
#define __arch_atomic_update_cmpxchg(mem, value, expr) \
- ({\
+ __extension__ ({ \
__typeof(value) __value = (value); \
__typeof(*(mem)) *__mem = (mem), __old = *__mem, __guess; \
do {\
@@ -189,12 +187,14 @@
/* Generic atomic op with 8- or 4-byte variant.
The _mask, _addend, and _expr arguments are ignored on tilegx. */
#define __arch_atomic_update(mem, value, op, _mask, _addend, _expr) \
- ({\
+ __extension__ ({ \
((__typeof(*(mem))) \
((sizeof(*(mem)) == 8) ? (__typeof(*(mem)-*(mem)))__insn_##op( \
-(void *)(mem), (int64_t)(__typeof((value)-(value)))(value)) : \
+(volatile void *)(mem), \
+(long long)(__typeof((value)-(value)))(value)) :\
(sizeof(*(mem)) == 4) ? (int)__insn_##op##4( \
-(void *)(mem), (int32_t)(__typeof((value)-(value)))(value)) : \
+(volatile void *)(mem), \
+(int)(__typeof((value)-(value)))(value)) : \
__arch_atomic_error_bad_argument_size()));\
})
@@ -224,7 +224,7 @@
/* Generic atomic op with 8- or 4-byte variant.
The _op argument is ignored on tilepro. */
#define __arch_atomic_update(mem, value, _op, mask, addend, expr) \
- ({
Re: RFA: Fix use of extra_objs when configuring tilepro-linux and tilegx-linux
Hi Nick. Looks good. Thanks for fixing it.
Walter
On 4/21/2013 7:03 AM, Nick Clifton wrote:
Hi Walter,
The tilepro-gnu-linux and tilegx-gnu-linux currently fail to build in
the FSF mainline sources because of:
libbackend.a(tilepro.o):(.data+0x2e4): undefined reference to
`linux_android_has_ifunc_p()'
This happens because the entries for tilegx-linux and tilepro-linux in
config.gcc override the definition of extra_objs, rather than
extending it, thus loosing the inclusion of linux_android.o into
libbackend.a.
I fixed the problem with the patch below and was able to build both
toolchains. OK to apply ?
Cheers
Nick
gcc/ChangeLog
2013-04-21 Nick Clifton ni...@redhat.com
* config.gcc (tilegx-linux): Extend extra_objs rather than
overwriting it.
(tilepro-linux): Likewise.
Index: gcc/config.gcc
===
--- gcc/config.gcc (revision 198115)
+++ gcc/config.gcc (working copy)
@@ -2573,7 +2573,7 @@
tilegx-*-linux*)
tm_file=elfos.h gnu-user.h linux.h glibc-stdint.h tilegx/linux.h
${tm_file}
tmake_file=${tmake_file} tilegx/t-tilegx
- extra_objs=mul-tables.o
+ extra_objs=${extra_objs} mul-tables.o
c_target_objs=${c_target_objs} tilegx-c.o
cxx_target_objs=${cxx_target_objs} tilegx-c.o
extra_headers=feedback.h
@@ -2581,7 +2581,7 @@
tilepro-*-linux*)
tm_file=elfos.h gnu-user.h linux.h glibc-stdint.h tilepro/linux.h
${tm_file}
tmake_file=${tmake_file} tilepro/t-tilepro
- extra_objs=mul-tables.o
+ extra_objs=${extra_objs} mul-tables.o
c_target_objs=${c_target_objs} tilepro-c.o
cxx_target_objs=${cxx_target_objs} tilepro-c.o
extra_headers=feedback.h
[committed] TILE-Gx: fixes for vector pattern using const 0
This patch replaces (const_int 0) in vector patterns with its
const_vector representation. Backported to 4.7 and 4.8.
* config/tilegx/tilegx.md (insn_mnz_mode): Replaced by ...
(insn_mnz_v8qi): ... this ...
(insn_mnz_v4hi): ... and this. Replace (const_int 0) with the
vector equivalent.
(insn_vnmnz): Replaced by ...
(insn_v1mnz): ... this ...
(insn_v2mnz): ... and this. Replace (const_int 0) with the vector
equivalent.
(insn_mz_mode): Replaced by ...
(insn_mz_v8qi): ... this ...
(insn_mz_v4hi): ... and this. Replace (const_int 0) with the
vector equivalent.
(insn_vnmz): Replaced by ...
(insn_v1mz): ... this ...
(insn_v2mz): ... and this. Replace (const_int 0) with the vector
equivalent.
Index: gcc/config/tilegx/tilegx.md
===
--- gcc/config/tilegx/tilegx.md (revision 197134)
+++ gcc/config/tilegx/tilegx.md (working copy)
@@ -4597,57 +4597,147 @@
;; insn_v1mz
;; insn_v2mnz
;; insn_v2mz
-(define_insn insn_mnz_mode
- [(set (match_operand:VEC48MODE 0 register_operand =r)
- (if_then_else:VEC48MODE
- (ne:VEC48MODE
- (match_operand:VEC48MODE 1 reg_or_0_operand rO)
- (const_int 0))
- (match_operand:VEC48MODE 2 reg_or_0_operand rO)
- (const_int 0)))]
+(define_insn insn_mnz_v8qi
+ [(set (match_operand:V8QI 0 register_operand =r)
+ (if_then_else:V8QI
+ (ne:V8QI
+ (match_operand:V8QI 1 reg_or_0_operand rO)
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)]))
+ (match_operand:V8QI 2 reg_or_0_operand rO)
+(const_vector:V8QI [(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)])))]
- vnmnz\t%0, %r1, %r2
+ v1mnz\t%0, %r1, %r2
[(set_attr type X01)])
-(define_expand insn_vnmnz
+(define_expand insn_v1mnz
[(set (match_operand:DI 0 register_operand )
- (if_then_else:VEC48MODE
- (ne:VEC48MODE
+ (if_then_else:V8QI
+ (ne:V8QI
(match_operand:DI 1 reg_or_0_operand )
- (const_int 0))
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])
+ )
(match_operand:DI 2 reg_or_0_operand )
- (const_int 0)))]
+(const_vector:V8QI [(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)])))]
{
- tilegx_expand_builtin_vector_binop (gen_insn_mnz_mode, MODEmode,
- operands[0], MODEmode, operands[1],
+ tilegx_expand_builtin_vector_binop (gen_insn_mnz_v8qi, V8QImode,
+ operands[0], V8QImode, operands[1],
operands[2], true);
DONE;
})
-(define_insn insn_mz_mode
- [(set (match_operand:VEC48MODE 0 register_operand =r)
- (if_then_else:VEC48MODE
- (ne:VEC48MODE
- (match_operand:VEC48MODE 1 reg_or_0_operand rO)
- (const_int 0))
- (const_int 0)
- (match_operand:VEC48MODE 2 reg_or_0_operand rO)))]
+(define_insn insn_mz_v8qi
+ [(set (match_operand:V8QI 0 register_operand =r)
+ (if_then_else:V8QI
+ (ne:V8QI
+ (match_operand:V8QI 1 reg_or_0_operand rO)
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)]))
+(const_vector:V8QI [(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)
+(const_int 0) (const_int 0)])
+ (match_operand:V8QI 2 reg_or_0_operand rO)))]
- vnmz\t%0, %r1, %r2
+ v1mz\t%0, %r1, %r2
[(set_attr type X01)])
-(define_expand insn_vnmz
+
+(define_expand insn_v1mz
[(set (match_operand:DI 0 register_operand )
- (if_then_else:VEC48MODE
- (ne:VEC48MODE
+ (if_then_else:V8QI
+ (ne:V8QI
(match_operand:DI 1 reg_or_0_operand )
- (const_int 0))
- (const_int 0)
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int
[committed] TILE-Gx: fix type attribute for jr
This patch fixes the type attribute for jr. Backported to 4.7 and 4.8. * config/tilegx/tilegx.md (*sibcall_insn): Fix type atribute for jr. (*sibcall_value): Ditto. --- gcc/config/tilegx/tilegx.md (revision 197135) +++ gcc/config/tilegx/tilegx.md (working copy) @@ -2592,7 +2592,7 @@ @ jr\t%r0 j\t%p0 - [(set_attr type X1,X1)]) + [(set_attr type Y1,X1)]) (define_expand sibcall_value [(parallel [(set (match_operand 0 ) @@ -2611,7 +2611,7 @@ @ jr\t%r1 j\t%p1 - [(set_attr type X1,X1)]) + [(set_attr type Y1,X1)]) (define_insn jump [(set (pc) (label_ref (match_operand 0 )))]
[committed] TILE-Gx: fix type attribute for jr
This patch deletes an extra tab in the asm addr vectors. Backported
to 4.7 and 4.8.
* config/tilegx/tilegx.h (ASM_OUTPUT_ADDR_VEC_ELT): Delete
extra tab.
(ASM_OUTPUT_ADDR_DIFF_ELT): Ditto.
--- gcc/config/tilegx/tilegx.h (revision 197134)
+++ gcc/config/tilegx/tilegx.h (working copy)
@@ -448,7 +448,7 @@ enum reg_class
{ \
char label[256]; \
ASM_GENERATE_INTERNAL_LABEL (label, L, (VALUE)); \
- fprintf (FILE, \t%s , \
+ fprintf (FILE, %s ,\
integer_asm_op (GET_MODE_SIZE (Pmode), TRUE)); \
assemble_name (FILE, label); \
fprintf (FILE, \n);\
@@ -460,7 +460,7 @@ enum reg_class
{ \
char label[256]; \
ASM_GENERATE_INTERNAL_LABEL (label, L, (VALUE)); \
- fprintf (FILE, \t%s , \
+ fprintf (FILE, %s ,\
integer_asm_op (GET_MODE_SIZE (Pmode), TRUE)); \
assemble_name (FILE, label); \
ASM_GENERATE_INTERNAL_LABEL (label, L, (REL)); \
[committed] TILE-Gx/TILEPro: use pc relative/indirect encoding in eh data
This patch switches eh data to always use pc relative/indirect
encoding, to avoid relocations of unaligned words. Backported to 4.7
and 4.8.
* config/tilegx/tilegx.c (tilegx_asm_preferred_eh_data_format):
Use indirect/pcrel encoding.
* config/tilepro/tilepro.c (tilepro_asm_preferred_eh_data_format):
Ditto.
Index: gcc/config/tilegx/tilegx.c
===
--- gcc/config/tilegx/tilegx.c (revision 197072)
+++ gcc/config/tilegx/tilegx.c (working copy)
@@ -4786,13 +4786,8 @@ tilegx_reorg (void)
int
tilegx_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED, int global)
{
- if (flag_pic)
-{
- int type = TARGET_32BIT ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8;
- return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
-}
- else
-return DW_EH_PE_absptr;
+ int type = TARGET_32BIT ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8;
+ return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
}
Index: gcc/config/tilepro/tilepro.c
===
--- gcc/config/tilepro/tilepro.c(revision 197072)
+++ gcc/config/tilepro/tilepro.c(working copy)
@@ -4338,10 +4338,7 @@ tilepro_reorg (void)
int
tilepro_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED, int global)
{
- if (flag_pic)
-return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4;
- else
-return DW_EH_PE_absptr;
+ return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4;
}
[committed] TILE-Gx: speed up code to synthesize a constant
This patch inlines some tests while searching for the best way to
synthesize a constant, to avoid the need to generate an rtx. This
became expensive for code that generates a lot of constants.
Backported to 4.7 and 4.8.
* config/tilegx/tilegx.c (expand_set_cint64_one_inst): Inline
tests for constraint J, K, N, P.
Index: gcc/config/tilegx/tilegx.c
===
--- gcc/config/tilegx/tilegx.c (revision 197073)
+++ gcc/config/tilegx/tilegx.c (working copy)
@@ -1429,14 +1429,16 @@ expand_set_cint64_one_inst (rtx dest_reg
}
else if (!three_wide_only)
{
- rtx imm_op = GEN_INT (val);
-
- if (satisfies_constraint_J (imm_op)
- || satisfies_constraint_K (imm_op)
- || satisfies_constraint_N (imm_op)
- || satisfies_constraint_P (imm_op))
+ /* Test for the following constraints: J, K, N, P. We avoid
+generating an rtx and using existing predicates because we
+can be testing and rejecting a lot of constants, and GEN_INT
+is O(N). */
+ if ((val = -32768 val = 65535)
+ || ((val == (val 0xFF) * 0x0101010101010101LL))
+ || (val == ((trunc_int_for_mode (val, QImode) 0x)
+ * 0x0001000100010001LL)))
{
- emit_move_insn (dest_reg, imm_op);
+ emit_move_insn (dest_reg, GEN_INT (val));
return true;
}
}
[committed] TILE-Gx: add float conversion patterns.
This patch adds patterns for floatsisf2, floatunssisf2, floatsidf2,
and floatunssidf2.
* config/tilegx/tilegx.md (floatsisf2): New pattern.
(floatunssisf2): New pattern.
(floatsidf2): New pattern.
(floatunssidf2): New pattern.
Index: gcc/config/tilegx/tilegx.md
===
--- gcc/config/tilegx/tilegx.md (revision 197072)
+++ gcc/config/tilegx/tilegx.md (working copy)
@@ -2129,6 +2129,108 @@
rotl\t%0, %r1, %r2)
+;; Integer to floating point conversions
+
+(define_expand floatsisf2
+ [(set (match_operand:SF 0 register_operand )
+ (float:SI (match_operand:SI 1 register_operand )))]
+
+{
+ rtx result = gen_lowpart (DImode, operands[0]);
+ rtx a = operands[1];
+
+ rtx nega = gen_reg_rtx (SImode);
+ rtx exp = gen_reg_rtx (DImode);
+ rtx sign = gen_reg_rtx (DImode);
+ rtx abs = gen_reg_rtx (DImode);
+ rtx flags = gen_reg_rtx (DImode);
+ rtx tmp1 = gen_reg_rtx (DImode);
+ rtx tmp2 = gen_reg_rtx (DImode);
+
+ emit_move_insn (exp, GEN_INT (0x9e));
+
+ emit_insn (gen_negsi2 (nega, a));
+
+ emit_insn (gen_insn_cmplts_sisi (gen_lowpart (SImode, sign), a, const0_rtx));
+ emit_insn (gen_insn_cmoveqz (abs, gen_lowpart (DImode, nega), sign,
+ gen_lowpart (DImode, a)));
+
+ emit_insn (gen_insn_bfins (tmp1, exp, sign, GEN_INT (10), GEN_INT (10)));
+ emit_insn (gen_insn_bfins (tmp2, tmp1, abs, GEN_INT (32), GEN_INT (63)));
+ emit_insn (gen_insn_fsingle_pack1 (flags, tmp2));
+ emit_insn (gen_insn_fsingle_pack2 (result, tmp2, flags));
+ DONE;
+})
+
+(define_expand floatunssisf2
+ [(set (match_operand:SF 0 register_operand )
+ (float:SI (match_operand:SI 1 register_operand )))]
+
+{
+ rtx result = gen_lowpart (DImode, operands[0]);
+ rtx a = operands[1];
+
+ rtx exp = gen_reg_rtx (DImode);
+ rtx flags = gen_reg_rtx (DImode);
+ rtx tmp = gen_reg_rtx (DImode);
+
+ emit_move_insn (exp, GEN_INT (0x9e));
+ emit_insn (gen_insn_bfins (tmp, exp, gen_lowpart (DImode, a),
+ GEN_INT (32), GEN_INT (63)));
+ emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
+ emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
+ DONE;
+})
+
+(define_expand floatsidf2
+ [(set (match_operand:DF 0 register_operand )
+ (float:SI (match_operand:SI 1 register_operand )))]
+
+{
+ rtx result = gen_lowpart (DImode, operands[0]);
+ rtx a = gen_lowpart (DImode, operands[1]);
+
+ rtx nega = gen_reg_rtx (DImode);
+ rtx exp = gen_reg_rtx (DImode);
+ rtx sign = gen_reg_rtx (DImode);
+ rtx abs = gen_reg_rtx (DImode);
+ rtx tmp1 = gen_reg_rtx (DImode);
+ rtx tmp2 = gen_reg_rtx (DImode);
+ rtx tmp3 = gen_reg_rtx (DImode);
+
+ emit_move_insn (exp, GEN_INT (0x21b00));
+
+ emit_insn (gen_negdi2 (nega, a));
+
+ emit_insn (gen_insn_cmplts_didi (sign, a, const0_rtx));
+ emit_insn (gen_insn_cmovnez (abs, a, sign, nega));
+
+ emit_insn (gen_ashldi3 (tmp1, abs, GEN_INT (4)));
+ emit_insn (gen_insn_bfins (tmp2, exp, sign, GEN_INT (20), GEN_INT (20)));
+ emit_insn (gen_insn_fdouble_pack1 (tmp3, tmp1, tmp2));
+ emit_insn (gen_insn_fdouble_pack2 (result, tmp3, tmp1, const0_rtx));
+ DONE;
+})
+
+(define_expand floatunssidf2
+ [(set (match_operand:DF 0 register_operand )
+ (float:SI (match_operand:SI 1 register_operand )))]
+
+{
+ rtx result = gen_lowpart (DImode, operands[0]);
+ rtx a = gen_lowpart (DImode, operands[1]);
+
+ rtx exp = gen_reg_rtx (DImode);
+ rtx tmp1 = gen_reg_rtx (DImode);
+ rtx tmp2 = gen_reg_rtx (DImode);
+
+ emit_move_insn (exp, GEN_INT (0x21b00));
+ emit_insn (gen_insn_bfins (tmp1, const0_rtx, a, GEN_INT (4), GEN_INT (35)));
+ emit_insn (gen_insn_fdouble_pack1 (tmp2, tmp1, exp));
+ emit_insn (gen_insn_fdouble_pack2 (result, tmp2, tmp1, const0_rtx));
+ DONE;
+})
+
;;
;; Multiplies
[committed] TILE-Gx: add __insn_shufflebytes1 intrinsic
This patch adds the __insn_shufflebytes1, which takes only one argument.
result = __insn_shufflebytes1(input, select);
is equivalent to:
result = __insn_shufflebytes(result, input, select);
It has the advantage that the compiler will not waste a cycle
initializing result unnecessarily. It is the user's responsibility to
ensure that the select value is only selecting bytes from the second
operand. This has been backported to 4.7 and 4.8.
* config/tilegx/tilegx-builtins.h (enum tilegx_builtin): Add
TILEGX_INSN_SHUFFLEBYTES1.
* config/tilegx/tilegx.c (tilegx_builtin_info): Add entry for
shufflebytes1.
(tilegx_builtins): Ditto.
* config/tilegx/tilegx.md (insn_shufflebytes1): New pattern.
Index: gcc/config/tilegx/tilegx.md
===
--- gcc/config/tilegx/tilegx.md (revision 197079)
+++ gcc/config/tilegx/tilegx.md (working copy)
@@ -3959,6 +3959,15 @@
shufflebytes\t%0, %r2, %r3
[(set_attr type X0)])
+(define_insn insn_shufflebytes1
+ [(set (match_operand:DI 0 register_operand =r)
+(unspec:DI [(match_operand:DI 1 reg_or_0_operand rO)
+(match_operand:DI 2 reg_or_0_operand rO)]
+ UNSPEC_INSN_SHUFFLEBYTES))]
+
+ shufflebytes\t%0, %r1, %r2
+ [(set_attr type X0)])
+
;; stores
(define_expand insn_st
Index: gcc/config/tilegx/tilegx-builtins.h
===
--- gcc/config/tilegx/tilegx-builtins.h (revision 197072)
+++ gcc/config/tilegx/tilegx-builtins.h (working copy)
@@ -193,6 +193,7 @@ enum tilegx_builtin
TILEGX_INSN_SHRU,
TILEGX_INSN_SHRUX,
TILEGX_INSN_SHUFFLEBYTES,
+ TILEGX_INSN_SHUFFLEBYTES1,
TILEGX_INSN_ST,
TILEGX_INSN_ST1,
TILEGX_INSN_ST2,
Index: gcc/config/tilegx/tilegx.c
===
--- gcc/config/tilegx/tilegx.c (revision 197074)
+++ gcc/config/tilegx/tilegx.c (working copy)
@@ -2897,6 +2897,7 @@ static struct tile_builtin_info tilegx_b
{ CODE_FOR_lshrdi3, NULL }, /* shru */
{ CODE_FOR_lshrsi3, NULL }, /* shrux */
{ CODE_FOR_insn_shufflebytes, NULL }, /* shufflebytes */
+ { CODE_FOR_insn_shufflebytes1,NULL }, /* shufflebytes1 */
{ CODE_FOR_insn_st, NULL }, /* st */
{ CODE_FOR_insn_st1, NULL }, /* st1 */
{ CODE_FOR_insn_st2, NULL }, /* st2 */
@@ -3225,6 +3226,7 @@ static const struct tilegx_builtin_def t
{ __insn_shrux, TILEGX_INSN_SHRUX, true, iii
},
{ __insn_shruxi, TILEGX_INSN_SHRUX, true, iii
},
{ __insn_shufflebytes, TILEGX_INSN_SHUFFLEBYTES, true,
},
+ { __insn_shufflebytes1, TILEGX_INSN_SHUFFLEBYTES1, true, lll
},
{ __insn_st, TILEGX_INSN_ST, false, vpl
},
{ __insn_st1,TILEGX_INSN_ST1,false, vpl
},
{ __insn_st2,TILEGX_INSN_ST2,false, vpl
},
[committed] TILE-Gx: add flags to CRTSTUFF_T_CFLAGS_S variable.
This patch adds -fno-asynchronous-unwind-tables -mcmodel=large to CRTSTUFF_T_CFLAGS_S. Backported to 4.8. * config/tilegx/t-crtstuff: Add -fno-asynchronous-unwind-tables -mcmodel=large to CRTSTUFF_T_CFLAGS_S variable. Index: libgcc/config/tilegx/t-crtstuff === --- libgcc/config/tilegx/t-crtstuff (revision 197072) +++ libgcc/config/tilegx/t-crtstuff (working copy) @@ -2,3 +2,7 @@ # because then __FRAME_END__ might not be the last thing in .eh_frame # section. CRTSTUFF_T_CFLAGS += -fno-asynchronous-unwind-tables +CRTSTUFF_T_CFLAGS_S += -fno-asynchronous-unwind-tables + +# Compile crtbeginS.o and crtendS.o with -mcmodel=large +CRTSTUFF_T_CFLAGS_S += -mcmodel=large
[committed] TILE-Gx/TILEPro: define PROFILE_BEFORE_PROLOGUE
This patch puts profiling code before the prologue, to avoid clobbering used registers. Backported to 4.7 and 4.8. * config/tilegx/tilegx.h (PROFILE_BEFORE_PROLOGUE): Define. * config/tilegx/tilepro.h (PROFILE_BEFORE_PROLOGUE): Define. Index: gcc/config/tilegx/tilegx.h === --- gcc/config/tilegx/tilegx.h (revision 197083) +++ gcc/config/tilegx/tilegx.h (working copy) @@ -287,6 +287,8 @@ enum reg_class #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ ((OFFSET) = tilegx_initial_elimination_offset((FROM),(TO))) +#define PROFILE_BEFORE_PROLOGUE 1 + #define FUNCTION_PROFILER(FILE, LABELNO) \ tilegx_function_profiler (FILE, LABELNO) Index: gcc/config/tilepro/tilepro.h === --- gcc/config/tilepro/tilepro.h(revision 197083) +++ gcc/config/tilepro/tilepro.h(working copy) @@ -268,6 +268,8 @@ enum reg_class #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ ((OFFSET) = tilepro_initial_elimination_offset((FROM),(TO))) +#define PROFILE_BEFORE_PROLOGUE 1 + #define FUNCTION_PROFILER(FILE, LABELNO) \ tilepro_function_profiler (FILE, LABELNO)
[committed] TILE-Gx: add atomic test and set pattern
This patch adds an atomic test and set pattern on tilegx. Without
this pattern, libatomic currently fails to build on tilegx. Do I need
permission to backport this to the 4.8 branch?
Thanks,
Walter
* config/tilegx/sync.md (atomic_test_and_set): New pattern.
Index: gcc/config/tilegx/sync.md
===
--- gcc/config/tilegx/sync.md (revision 196804)
+++ gcc/config/tilegx/sync.md (working copy)
@@ -162,3 +162,49 @@
tilegx_post_atomic_barrier (model);
DONE;
})
+
+
+(define_expand atomic_test_and_set
+ [(match_operand:QI 0 register_operand ) ;; bool output
+ (match_operand:QI 1 nonautoincmem_operand +U);; memory
+ (match_operand:SI 2 const_int_operand )] ;; model
+
+{
+ rtx addr, aligned_addr, aligned_mem, offset, word, shmt;
+ rtx tmp0, tmp1;
+ rtx result = operands[0];
+ rtx mem = operands[1];
+ enum memmodel model = (enum memmodel) INTVAL (operands[2]);
+
+ addr = force_reg (Pmode, XEXP (mem, 0));
+
+ aligned_addr = gen_reg_rtx (Pmode);
+ emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-8)));
+
+ aligned_mem = change_address (mem, DImode, aligned_addr);
+ set_mem_alias_set (aligned_mem, 0);
+
+ offset = gen_reg_rtx (DImode);
+ emit_move_insn (offset, gen_rtx_AND (DImode, gen_lowpart (DImode, addr),
+ GEN_INT (7)));
+
+ tmp0 = gen_reg_rtx (DImode);
+ emit_move_insn (tmp0, GEN_INT (1));
+
+ shmt = gen_reg_rtx (DImode);
+ emit_move_insn (shmt, gen_rtx_ASHIFT (DImode, offset, GEN_INT (3)));
+
+ word = gen_reg_rtx (DImode);
+ emit_move_insn (word, gen_rtx_ASHIFT (DImode, tmp0,
+gen_lowpart (SImode, shmt)));
+
+ tmp1 = gen_reg_rtx (DImode);
+ tilegx_pre_atomic_barrier (model);
+ emit_insn (gen_atomic_fetch_or_baredi (tmp1, aligned_mem, word));
+ tilegx_post_atomic_barrier (model);
+
+ emit_move_insn (gen_lowpart (DImode, result),
+ gen_rtx_LSHIFTRT (DImode, tmp1,
+gen_lowpart (SImode, shmt)));
+ DONE;
+})
Re: Top Level GCC change questions
Not in GCC: 2012-09-15 Jiong Wang jiw...@tilera.com * configure.ac (ENABLE_GOLD): support tilegx* * configure: rebuild I pulled this into gcc. Walter
Re: [TILE-Gx, committed] support -mcmodel=MODEL
On 9/1/2012 7:33 AM, Gerald Pfeifer wrote:
On Tue, 28 Aug 2012, Walter Lee wrote:
This patch adds support for the -mcmodel=MODEL flag on TILE-Gx.
At which point I cannot help asking for an update to the
release notes at http://gcc.gnu.org/gcc-4.8/changes.html. ;-)
Let me know if you need help with that.
How does this look:
--- changes.html6 Sep 2012 03:42:45 - 1.28
+++ changes.html14 Sep 2012 20:40:39 -
@@ -298,6 +298,13 @@ by this change./p
liAdded optimized instruction scheduling for Niagara4./li
/ul
+h3 id=tilegxTILE-Gx/h3
+
+ ul
+liAdded support for the -mcmodel=MODEL command-line option. The
+models supported are small and large./li
+ /ul
+
h3 id=xstormy16XStormy16/h3
ul
@emph{TILEPro Options}
@gccoptlist{-mcpu=CPU -m32}
Why are only -mcpu and -m32 listed here?
Those are the only options supported on TILEPro. -m32 is basically a
no-op as tilepro does not support other models.
I've fixed the remaining grammar/spelling issues you pointed out. See
patch below.
Thanks,
Walter
* doc/invoke.texi (Option Summary): fix typesetting for -mcpu
option for TILEPro and TILE-Gx.
(TILE-Gx Options): Fix grammar and spellings in documentation for
-mcmodel.
--- gcc/doc/invoke.texi(revision 191306)
+++ gcc/doc/invoke.texi(working copy)
@@ -932,10 +932,10 @@ See RS/6000 and PowerPC Options.
@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
@emph{TILE-Gx Options}
-@gccoptlist{-mcpu=CPU -m32 -m64 -mcmodel=@var{code-model}}
+@gccoptlist{-mcpu=@var{cpu} -m32 -m64 -mcmodel=@var{code-model}}
@emph{TILEPro Options}
-@gccoptlist{-mcpu=CPU -m32}
+@gccoptlist{-mcpu=@var{cpu} -m32}
@emph{V850 Options}
@gccoptlist{-mlong-calls -mno-long-calls -mep -mno-ep @gol
@@ -19003,13 +19003,13 @@ These @samp{-m} options are supported on
@table @gcctabopt
@item -mcmodel=small
@opindex mcmodel=small
-Generate code for the small model. Distance for direct calls is
+Generate code for the small model. The distance for direct calls is
limited to 500M in either direction. PC-relative addresses are 32
bits. Absolute addresses support the full address range.
@item -mcmodel=large
@opindex mcmodel=large
-Generate code for the large model. There is no limiation on call
+Generate code for the large model. There is no limitation on call
distance, pc-relative addresses, or absolute addresses.
@item -mcpu=@var{name}
[TILE-Gx, committed] coding style fixes
This patch fixes some typos and coding style violations.
* confg/tilegx/tilegx.md: Fix code style.
(*zero_extendsidi_truncdisi): Fix typo.
* config/tilegx/tilegx.c: Fix code style.
(tilegx_function_profiler): Fix typo.
Index: gcc/config/tilegx/tilegx.md
===
--- gcc/config/tilegx/tilegx.md (revision 190737)
+++ gcc/config/tilegx/tilegx.md (working copy)
@@ -417,7 +417,7 @@
(ss_minus )
(us_minus )
])
-
+
;; s is the load/store extension suffix.
(define_code_attr s [(zero_extend u)
(sign_extend s)])
@@ -825,11 +825,11 @@
bit_width = INTVAL (operands[2]);
bit_offset = INTVAL (operands[3]);
- /* Reject bitfields that can be done with a normal load */
+ /* Reject bitfields that can be done with a normal load. */
if (MEM_ALIGN (operands[1]) = bit_offset + bit_width)
FAIL;
- /* The value in memory cannot span more than 8 bytes. */
+ /* The value in memory cannot span more than 8 bytes. */
first_byte_offset = bit_offset / BITS_PER_UNIT;
last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
if (last_byte_offset - first_byte_offset 7)
@@ -854,7 +854,6 @@
HOST_WIDE_INT bit_width = INTVAL (operands[2]);
HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
-
if (MEM_P (operands[1]))
{
HOST_WIDE_INT first_byte_offset, last_byte_offset;
@@ -862,11 +861,11 @@
if (GET_MODE (operands[1]) != QImode)
FAIL;
- /* Reject bitfields that can be done with a normal load */
+ /* Reject bitfields that can be done with a normal load. */
if (MEM_ALIGN (operands[1]) = bit_offset + bit_width)
FAIL;
- /* The value in memory cannot span more than 8 bytes. */
+ /* The value in memory cannot span more than 8 bytes. */
first_byte_offset = bit_offset / BITS_PER_UNIT;
last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
if (last_byte_offset - first_byte_offset 7)
@@ -882,7 +881,7 @@
if (bit_offset == 0)
{
-/* Extracting the low bits is just a bitwise AND. */
+/* Extracting the low bits is just a bitwise AND. */
HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 bit_width) - 1;
emit_insn (gen_anddi3 (operands[0], operands[1], GEN_INT (mask)));
DONE;
@@ -902,7 +901,7 @@
[(set (match_operand:DI 0 register_operand )
(const:DI (unspec:DI [(match_operand:DI 1 symbolic_operand )]
UNSPEC_HW2_LAST)))])
-
+
(define_expand mov_address_step2
[(set (match_operand:DI 0 register_operand )
(unspec:DI
@@ -954,7 +953,7 @@
%1 = . + 8\n\tlnk\t%0
[(set_attr type Y1)])
-;; First step of the 3-insn sequence to materialize a position
+;; The next three patterns are used to to materialize a position
;; independent address by adding the difference of two labels to a
;; base label in the text segment, assuming that the difference fits
;; in 32 signed bits.
@@ -966,10 +965,6 @@
UNSPEC_HW1_LAST_PCREL)))]
flag_pic)
-;; Second step of the 3-insn sequence to materialize a position
-;; independent address by adding the difference of two labels to a
-;; base label in the text segment, assuming that the difference fits
-;; in 32 signed bits.
(define_expand mov_pcrel_step2bitsuffix
[(set (match_operand:I48MODE 0 register_operand )
(unspec:I48MODE
@@ -980,11 +975,7 @@
UNSPEC_HW0_PCREL))]
UNSPEC_INSN_ADDR_SHL16INSLI))]
flag_pic)
-
-;; Third step of the 3-insn sequence to materialize a position
-;; independent address by adding the difference of two labels to a base
-;; label in the text segment, assuming that the difference fits in 32
-;; signed bits.
+
(define_insn mov_pcrel_step3bitsuffix
[(set (match_operand:I48MODE 0 register_operand =r)
(unspec:I48MODE [(match_operand:I48MODE 1 reg_or_0_operand rO)
@@ -1442,7 +1433,6 @@
DONE;
})
-
(define_expand subdf3
[(set (match_operand:DF 0 register_operand )
(minus:DF (match_operand:DF 1 register_operand )
@@ -1815,7 +1805,6 @@
ctz\t%0, %r1
[(set_attr type Y0)])
-
(define_insn popcountmode2
[(set (match_operand:I48MODE 0 register_operand =r)
(popcount:I48MODE (match_operand:DI 1 reg_or_0_operand rO)))]
@@ -2044,7 +2033,7 @@
(define_insn *zero_extendsidi_truncdisi
[(set (match_operand:DI 0 register_operand =r)
(zero_extend:DI
-(truncate:SI (match_operand:DI 1 reg_or_0_operand 0]
+(truncate:SI (match_operand:DI 1 reg_or_0_operand rO]
v4int_l\t%0, zero, %r1
[(set_attr type X01)])
@@ -2115,7 +2104,7 @@
shruxi\t%0, %r1, %2
shrux\t%0, %r1, %r2
[(set_attr type X01,X01)])
-
+
(define_insn *lshrsi_truncdisi2
[(set (match_operand:SI 0 register_operand =r)
[TILE-Gx, committed] fix atomic op latency
This patch properly sets the latency of atomic ops to the approximate latency of a remote memory operation. * config/tilegx/sync.md (atomic_compare_and_swap_baremode, atomic_exchange_baremode, atomic_fetch_fetchop_name_baremode): Set type to X1_remote. * config/tilegx/tilegx-generic.md (X1_remote): New insn_reservation. * config/tilegx/tilegx.md (type): Add X1_remove. (insn_cmpexchfour_if_si, insn_exchfour_if_si, insn_fetchaddfour_if_si, insn_fetchaddgezfour_if_si, insn_fetchandfour_if_si, insn_fetchorfour_if_si): Set type to X1_remote. Index: gcc/config/tilegx/tilegx.md === --- gcc/config/tilegx/tilegx.md (revision 190711) +++ gcc/config/tilegx/tilegx.md (working copy) @@ -250,7 +250,7 @@ ;; Define an insn type attribute. This defines what pipes things can go in. (define_attr type - X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing + X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_remote,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing (const_string Y01)) (define_attr length @@ -2679,7 +2679,7 @@ UNSPEC_INSN_CMPEXCH))] cmpexchfour_if_si\t%0, %r1, %r2 - [(set_attr type X1_L2)]) + [(set_attr type X1_remote)]) (define_insn insn_cmul [(set (match_operand:DI 0 register_operand =r) @@ -2817,7 +2817,7 @@ UNSPEC_INSN_EXCH))] exchfour_if_si\t%0, %r1, %r2 - [(set_attr type X1_2cycle)]) + [(set_attr type X1_remote)]) (define_insn insn_fdouble_add_flags [(set (match_operand:DI 0 register_operand =r) @@ -2903,7 +2903,7 @@ (match_operand:I48MODE 2 reg_or_0_operand rO)))] fetchaddfour_if_si\t%0, %r1, %r2 - [(set_attr type X1_2cycle)]) + [(set_attr type X1_remote)]) (define_insn insn_fetchaddgezfour_if_si [(set (match_operand:I48MODE 0 register_operand =r) @@ -2916,7 +2916,7 @@ UNSPEC_INSN_FETCHADDGEZ))] fetchaddgezfour_if_si\t%0, %r1, %r2 - [(set_attr type X1_2cycle)]) + [(set_attr type X1_remote)]) (define_insn insn_fetchandfour_if_si [(set (match_operand:I48MODE 0 register_operand =r) @@ -2928,7 +2928,7 @@ (match_operand:I48MODE 2 reg_or_0_operand rO)))] fetchandfour_if_si\t%0, %r1, %r2 - [(set_attr type X1_2cycle)]) + [(set_attr type X1_remote)]) (define_insn insn_fetchorfour_if_si [(set (match_operand:I48MODE 0 register_operand =r) @@ -2940,7 +2940,7 @@ (match_operand:I48MODE 2 reg_or_0_operand rO)))] fetchorfour_if_si\t%0, %r1, %r2 - [(set_attr type X1_2cycle)]) + [(set_attr type X1_remote)]) (define_insn insn_finv [(unspec_volatile:VOID [(match_operand 0 pointer_operand rO)] Index: gcc/config/tilegx/tilegx-generic.md === --- gcc/config/tilegx/tilegx-generic.md (revision 190711) +++ gcc/config/tilegx/tilegx-generic.md (working copy) @@ -51,6 +51,10 @@ (eq_attr type X1_L2) X1) +(define_insn_reservation X1_remote 50 + (eq_attr type X1_remote) + X1) + (define_insn_reservation X1_miss 80 (eq_attr type X1_miss) X1) Index: gcc/config/tilegx/sync.md === --- gcc/config/tilegx/sync.md (revision 190711) +++ gcc/config/tilegx/sync.md (working copy) @@ -72,7 +72,7 @@ UNSPEC_CMPXCHG))] cmpexchfour_if_si\t%0, %1, %r2 - [(set_attr type X1_L2)]) + [(set_attr type X1_remote)]) (define_expand atomic_exchangemode @@ -101,7 +101,7 @@ UNSPEC_XCHG))] exchfour_if_si\t%0, %1, %r2 - [(set_attr type X1_2cycle)]) + [(set_attr type X1_remote)]) (define_expand atomic_fetch_fetchop_namemode @@ -137,7 +137,7 @@ UNSPEC_ATOMIC))] fetchfetchop_namefour_if_si\t%0, %1, %r2 - [(set_attr type X1_2cycle)]) + [(set_attr type X1_remote)]) (define_expand atomic_fetch_submode
[TILE-Gx, committed] bfins instruction fix
This patch stops trying to represent the bfins instruction with the
insv pattern, because it causes an extra copy when bfins reuses one of
its inputs.
* config/tilegx/tilegx.md (*bfins): Rename to insn_bfins.
(insn_bfins): Delete.
Index: gcc/config/tilegx/tilegx.md
===
--- gcc/config/tilegx/tilegx.md (revision 190722)
+++ gcc/config/tilegx/tilegx.md (working copy)
@@ -2627,7 +2627,7 @@
bfextu\t%0, %r1, %2, %3
[(set_attr type X0)])
-(define_insn *bfins
+(define_insn insn_bfins
[(set (match_operand:DI 0 register_operand =r)
(unspec:DI [(match_operand:DI 1 reg_or_0_operand 0)
(match_operand:DI 2 reg_or_0_operand rO)
@@ -2638,36 +2638,6 @@
bfins\t%0, %r2, %3, %4
[(set_attr type X0)])
-(define_expand insn_bfins
- [(set (match_operand:DI 0 register_operand )
-(unspec:DI [(match_operand:DI 1 reg_or_0_operand )
-(match_operand:DI 2 reg_or_0_operand )
-(match_operand:DI 3 u6bit_cint_operand )
-(match_operand:DI 4 u6bit_cint_operand )]
- UNSPEC_INSN_BFINS))]
- INTVAL (operands[3]) != 64
-{
- HOST_WIDE_INT first = INTVAL (operands[3]);
- HOST_WIDE_INT last = INTVAL (operands[4]);
-
- if (last = first)
-{
- /* This is not a wacky wraparound case, so we can express this
- as a standard insv. */
- if (operands[0] != operands[1])
-{
- operands[2] = make_safe_from (operands[2], operands[0]);
- emit_move_insn (operands[0], operands[1]);
- }
-
- emit_insn (gen_insv (operands[0],
- GEN_INT (last - first + 1), operands[3],
- operands[2]));
-
- DONE;
-}
-})
-
(define_insn insn_cmpexchfour_if_si
[(set (match_operand:I48MODE 0 register_operand =r)
(mem:I48MODE (match_operand 1 pointer_operand rO)))
[TILE-Gx/TILEPro, committed] mcount typo
This patch fixes a typo in the mcount function_profiler.
* config/tilegx/tilegx.c (tilegx_function_profiler): Fix typo.
config/tilepro/tilepro.c (tilepro_function_profiler): Ditto.
Index: gcc/config/tilegx/tilegx.c
===
--- gcc/config/tilegx/tilegx.c (revision 190721)
+++ gcc/config/tilegx/tilegx.c (working copy)
@@ -5313,7 +5313,7 @@ tilegx_function_profiler (FILE *file, in
fprintf (file,
\t{\n
\tmove\tr10, lr\n
- \tjal\t%s@plt\n
+ \tjal\tplt(%s)\n
\t}\n, MCOUNT_NAME);
}
else
Index: gcc/config/tilepro/tilepro.c
===
--- gcc/config/tilepro/tilepro.c(revision 190721)
+++ gcc/config/tilepro/tilepro.c(working copy)
@@ -4914,7 +4914,7 @@ tilepro_function_profiler (FILE *file, i
fprintf (file,
\t{\n
\tmove\tr10, lr\n
- \tjal\t%s@plt\n
+ \tjal\tplt(%s)\n
\t}\n, MCOUNT_NAME);
}
else
[TILE-Gx, committed] support -mcmodel=MODEL
))]
+ flag_pic)
+
+(define_expand mov_plt_pcrel_step3
+ [(set (match_operand:DI 0 register_operand )
+ (unspec:DI
+[(match_operand:DI 1 reg_or_0_operand )
+ (const:DI
+ (unspec:DI [(match_operand:DI 2 symbolic_operand )
+ (match_operand:DI 3 symbolic_operand )]
+ UNSPEC_HW0_PLT_PCREL))]
+UNSPEC_INSN_ADDR_SHL16INSLI))]
+ flag_pic)
+
+;; The next two patterns are used to materialize a position independent
+;; 32-bit plt address by adding the difference of two labels to a base
+;; label in the text segment.
+(define_expand mov_plt_pcrel_step1_32bit
+ [(set (match_operand:SI 0 register_operand )
+ (const:SI (unspec:SI
+ [(match_operand:SI 1 symbolic_operand )
+(match_operand:SI 2 symbolic_operand )]
+UNSPEC_HW1_LAST_PLT_PCREL)))]
+ flag_pic)
+
+(define_expand mov_plt_pcrel_step2_32bit
+ [(set (match_operand:SI 0 register_operand )
+ (unspec:SI
+[(match_operand:SI 1 reg_or_0_operand )
+ (const:SI
+ (unspec:SI [(match_operand:SI 2 symbolic_operand )
+ (match_operand:SI 3 symbolic_operand )]
+ UNSPEC_HW0_PLT_PCREL))]
+UNSPEC_INSN_ADDR_SHL16INSLI))]
+ flag_pic)
+
(define_expand add_got16bitsuffix
[(set (match_operand:I48MODE 0 register_operand )
(plus:I48MODE
@@ -2300,7 +2407,29 @@
(use (reg:DI 54))
(clobber (reg:DI 55))])]
- )
+{
+ rtx orig_addr = XEXP (operands[0], 0);
+ rtx addr;
+ if (GET_CODE (orig_addr) == SYMBOL_REF)
+{
+ if (tilegx_cmodel == CM_LARGE)
+{
+ addr = gen_reg_rtx (Pmode);
+ tilegx_expand_set_const64 (addr, orig_addr);
+ operands[0] = gen_rtx_MEM (DImode, addr);
+}
+ else if (tilegx_cmodel == CM_LARGE_PIC)
+{
+ crtl-uses_pic_offset_table = 1;
+ addr = gen_reg_rtx (Pmode);
+ if (SYMBOL_REF_LOCAL_P (orig_addr))
+ tilegx_compute_pcrel_address (addr, orig_addr);
+ else
+ tilegx_compute_pcrel_plt_address (addr, orig_addr);
+ operands[0] = gen_rtx_MEM (DImode, addr);
+}
+}
+})
(define_insn *call_insn
[(call (mem:DI (match_operand:I48MODE 0 call_address_operand rO,i))
@@ -2319,7 +2448,30 @@
(match_operand 2 )))
(use (reg:DI 54))
(clobber (reg:DI 55))])]
- )
+
+{
+ rtx orig_addr = XEXP (operands[1], 0);
+ rtx addr;
+ if (GET_CODE (orig_addr) == SYMBOL_REF)
+{
+ if (tilegx_cmodel == CM_LARGE)
+{
+ addr = gen_reg_rtx (Pmode);
+ tilegx_expand_set_const64 (addr, orig_addr);
+ operands[1] = gen_rtx_MEM (DImode, addr);
+}
+ else if (tilegx_cmodel == CM_LARGE_PIC)
+{
+ crtl-uses_pic_offset_table = 1;
+ addr = gen_reg_rtx (Pmode);
+ if (SYMBOL_REF_LOCAL_P (orig_addr))
+ tilegx_compute_pcrel_address (addr, orig_addr);
+ else
+ tilegx_compute_pcrel_plt_address (addr, orig_addr);
+ operands[1] = gen_rtx_MEM (DImode, addr);
+}
+ }
+})
(define_insn *call_value_insn
[(set (match_operand 0 register_operand =r,r)
Index: gcc/config/tilegx/tilegx.opt
===
--- gcc/config/tilegx/tilegx.opt(revision 190736)
+++ gcc/config/tilegx/tilegx.opt(working copy)
@@ -19,6 +19,9 @@
; along with GCC; see the file COPYING3. If not see
; http://www.gnu.org/licenses/.
+HeaderInclude
+config/tilegx/tilegx-opts.h
+
mcpu=
Target RejectNegative Joined Enum(tilegx_cpu) Var(tilegx_cpu) Init(0)
-mcpu=CPU Use features of and schedule code for given CPU
@@ -38,3 +41,16 @@ m64
Target Report RejectNegative Negative(m32) InverseMask(32BIT, 64BIT)
Compile with 64 bit longs and pointers.
+mcmodel=
+Target RejectNegative Joined Enum(cmodel) Var(tilegx_cmodel) Init(CM_SMALL)
+Use given TILE-Gx code model
+
+Enum
+Name(cmodel) Type(enum cmodel)
+Known code models (for use with the -mcmodel= option):
+
+EnumValue
+Enum(cmodel) String(small) Value(CM_SMALL)
+
+EnumValue
+Enum(cmodel) String(large) Value(CM_LARGE)
Index: gcc/config/tilegx/tilegx-opts.h
===
--- gcc/config/tilegx/tilegx-opts.h (revision 0)
+++ gcc/config/tilegx/tilegx-opts.h (revision 0)
@@ -0,0 +1,34 @@
+/* Definitions for option handling for TILE-Gx.
+ Copyright (C) 2012
+ Free Software Foundation, Inc.
+ Contributed by Walter Lee (w...@tilera.com)
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful
[committed] TILE-Gx/TILEPro: add stubs for feedback instrumentation
This patch defines the stubs for feedback instrumentation, needed to compile glibc and linux. * config/tilegx/feedback.h (FEEDBACK_ENTER_EXPLICIT): Define. (FEEDBACK_ENTER): Define. (FEEDBACK_REENTER): Define. (FEEDBACK_ENTRY): Define. * config/tilepro/feedback.h: (FEEDBACK_ENTER_EXPLICIT): Define. (FEEDBACK_ENTER): Define. (FEEDBACK_REENTER): Define. (FEEDBACK_ENTRY): Define. Index: gcc/config/tilegx/feedback.h === --- gcc/config/tilegx/feedback.h(revision 190498) +++ gcc/config/tilegx/feedback.h(working copy) @@ -1 +1,14 @@ -/* This file is currently empty and serves as a placeholder. */ +#ifndef _FEEDBACK_H +#define _FEEDBACK_H 1 + +#ifdef __ASSEMBLER__ + +/* Stub defines for feedback instrumentation. */ +#define FEEDBACK_ENTER_EXPLICIT(FUNCNAME, SECNAME, SIZE) +#define FEEDBACK_ENTER(FUNCNAME) +#define FEEDBACK_REENTER(FUNCNAME) +#define FEEDBACK_ENTRY(FUNCNAME, SECNAME, SIZE) + +#endif /* __ASSEMBLER__ */ + +#endif /* _FEEDBACK_H */ Index: gcc/config/tilepro/feedback.h === --- gcc/config/tilepro/feedback.h (revision 190498) +++ gcc/config/tilepro/feedback.h (working copy) @@ -1 +1,14 @@ -/* This file is currently empty and serves as a placeholder. */ +#ifndef _FEEDBACK_H +#define _FEEDBACK_H 1 + +#ifdef __ASSEMBLER__ + +/* Stub defines for feedback instrumentation. */ +#define FEEDBACK_ENTER_EXPLICIT(FUNCNAME, SECNAME, SIZE) +#define FEEDBACK_ENTER(FUNCNAME) +#define FEEDBACK_REENTER(FUNCNAME) +#define FEEDBACK_ENTRY(FUNCNAME, SECNAME, SIZE) + +#endif /* __ASSEMBLER__ */ + +#endif /* _FEEDBACK_H */
[committed] TILE-Gx/TILEPro: add stub header file
This patch adds a stub header file feedback.h, needed to compile
glibc and linux.
Walter
Index: gcc/config.gcc
===
--- gcc/config.gcc (revision 190448)
+++ gcc/config.gcc (working copy)
@@ -2440,6 +2440,7 @@ tilegx-*-linux*)
extra_objs=mul-tables.o
c_target_objs=tilegx-c.o
cxx_target_objs=tilegx-c.o
+ extra_headers=feedback.h
;;
tilepro-*-linux*)
tm_file=elfos.h gnu-user.h linux.h glibc-stdint.h tilepro/linux.h
${tm_file}
@@ -2447,6 +2448,7 @@ tilepro-*-linux*)
extra_objs=mul-tables.o
c_target_objs=tilepro-c.o
cxx_target_objs=tilepro-c.o
+ extra_headers=feedback.h
;;
v850-*-rtems*)
target_cpu_default=TARGET_CPU_generic
Index: gcc/config/tilegx/feedback.h
===
--- gcc/config/tilegx/feedback.h(revision 0)
+++ gcc/config/tilegx/feedback.h(revision 0)
@@ -0,0 +1 @@
+/* This file is currently empty and serves as a placeholder. */
Index: gcc/config/tilepro/feedback.h
===
--- gcc/config/tilepro/feedback.h (revision 0)
+++ gcc/config/tilepro/feedback.h (revision 0)
@@ -0,0 +1 @@
+/* This file is currently empty and serves as a placeholder. */
Re: [PATCH, TileGX] Committed fix for a typo bug
Thanks. I found another one and I fixed it. 2012-06-15 Walter Lee w...@tilera.com * config/tilegx/sync.md (atomic_fetch_fetchop_namemode): Fix typo. Index: config/tilegx/sync.md === --- config/tilegx/sync.md (revision 188672) +++ config/tilegx/sync.md (working copy) @@ -121,7 +121,7 @@ emit_insn (gen_atomic_fetch_fetchop_name_baremode (operands[0], operands[1], operands[2])); - tilegx_pre_atomic_barrier (model); + tilegx_post_atomic_barrier (model); DONE; }) On 6/14/2012 6:46 PM, Maxim Kuvyrkov wrote: Walter, While working on atomics for a different target, I've noticed below typo bug in TileGX. Patch checked in as obvious. Thank you, -- Maxim Kuvyrkov CodeSourcery / Mentor Graphics
[committed] TILE-Gx/TILEPro: unwind fix for dynamic frames
This patch fixes an unwinding bug for functions with dynamic stack
frames. We stop generating REG_CFA_* notes for stack pointer, and at
the end of unwinding we restore the stack pointer by adjusting it by
EH_RETURN_STACKADJ_RTX.
Walter
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index fa739e3..217682e 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -3881,9 +3881,8 @@ tilegx_expand_prologue (void)
{
/* Copy the old stack pointer aside so we can save it later. */
sp_copy_regno = next_scratch_regno--;
- insn = FRP (emit_move_insn (gen_rtx_REG (Pmode, sp_copy_regno),
- stack_pointer_rtx));
- add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
+ emit_move_insn (gen_rtx_REG (Pmode, sp_copy_regno),
+ stack_pointer_rtx);
}
if (tilegx_current_function_is_leaf ())
@@ -3925,8 +3924,8 @@ tilegx_expand_prologue (void)
}
/* Save our frame pointer for backtrace chaining. */
- FRP (frame_emit_store (sp_copy_regno, STACK_POINTER_REGNUM,
-chain_addr, cfa, cfa_offset));
+ emit_insn (gen_movdi (gen_frame_mem (DImode, chain_addr),
+ gen_rtx_REG (DImode, sp_copy_regno)));
}
/* Compute where to start storing registers we need to save. */
@@ -4067,16 +4066,7 @@ tilegx_expand_epilogue (bool sibcall_p)
emit_insn (gen_blockage ());
- if (crtl-calls_eh_return)
-{
- rtx r = compute_frame_addr (-total_size + UNITS_PER_WORD,
- next_scratch_regno);
- insn = emit_move_insn (gen_lowpart (DImode, stack_pointer_rtx),
-gen_frame_mem (DImode, r));
- RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) = cfa_restores;
-}
- else if (frame_pointer_needed)
+ if (frame_pointer_needed)
{
/* Restore the old stack pointer by copying from the frame
pointer. */
@@ -4100,6 +4090,16 @@ tilegx_expand_epilogue (bool sibcall_p)
cfa_restores);
}
+ if (crtl-calls_eh_return)
+{
+ if (TARGET_32BIT)
+ emit_insn (gen_sp_adjust_32bit (stack_pointer_rtx, stack_pointer_rtx,
+ EH_RETURN_STACKADJ_RTX));
+ else
+ emit_insn (gen_sp_adjust (stack_pointer_rtx, stack_pointer_rtx,
+ EH_RETURN_STACKADJ_RTX));
+}
+
/* Restore the old frame pointer. */
if (frame_pointer_needed)
{
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index 71b5807..011ac08 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -3556,9 +3556,8 @@ tilepro_expand_prologue (void)
{
/* Copy the old stack pointer aside so we can save it later. */
sp_copy_regno = next_scratch_regno--;
- insn = FRP (emit_move_insn (gen_rtx_REG (Pmode, sp_copy_regno),
- stack_pointer_rtx));
- add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
+ emit_move_insn (gen_rtx_REG (Pmode, sp_copy_regno),
+ stack_pointer_rtx);
}
if (tilepro_current_function_is_leaf ())
@@ -3600,8 +3599,8 @@ tilepro_expand_prologue (void)
}
/* Save our frame pointer for backtrace chaining. */
- FRP (frame_emit_store (sp_copy_regno, STACK_POINTER_REGNUM,
-chain_addr, cfa, cfa_offset));
+ emit_insn (gen_movsi (gen_frame_mem (SImode, chain_addr),
+ gen_rtx_REG (SImode, sp_copy_regno)));
}
/* Compute where to start storing registers we need to save. */
@@ -3742,16 +3741,7 @@ tilepro_expand_epilogue (bool sibcall_p)
emit_insn (gen_blockage ());
- if (crtl-calls_eh_return)
-{
- rtx r = compute_frame_addr (-total_size + UNITS_PER_WORD,
- next_scratch_regno);
- insn = emit_move_insn (gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
-gen_frame_mem (Pmode, r));
- RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) = cfa_restores;
-}
- else if (frame_pointer_needed)
+ if (frame_pointer_needed)
{
/* Restore the old stack pointer by copying from the frame
pointer. */
@@ -3767,6 +3757,10 @@ tilepro_expand_epilogue (bool sibcall_p)
cfa_restores);
}
+ if (crtl-calls_eh_return)
+emit_insn (gen_sp_adjust (stack_pointer_rtx, stack_pointer_rtx,
+ EH_RETURN_STACKADJ_RTX));
+
/* Restore the old frame pointer. */
if (frame_pointer_needed)
{
[committed] TILEPro/TILE-Gx: rename internal atomic macros
This patch renames some internal atomic macros to have a less generic
prefix.
Walter
* config/tilepro/atomic.c: Rename atomic_ prefix to
arch_atomic_.
(atomic_xor): Rename and move definition to
config/tilepro/atomic.h.
(atomic_nand): Ditto.
* config/tilepro/atomic.h: Rename atomic_ prefix to
arch_atomic_.
(arch_atomic_xor): Move from config/tilepro/atomic.c.
(arch_atomic_nand): Ditto.
diff --git a/libgcc/config/tilepro/atomic.c b/libgcc/config/tilepro/atomic.c
index cafbde8..bdf8098 100644
--- a/libgcc/config/tilepro/atomic.c
+++ b/libgcc/config/tilepro/atomic.c
@@ -63,18 +63,12 @@ post_atomic_barrier (int model)
#define __unused __attribute__((unused))
-/* Provide additional methods not implemented by atomic.h. */
-#define atomic_xor(mem, mask) \
- __atomic_update_cmpxchg(mem, mask, __old ^ __value)
-#define atomic_nand(mem, mask) \
- __atomic_update_cmpxchg(mem, mask, ~(__old __value))
-
#define __atomic_fetch_and_do(type, size, opname) \
type \
__atomic_fetch_##opname##_##size(type* p, type i, int model) \
{ \
pre_atomic_barrier(model); \
- type rv = atomic_##opname(p, i); \
+ type rv = arch_atomic_##opname(p, i);\
post_atomic_barrier(model); \
return rv; \
}
@@ -96,7 +90,7 @@ type
\
__atomic_##opname##_fetch_##size(type* p, type i, int model) \
{ \
pre_atomic_barrier(model); \
- type rv = atomic_##opname(p, i) op i;\
+ type rv = arch_atomic_##opname(p, i) op i; \
post_atomic_barrier(model); \
return rv; \
}
@@ -120,7 +114,7 @@ __atomic_compare_exchange_##size(volatile type* ptr, type*
oldvalp, \
{ \
type oldval = *oldvalp; \
pre_atomic_barrier(models); \
- type retval = atomic_val_compare_and_exchange(ptr, oldval, newval); \
+ type retval = arch_atomic_val_compare_and_exchange(ptr, oldval, newval); \
post_atomic_barrier(models); \
bool success = (retval == oldval); \
*oldvalp = retval; \
@@ -131,7 +125,7 @@ type
\
__atomic_exchange_##size(volatile type* ptr, type val, int model) \
{ \
pre_atomic_barrier(model); \
- type retval = atomic_exchange(ptr, val); \
+ type retval = arch_atomic_exchange(ptr, val);
\
post_atomic_barrier(model); \
return retval; \
}
@@ -159,7 +153,7 @@ __atomic_compare_exchange_##size(volatile type* ptr, type*
guess, \
type oldval = (oldword shift) valmask; \
if (__builtin_expect((oldval == *guess), 1)) { \
unsigned int word = (oldword bgmask) | ((val valmask) shift); \
-oldword = atomic_val_compare_and_exchange(p, oldword, word); \
+oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \
oldval = (oldword shift) valmask; \
}\
post_atomic_barrier(models); \
@@ -187,7 +181,7 @@ proto
\
oldval = (oldword shift) valmask; \
val = expr;
\
unsigned int word = (oldword bgmask) | ((val valmask) shift); \
-xword = atomic_val_compare_and_exchange(p, oldword, word); \
+xword = arch_atomic_val_compare_and_exchange(p, oldword, word);\
} while (__builtin_expect(xword != oldword, 0)); \
bottom \
}
diff --git a/libgcc/config/tilepro/atomic.h b/libgcc/config/tilepro/atomic.h
index 16306fe..d49d13b 100644
--- a/libgcc/config/tilepro/atomic.h
+++ b/libgcc/config/tilepro/atomic.h
@@ -104,8 +104,8 @@
/* 32-bit integer
Re: [committed] TILE-Gx/TILEPro: unwind fix for dynamic frames
On 3/7/2012 1:01 PM, Walter Lee wrote: This patch fixes an unwinding bug for functions with dynamic stack frames. We stop generating REG_CFA_* notes for stack pointer, and at the end of unwinding we restore the stack pointer by adjusting it by EH_RETURN_STACKADJ_RTX. I forgot to attach the ChangeLog: * config/tilegx/tilegx.c (tilegx_expand_prologue): Don't generate REG_CFA_* notes for the stack pointer. (tilegx_expand_epilogue): Restore stack pointer by adjusting it by EH_RETURN_STACKADJ_RTX. * config/tilepro/tilepro.c (tilepro_expand_prologue): Don't generate REG_CFA_* notes for the stack pointer. (tilepro_expand_epilogue): Restore stack pointer by adjusting it by EH_RETURN_STACKADJ_RTX. Walter
[committed] TILE-Gx: Fix tilegx_fixup_pcrel_references
This patch fixes a bug in tilegx_fixup_pcrel_references, to properly
match and fixup the second instruction of the instruction sequence to
generate a pc relative address.
Walter
* config/tilegx/tilegx.c (match_pcrel_step2): Fix instruction
pattern.
(replace_mov_pcrel_step2): Ditto.
Index: gcc/config/tilegx/tilegx.c
===
--- gcc/config/tilegx/tilegx.c (revision 184581)
+++ gcc/config/tilegx/tilegx.c (working copy)
@@ -4420,7 +4420,9 @@ replace_mov_pcrel_step1 (rtx insn)
static bool
match_pcrel_step2 (rtx insn)
{
- rtx src;
+ rtx unspec;
+ rtx addr;
+
if (TARGET_32BIT)
{
if (recog_memoized (insn) != CODE_FOR_insn_addr_shl16insli_32bit)
@@ -4432,11 +4434,12 @@ match_pcrel_step2 (rtx insn)
return false;
}
- src = SET_SRC (PATTERN (insn));
+ unspec = SET_SRC (PATTERN (insn));
+ addr = XVECEXP (unspec, 0, 1);
- return (GET_CODE (src) == CONST
- GET_CODE (XEXP (src, 0)) == UNSPEC
- XINT (XEXP (src, 0), 1) == UNSPEC_HW0_PCREL);
+ return (GET_CODE (addr) == CONST
+ GET_CODE (XEXP (addr, 0)) == UNSPEC
+ XINT (XEXP (addr, 0), 1) == UNSPEC_HW0_PCREL);
}
@@ -4446,6 +4449,7 @@ replace_mov_pcrel_step2 (rtx insn)
{
rtx pattern = PATTERN (insn);
rtx unspec;
+ rtx addr;
rtx opnds[3];
rtx new_insns;
rtx got_rtx = tilegx_got_rtx ();
@@ -4453,10 +4457,18 @@ replace_mov_pcrel_step2 (rtx insn)
gcc_assert (GET_CODE (pattern) == SET);
opnds[0] = SET_DEST (pattern);
- unspec = XEXP (SET_SRC (pattern), 0);
+ unspec = SET_SRC (pattern);
+ gcc_assert (GET_CODE (unspec) == UNSPEC);
+ gcc_assert (XINT (unspec, 1) == UNSPEC_INSN_ADDR_SHL16INSLI);
+
+ opnds[1] = XVECEXP (unspec, 0, 0);
+
+ addr = XVECEXP (unspec, 0, 1);
+ gcc_assert (GET_CODE (addr) == CONST);
+
+ unspec = XEXP (addr, 0);
gcc_assert (GET_CODE (unspec) == UNSPEC);
gcc_assert (XINT (unspec, 1) == UNSPEC_HW0_PCREL);
- opnds[1] = XEXP (XEXP (SET_SRC (pattern), 0), 0);
opnds[2] = XVECEXP (unspec, 0, 0);
/* We only need to replace SYMBOL_REFs, not LABEL_REFs. */
Re: [wwwdocs] add information on TILE-Gx/TILEPro ports
On 2/17/2012 1:30 PM, Gerald Pfeifer wrote: On Tue, 14 Feb 2012, Walter Lee wrote: This patch adds information on the Tile-Gx/TILEPro ports to wwwdocs. Ok to commit? (assuming I have commit rights which I have not tried.) Yes (and yes). :-) If you'd like to mention your name in the news item, like we have in other cases, that would be perfectly fine as well. Great thanks. I added my name and committed. Walter
Re: [PING] New port resubmission for TILEPro and TILE-Gx
On 2/13/2012 6:30 PM, Mike Stump wrote: On Feb 13, 2012, at 1:43 PM, Walter Lee wrote: Thanks for the review. Do I have permission to commit, Yes, you do. Richard can approve this, and when he says, Ok., you're good to go. or is there anything else I need to do? Nope. (Assuming you have write after approval to the tree.) Great. Thanks. I have committed the changes. Walter
[wwwdocs] add information on TILE-Gx/TILEPro ports
This patch adds information on the Tile-Gx/TILEPro ports to wwwdocs. Ok to commit? (assuming I have commit rights which I have not tried.) Thanks, Walter Index: backends.html === RCS file: /cvs/gcc/wwwdocs/htdocs/backends.html,v retrieving revision 1.42 diff -u -p -r1.42 backends.html --- backends.html 5 Nov 2011 20:55:57 - 1.42 +++ backends.html 14 Feb 2012 17:24:36 - @@ -99,6 +99,8 @@ sh | Q CB qr da sparc| Q CB qr pda spu | ? Q *C p g bd stormy16 | ???L FIC D l p m a +tilegx | S Q Cq p g bda e +tilepro | S F C p g bda e v850 | ??FI cp gm d s vax | M?I cp a e xtensa | ? C p bd Index: index.html === RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v retrieving revision 1.833 diff -u -p -r1.833 index.html --- index.html 12 Feb 2012 18:55:35 - 1.833 +++ index.html 14 Feb 2012 17:24:36 - @@ -53,6 +53,11 @@ mission statement/a./p dl class=news +dtspanTILE-Gx and TILEPro processor support/span +span class=date[2012-02-14]/span/dt +ddPorts for the TILE-Gx and TILEPro families of processors have been +contributed by Tilera./dd + dtspanAtomic memory model support/span span class=date[2011-11-06]/span/dt ddC++11/C11 a href=http://gcc.gnu.org/wiki/Atomic/GCCMM;memory model/a Index: readings.html === RCS file: /cvs/gcc/wwwdocs/htdocs/readings.html,v retrieving revision 1.216 diff -u -p -r1.216 readings.html --- readings.html 5 Nov 2011 20:55:57 - 1.216 +++ readings.html 14 Feb 2012 17:24:36 - @@ -263,6 +263,16 @@ Intelreg;64 and IA-32 Architectures Sof br /Acronym stands for: Scalable Processor ARChitecture /li + litilegx + br /Manufacturer: Tilera + br /a href=http://www.tilera.com/scm/docs/index.html;Documentation/a + /li + + litilepro + br /Manufacturer: Tilera + br /a href=http://www.tilera.com/scm/docs/index.html;Documentation/a + /li + liv850 br /Manufacturer: NEC /li Index: gcc-4.7/changes.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v retrieving revision 1.82 diff -u -p -r1.82 changes.html --- gcc-4.7/changes.html13 Feb 2012 21:57:31 - 1.82 +++ gcc-4.7/changes.html14 Feb 2012 17:24:37 - @@ -715,6 +715,11 @@ well./p/li default on UltraSPARC T3 (Niagara 3) and later CPUs./li /ul +h3TILE-Gx/TILEPro/h3 + ul +liSupport has been added for the Tilera TILE-Gx and TILEPro families of + processors./li + /ul !-- h2Documentation improvements/h2
Re: [PING] New port resubmission for TILEPro and TILE-Gx
Ping. Can someone please review these ports? Here is a summary of the submission. Summary of changes in latest submit: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01854.html Latest submit: 1/6 toplevel: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01860.html 2/6 contrib: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01855.html 3/6 gcc: http://gcc.gnu.org/ml/gcc-patches/2012-01/msg01494.html 4/6 libcpp: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01857.html 5/6 libgcc: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01858.html 6/6 libgomp: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01859.html 1st round review comments: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01385.html http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01387.html 2nd round review comments: http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01232.html http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01247.html Thanks, Walter Lee
Re: [PING] New port resubmission for TILEPro and TILE-Gx
On 2/13/2012 3:02 PM, Richard Henderson wrote: On 02/13/2012 07:42 AM, Walter Lee wrote: 1/6 toplevel: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01860.html 2/6 contrib: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01855.html 3/6 gcc: http://gcc.gnu.org/ml/gcc-patches/2012-01/msg01494.html 4/6 libcpp: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01857.html 5/6 libgcc: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01858.html 6/6 libgomp: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01859.html Ok. r~ Hi Richard, Thanks for the review. Do I have permission to commit, or is there anything else I need to do? I will update the copyright notices with the year 2012. The assignment of copyright paperwork was filed on May 26, 2011 by Tilera Corporation. The gcc steering committee has approved my maintainership: http://gcc.gnu.org/ml/gcc/2012-02/msg00123.html. I have an account at sourceware.org. Can I use your name to get commit rights to gcc? Thanks, Walter
MAINTAINERS: add myself
Committed. 2012-02-14 Walter Lee w...@tilera.com * MAINTAINERS (Write After Approval): Add myself. Index: MAINTAINERS === --- MAINTAINERS (revision 184193) +++ MAINTAINERS (working copy) @@ -428,6 +428,7 @@ Asher Langton langt...@llnl.gov Chris Lattner sa...@nondot.org Terry Laurenzo tlaure...@gmail.com Georg-Johann Lay a...@gjlay.de +Walter Lee w...@tilera.com Marc Lehmann p...@goof.com James Lemkejwle...@codesourcery.com Kriang Lerdsuwanakij lerds...@users.sourceforge.net
Re: [PING2] New port resubmission for TILEPro and TILE-Gx
Still looking for review. It's been about a month and a half.
Thanks,
Walter
On 1/27/2012 12:47 PM, Walter Lee wrote:
Ping? It's been a month. Seeing more feedback or status update.
Thanks,
Walter Lee
On 12/30/2011 7:30 PM, Walter Lee wrote:
I'm resubmitting the gcc ports to TILE-Gx and TILEPro as replies to
this email. The resubmission addresses the feedback made by Richard
Henderson in:
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01232.html, and
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01247.html
Feedback by Joseph Myers made in:
http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01385.html
http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01387.html
was addressed in a previous submission.
Here is a summary of the issues addressed:
Changes made to both ports:
- added vector patterns for suitable vector ops.
- cleaned up various move pattens, deleting dead alternatives,
deleting redundant immediate insn_and_split patterns, and delete
unnecessary movdi multi-word move pattern (tilepro only).
- added extra insv patterns.
- combined all the conditional moves into one pattern.
- combined *lh and *extendhisi2 pattern, and *lb and
*extendqihi2.
- partially remove the divsi stubs that were there to work around an
old gcc bug that has been partially fixed. Previously gcc would not
turn divide by constant into multiply by constant unless there is a
pattern for the divide of the given mode. It now seems to do
better, but we still need the stub on tilegx, else it turns 32-bit
divide by constant into 64-bit multiply by constant.
- wrap the GOT and TLS unspec addresses in const, and handle them with
a single pattern.
- add support for post_{inc,dec,modify} addressing modes.
- fixed invalid rtl sharing in alloca handling routines.
- use REG_CFA_* notes in prologue and epilogue.
- Use post-inc load in TARGET_ASM_TRAMPOLINE_TEMPLATE.
- converted the following to target hooks: LIBCALL_VALUE,
FUNCTION_VALUE_REGNO_P, GO_IF_LEGITIMATE_ADDRESS. Delete
GO_IF_MODE_DEPENDENT_ADDRESS and use the default.
- use the new atomics_ names and patterns.
Changes made to tilegx port:
- merged the AND patterns.
- add patterns that sign extends an SI result to DI for all the 32-bit
insns.
Here are replies to a few feedback items:
optabs.c will do exactly this if the pattern is not present. Similarly
for the DImode logicals (popcount, parity, etc).
I tried taking out the patterns for ctzdi2, clzdi2, ffsdi2, paritydi2,
and popcountdi2, and I found that the compiler generates libgcc
function calls for all of them except clzdi2. For clzdi2 the tilepro
pattern is better than the default because it uses mvnz to get rid of
a branch.
This is all true for gcc 4.4.6... gcc 4.7 does not use my patterns at
all, which seems like a bug.
I need the paritysi2 as well; without it the compiler does not
generate code for paritydi2 properly.
Post merge, consider changing this to simple_return to enable shrink
wrapping. This may also involve epilogue unwind fixups though.
I have not enabled the simple_return pattern. On the tile ports,
the prologue defines a register not accounted for in the shrink
wrapping code (the PIC_TEXT_LABEL_REGNUM register). Is there a plan
to provide a target hook to support this? I did verify that shrink
wrapping work properly when I account for this register.
I also don't see support for AND addresses, as for lw_na. And yet you
seem to be using those addressing modes in
tilepro_expand_unaligned_load.
I can only assume these are failing validate_mem, and forcing the
address into a register first?
Yeah there is no AND addressing mode; the addresses are being put into
registers.
Why not use gp-relative references? A small matter of extending the
assembler with new relocations, perhaps.
We don't have that support in the tool chain currently. I can look
into it, but I haven't done it.
/* We represent all SI values as sign-extended DI values in
registers. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
((INPREC)= 32 || (OUTPREC) 32)
I think you should be *very* careful before you insist on this. Do
you not have a memory mode that ignores the high bits for 32-bit
pointers? From the description of memoryReadWord, it does seem like
you've got modes that pre-process input addresses.
Unfortunately all the address bits are read; we do not ignore the high
bits of 32-bit pointers.
MIPS uses this because, technically, the 32-bit operation insns
produce undefined results when given inputs that are not
sign-extended. I see no such restriction in the TileGx manual.
I think the issue is that we do not have 32-bit compares; we just
reuse the 64-bit ones. This requires that the inputs be sign
extended.
At least in 64-bit pointer mode, I think you should drop this and make
sure that you've got appropriate sign_extend patterns for all of the
x insns. Similar to how x86_64 does for the zero_extend patterns.
I've added the sign_extend patterns for the 32-bit insns.
Please let me know
[PING] New port resubmission for TILEPro and TILE-Gx
Ping? It's been a month. Seeing more feedback or status update.
Thanks,
Walter Lee
On 12/30/2011 7:30 PM, Walter Lee wrote:
I'm resubmitting the gcc ports to TILE-Gx and TILEPro as replies to
this email. The resubmission addresses the feedback made by Richard
Henderson in:
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01232.html, and
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01247.html
Feedback by Joseph Myers made in:
http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01385.html
http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01387.html
was addressed in a previous submission.
Here is a summary of the issues addressed:
Changes made to both ports:
- added vector patterns for suitable vector ops.
- cleaned up various move pattens, deleting dead alternatives,
deleting redundant immediate insn_and_split patterns, and delete
unnecessary movdi multi-word move pattern (tilepro only).
- added extra insv patterns.
- combined all the conditional moves into one pattern.
- combined *lh and *extendhisi2 pattern, and *lb and
*extendqihi2.
- partially remove the divsi stubs that were there to work around an
old gcc bug that has been partially fixed. Previously gcc would not
turn divide by constant into multiply by constant unless there is a
pattern for the divide of the given mode. It now seems to do
better, but we still need the stub on tilegx, else it turns 32-bit
divide by constant into 64-bit multiply by constant.
- wrap the GOT and TLS unspec addresses in const, and handle them with
a single pattern.
- add support for post_{inc,dec,modify} addressing modes.
- fixed invalid rtl sharing in alloca handling routines.
- use REG_CFA_* notes in prologue and epilogue.
- Use post-inc load in TARGET_ASM_TRAMPOLINE_TEMPLATE.
- converted the following to target hooks: LIBCALL_VALUE,
FUNCTION_VALUE_REGNO_P, GO_IF_LEGITIMATE_ADDRESS. Delete
GO_IF_MODE_DEPENDENT_ADDRESS and use the default.
- use the new atomics_ names and patterns.
Changes made to tilegx port:
- merged the AND patterns.
- add patterns that sign extends an SI result to DI for all the 32-bit
insns.
Here are replies to a few feedback items:
optabs.c will do exactly this if the pattern is not present. Similarly
for the DImode logicals (popcount, parity, etc).
I tried taking out the patterns for ctzdi2, clzdi2, ffsdi2, paritydi2,
and popcountdi2, and I found that the compiler generates libgcc
function calls for all of them except clzdi2. For clzdi2 the tilepro
pattern is better than the default because it uses mvnz to get rid of
a branch.
This is all true for gcc 4.4.6... gcc 4.7 does not use my patterns at
all, which seems like a bug.
I need the paritysi2 as well; without it the compiler does not
generate code for paritydi2 properly.
Post merge, consider changing this to simple_return to enable shrink
wrapping. This may also involve epilogue unwind fixups though.
I have not enabled the simple_return pattern. On the tile ports,
the prologue defines a register not accounted for in the shrink
wrapping code (the PIC_TEXT_LABEL_REGNUM register). Is there a plan
to provide a target hook to support this? I did verify that shrink
wrapping work properly when I account for this register.
I also don't see support for AND addresses, as for lw_na. And yet you
seem to be using those addressing modes in tilepro_expand_unaligned_load.
I can only assume these are failing validate_mem, and forcing the
address into a register first?
Yeah there is no AND addressing mode; the addresses are being put into
registers.
Why not use gp-relative references? A small matter of extending the
assembler with new relocations, perhaps.
We don't have that support in the tool chain currently. I can look
into it, but I haven't done it.
/* We represent all SI values as sign-extended DI values in
registers. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
((INPREC)= 32 || (OUTPREC) 32)
I think you should be *very* careful before you insist on this. Do
you not have a memory mode that ignores the high bits for 32-bit
pointers? From the description of memoryReadWord, it does seem like
you've got modes that pre-process input addresses.
Unfortunately all the address bits are read; we do not ignore the high
bits of 32-bit pointers.
MIPS uses this because, technically, the 32-bit operation insns
produce undefined results when given inputs that are not
sign-extended. I see no such restriction in the TileGx manual.
I think the issue is that we do not have 32-bit compares; we just
reuse the 64-bit ones. This requires that the inputs be sign
extended.
At least in 64-bit pointer mode, I think you should drop this and make
sure that you've got appropriate sign_extend patterns for all of the
x insns. Similar to how x86_64 does for the zero_extend patterns.
I've added the sign_extend patterns for the 32-bit insns.
Please let me know if there is anything I need to address.
Thanks,
Walter Lee
[PATCH] New port resubmission for TILEPro and TILE-Gx
I'm resubmitting the gcc ports to TILE-Gx and TILEPro as replies to
this email. The resubmission addresses the feedback made by Richard
Henderson in:
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01232.html, and
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01247.html
Feedback by Joseph Myers made in:
http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01385.html
http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01387.html
was addressed in a previous submission.
Here is a summary of the issues addressed:
Changes made to both ports:
- added vector patterns for suitable vector ops.
- cleaned up various move pattens, deleting dead alternatives,
deleting redundant immediate insn_and_split patterns, and delete
unnecessary movdi multi-word move pattern (tilepro only).
- added extra insv patterns.
- combined all the conditional moves into one pattern.
- combined *lh and *extendhisi2 pattern, and *lb and
*extendqihi2.
- partially remove the divsi stubs that were there to work around an
old gcc bug that has been partially fixed. Previously gcc would not
turn divide by constant into multiply by constant unless there is a
pattern for the divide of the given mode. It now seems to do
better, but we still need the stub on tilegx, else it turns 32-bit
divide by constant into 64-bit multiply by constant.
- wrap the GOT and TLS unspec addresses in const, and handle them with
a single pattern.
- add support for post_{inc,dec,modify} addressing modes.
- fixed invalid rtl sharing in alloca handling routines.
- use REG_CFA_* notes in prologue and epilogue.
- Use post-inc load in TARGET_ASM_TRAMPOLINE_TEMPLATE.
- converted the following to target hooks: LIBCALL_VALUE,
FUNCTION_VALUE_REGNO_P, GO_IF_LEGITIMATE_ADDRESS. Delete
GO_IF_MODE_DEPENDENT_ADDRESS and use the default.
- use the new atomics_ names and patterns.
Changes made to tilegx port:
- merged the AND patterns.
- add patterns that sign extends an SI result to DI for all the 32-bit
insns.
Here are replies to a few feedback items:
optabs.c will do exactly this if the pattern is not present. Similarly
for the DImode logicals (popcount, parity, etc).
I tried taking out the patterns for ctzdi2, clzdi2, ffsdi2, paritydi2,
and popcountdi2, and I found that the compiler generates libgcc
function calls for all of them except clzdi2. For clzdi2 the tilepro
pattern is better than the default because it uses mvnz to get rid of
a branch.
This is all true for gcc 4.4.6... gcc 4.7 does not use my patterns at
all, which seems like a bug.
I need the paritysi2 as well; without it the compiler does not
generate code for paritydi2 properly.
Post merge, consider changing this to simple_return to enable shrink
wrapping. This may also involve epilogue unwind fixups though.
I have not enabled the simple_return pattern. On the tile ports,
the prologue defines a register not accounted for in the shrink
wrapping code (the PIC_TEXT_LABEL_REGNUM register). Is there a plan
to provide a target hook to support this? I did verify that shrink
wrapping work properly when I account for this register.
I also don't see support for AND addresses, as for lw_na. And yet you
seem to be using those addressing modes in tilepro_expand_unaligned_load.
I can only assume these are failing validate_mem, and forcing the
address into a register first?
Yeah there is no AND addressing mode; the addresses are being put into
registers.
Why not use gp-relative references? A small matter of extending the
assembler with new relocations, perhaps.
We don't have that support in the tool chain currently. I can look
into it, but I haven't done it.
/* We represent all SI values as sign-extended DI values in
registers. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
((INPREC) = 32 || (OUTPREC) 32)
I think you should be *very* careful before you insist on this. Do
you not have a memory mode that ignores the high bits for 32-bit
pointers? From the description of memoryReadWord, it does seem like
you've got modes that pre-process input addresses.
Unfortunately all the address bits are read; we do not ignore the high
bits of 32-bit pointers.
MIPS uses this because, technically, the 32-bit operation insns
produce undefined results when given inputs that are not
sign-extended. I see no such restriction in the TileGx manual.
I think the issue is that we do not have 32-bit compares; we just
reuse the 64-bit ones. This requires that the inputs be sign
extended.
At least in 64-bit pointer mode, I think you should drop this and make
sure that you've got appropriate sign_extend patterns for all of the
x insns. Similar to how x86_64 does for the zero_extend patterns.
I've added the sign_extend patterns for the 32-bit insns.
Please let me know if there is anything I need to address.
Thanks,
Walter Lee
[PATCH] New port resubmission for TILEPro and TILE-Gx 2/6: changes in contrib
Here are the contrib changes. 2011-12-30 Walter Lee w...@tilera.com * config-list.mk (tilegx-linux-gnu): Add. (tilepro-linux-gnu): Add. * gcc_update (gcc/config/tilegx/mul-tables.c): New dependencies. (gcc/config/tilepro/mul-tables.c): New dependencies. diff -r -u -p -N /home/packages/gcc-4.7.0-182680/contrib/config-list.mk ./contrib/config-list.mk --- /home/packages/gcc-4.7.0-182680/contrib/config-list.mk 2011-12-08 13:43:41.0 -0500 +++ ./contrib/config-list.mk2011-12-29 22:06:40.921926000 -0500 @@ -60,7 +60,8 @@ LIST = alpha-linux-gnu alpha-freebsd6 al sparc-leon3-linux-gnuOPT-enable-target=all sparc-netbsdelf \ sparc64-sun-solaris2.10OPT-with-gnu-ldOPT-with-gnu-asOPT-enable-threads=posix \ sparc-wrs-vxworks sparc64-elf sparc64-rtems sparc64-linux sparc64-freebsd6 \ - sparc64-netbsd sparc64-openbsd spu-elf v850e-elf v850-elf vax-linux-gnu \ + sparc64-netbsd sparc64-openbsd spu-elf tilegx-linux-gnu tilepro-linux-gnu \ + v850e-elf v850-elf vax-linux-gnu \ vax-netbsdelf vax-openbsd x86_64-apple-darwin \ x86_64-pc-linux-gnuOPT-with-fpmath=avx \ x86_64-elfOPT-with-fpmath=sse x86_64-freebsd6 x86_64-netbsd \ diff -r -u -p -N /home/packages/gcc-4.7.0-182680/contrib/gcc_update ./contrib/gcc_update --- /home/packages/gcc-4.7.0-182680/contrib/gcc_update 2011-12-08 13:43:41.0 -0500 +++ ./contrib/gcc_update2011-12-29 22:06:40.934902000 -0500 @@ -88,6 +88,8 @@ gcc/config/c6x/c6x-mult.md: gcc/config/c gcc/config/m68k/m68k-tables.opt: gcc/config/m68k/m68k-devices.def gcc/config/m68k/m68k-isas.def gcc/config/m68k/m68k-microarchs.def gcc/config/m68k/genopt.sh gcc/config/mips/mips-tables.opt: gcc/config/mips/mips-cpus.def gcc/config/mips/genopt.sh gcc/config/rs6000/rs6000-tables.opt: gcc/config/rs6000/rs6000-cpus.def gcc/config/rs6000/genopt.sh +gcc/config/tilegx/mul-tables.c: gcc/config/tilepro/gen-mul-tables.cc +gcc/config/tilepro/mul-tables.c: gcc/config/tilepro/gen-mul-tables.cc # And then, language-specific files gcc/cp/cfns.h: gcc/cp/cfns.gperf gcc/java/keyword.h: gcc/java/keyword.gperf
New port resubmission for TILEPro and TILE-Gx 4/6: libcpp port
Here is the libcpp port. 2011-12-30 Walter Lee w...@tilera.com * configure.ac: Require 64-bit hwint for tilegx and tilepro. * configure: Regenerate. diff -r -u -p -N /home/packages/gcc-4.7.0-182680/libcpp/configure ./libcpp/configure --- /home/packages/gcc-4.7.0-182680/libcpp/configure2011-12-25 17:50:24.0 -0500 +++ ./libcpp/configure 2011-12-29 22:06:47.767943000 -0500 @@ -7382,7 +7382,8 @@ case $target in s390*-*-* | \ sparc*-*-* | \ spu-*-* | \ - sh[123456789lbe]*-*-* | sh-*-*) + sh[123456789lbe]*-*-* | sh-*-* | \ + tilegx-*-* | tilepro-*-* ) need_64bit_hwint=yes ;; *) need_64bit_hwint=no ;; diff -r -u -p -N /home/packages/gcc-4.7.0-182680/libcpp/configure.ac ./libcpp/configure.ac --- /home/packages/gcc-4.7.0-182680/libcpp/configure.ac 2011-12-08 13:45:51.0 -0500 +++ ./libcpp/configure.ac 2011-12-29 22:06:47.784911000 -0500 @@ -162,7 +162,8 @@ case $target in s390*-*-* | \ sparc*-*-* | \ spu-*-* | \ - sh[123456789lbe]*-*-* | sh-*-*) + sh[123456789lbe]*-*-* | sh-*-* | \ + tilegx-*-* | tilepro-*-* ) need_64bit_hwint=yes ;; *) need_64bit_hwint=no ;;
[PATCH] New port resubmission for TILEPro and TILE-Gx 5/6: libgcc port
Here is the libgcc port. 2011-12-30 Walter Lee w...@tilera.com * config.host: Handle tilegx and tilepro. * config/tilegx/sfp-machine.h: New file. * config/tilegx/sfp-machine32.h: New file. * config/tilegx/sfp-machine64.h: New file. * config/tilegx/t-crtstuff: New file. * config/tilegx/t-softfp: New file. * config/tilegx/t-tilegx: New file. * config/tilepro/atomic.c: New file. * config/tilepro/atomic.h: New file. * config/tilepro/linux-unwind.h: New file. * config/tilepro/sfp-machine.h: New file. * config/tilepro/softdivide.c: New file. * config/tilepro/softmpy.S: New file. * config/tilepro/t-crtstuff: New file. * config/tilepro/t-tilepro: New file. libgcc.diff.gz Description: GNU Zip compressed data
[PATCH] New port resubmission for TILEPro and TILE-Gx 6/6: libgomp port
Here is the libgomp port.
2011-12-30 Walter Lee w...@tilera.com
* configure.tgt: Handle tilegx and tilepro.
* config/linux/tile/futex.h: New file.
diff -r -u -p -N
/home/packages/gcc-4.7.0-182680/libgomp/config/linux/tile/futex.h
./libgomp/config/linux/tile/futex.h
--- /home/packages/gcc-4.7.0-182680/libgomp/config/linux/tile/futex.h
1969-12-31 19:00:00.0 -0500
+++ ./libgomp/config/linux/tile/futex.h 2011-12-29 22:06:53.524965000 -0500
@@ -0,0 +1,73 @@
+/* Copyright (C) 2011
+ Free Software Foundation, Inc.
+ Contributed by Walter Lee (w...@tilera.com)
+
+ This file is part of the GNU OpenMP Library (libgomp).
+
+ Libgomp is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ http://www.gnu.org/licenses/. */
+
+/* Provide target-specific access to the futex system call. */
+
+#include sys/syscall.h
+#include linux/futex.h
+
+static inline void
+sys_futex0 (int *addr, int op, int val)
+{
+ long _sys_result;
+ long _clobber_r2, _clobber_r3, _clobber_r4, _clobber_r5, _clobber_r10;
+ int err;
+
+ __asm__ __volatile__ (
+swint1
+: =R00 (_sys_result), =R01 (err), =R02 (_clobber_r2),
+ =R03 (_clobber_r3), =R04 (_clobber_r4), =R05 (_clobber_r5),
+ =R10 (_clobber_r10)
+: R10 (SYS_futex), R00 (addr), R01 (op), R02 (val),
+ R03 (0)
+: r6, r7,
+ r8, r9,r11, r12, r13, r14, r15,
+ r16, r17, r18, r19, r20, r21, r22, r23,
+ r24, r25, r26, r27, r28, r29, memory);
+}
+
+static inline void
+futex_wait (int *addr, int val)
+{
+ sys_futex0 (addr, FUTEX_WAIT, val);
+}
+
+static inline void
+futex_wake (int *addr, int count)
+{
+ sys_futex0 (addr, FUTEX_WAKE, count);
+}
+
+static inline void
+cpu_relax (void)
+{
+ __asm volatile ( : : : memory);
+}
+
+static inline void
+atomic_write_barrier (void)
+{
+ __sync_synchronize ();
+}
diff -r -u -p -N /home/packages/gcc-4.7.0-182680/libgomp/configure.tgt
./libgomp/configure.tgt
--- /home/packages/gcc-4.7.0-182680/libgomp/configure.tgt 2011-10-14
00:46:46.0 -0400
+++ ./libgomp/configure.tgt 2011-12-29 22:06:48.781929000 -0500
@@ -51,6 +51,10 @@ if test $enable_linux_futex = yes; then
config_path=linux/s390 linux posix
;;
+tile*-*-linux*)
+ config_path=linux/tile linux posix
+ ;;
+
# Note that bare i386 is not included here. We need cmpxchg.
i[456]86-*-linux*)
config_path=linux/x86 linux posix
Re: [PATCH] New port resubmission for TILEPro and TILE-Gx 1/6: toplevel changes
Here are the toplevel changes. 2011-12-30 Walter Lee w...@tilera.com * MAINTAINERS (tilegx port): Add self. (tilepro port): Add self. diff -r -u -p -N /home/packages/gcc-4.7.0-182680/MAINTAINERS ./MAINTAINERS --- /home/packages/gcc-4.7.0-182680/MAINTAINERS 2011-12-18 01:31:26.0 -0500 +++ ./MAINTAINERS 2011-12-29 22:06:38.548864000 -0500 @@ -104,6 +104,8 @@ sparc port Eric Botcazou ebotcazou@lib spu port Trevor Smigiel trevor_smig...@playstation.sony.com spu port David Edelsohn dje@gmail.com spu port Ulrich Weigand uweig...@de.ibm.com +tilegx portWalter Lee w...@tilera.com +tilepro port Walter Lee w...@tilera.com v850 port Nick Cliftonni...@redhat.com vax port Matt Thomas m...@3am-software.com x86-64 portJan Hubicka j...@suse.cz
Re: [PING2] New port for TILEPro and TILE-Gx
Seeking more feedback or status update. Thanks, Walter Lee On 10/30/2011 12:07 PM, Walter Lee wrote: Ping? I believe I have addressed all the reviewer's (namely Joseph Myers') comments to date. Thanks, Walter Lee
Re: [PING2] New port for TILEPro and TILE-Gx
On 11/7/2011 5:17 PM, Richard Henderson wrote: I haven't seen a re-post since Joseph's review? If I've missed it, please give me urls into the gcc-patches archive. contrib: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01881.html gcc: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01880.html http://gcc.gnu.org/ml/gcc-patches/2011-10/msg02084.html libgcc: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01882.html http://gcc.gnu.org/ml/gcc-patches/2011-10/msg02086.html Thanks, Walter Lee
[PING] New port for TILEPro and TILE-Gx
Ping? I believe I have addressed all the reviewer's (namely Joseph Myers') comments to date. Thanks, Walter Lee
Re: [PATCH] New port for TILEPro and TILE-Gx: 5/7 libgcc port
Here is a resubmission of the libgcc patch, removing the dependence on a header (arch/atomic.h) that's not installed by linux. Walter * config.host: Handle tilegx and tilepro. * config/tilegx/sfp-machine.h: New file. * config/tilegx/sfp-machine32.h: New file. * config/tilegx/sfp-machine64.h: New file. * config/tilegx/t-softfp: New file. * config/tilegx/t-tilegx: New file. * config/tilepro/atomic.c: New file. * config/tilepro/atomic.h: New file. * config/tilepro/sfp-machine.h: New file. * config/tilepro/softdivide.c: New file. * config/tilepro/softmpy.S: New file. * config/tilepro/t-tilepro: New file. libgcc.diff.gz Description: GNU Zip compressed data
Re: [PATCH] New port for TILEPro and TILE-Gx 2/7: changes in contrib
Here is a resubmission of the contrib patch, adding the entries to gcc_update to handle the multiply tables. * config-list.mk (tilegx-linux-gnu): Add. (tilepro-linux-gnu): Add. * gcc_update (gcc/config/tilegx/mul-tables.c): New dependencies. (gcc/config/tilepro/mul-tables.c): New dependencies. diff -r -u -p -N /home/packages/gcc-4.7.0-180241/contrib/config-list.mk ./contrib/config-list.mk --- /home/packages/gcc-4.7.0-180241/contrib/config-list.mk 2011-10-14 01:08:51.0 -0400 +++ ./contrib/config-list.mk2011-10-20 10:23:51.331484000 -0400 @@ -59,7 +59,8 @@ LIST = alpha-linux-gnu alpha-freebsd6 al sparc-leon3-linux-gnuOPT-enable-target=all sparc-netbsdelf \ sparc64-sun-solaris2.10OPT-with-gnu-ldOPT-with-gnu-asOPT-enable-threads=posix \ sparc-wrs-vxworks sparc64-elf sparc64-rtems sparc64-linux sparc64-freebsd6 \ - sparc64-netbsd sparc64-openbsd spu-elf v850e-elf v850-elf vax-linux-gnu \ + sparc64-netbsd sparc64-openbsd spu-elf tilegx-linux-gnu tilepro-linux-gnu \ + v850e-elf v850-elf vax-linux-gnu \ vax-netbsdelf vax-openbsd x86_64-apple-darwin \ x86_64-pc-linux-gnuOPT-with-fpmath=avx \ x86_64-elfOPT-with-fpmath=sse x86_64-freebsd6 x86_64-netbsd \ diff -r -u -p -N /home/packages/gcc-4.7.0-180241/contrib/gcc_update ./contrib/gcc_update --- /home/packages/gcc-4.7.0-180241/contrib/gcc_update 2011-10-14 01:08:51.0 -0400 +++ ./contrib/gcc_update2011-10-20 10:23:51.337478000 -0400 @@ -88,6 +88,8 @@ gcc/config/c6x/c6x-mult.md: gcc/config/c gcc/config/m68k/m68k-tables.opt: gcc/config/m68k/m68k-devices.def gcc/config/m68k/m68k-isas.def gcc/config/m68k/m68k-microarchs.def gcc/config/m68k/genopt.sh gcc/config/mips/mips-tables.opt: gcc/config/mips/mips-cpus.def gcc/config/mips/genopt.sh gcc/config/rs6000/rs6000-tables.opt: gcc/config/rs6000/rs6000-cpus.def gcc/config/rs6000/genopt.sh +gcc/config/tilegx/mul-tables.c: gcc/config/tilepro/gen-mul-tables.cc +gcc/config/tilepro/mul-tables.c: gcc/config/tilepro/gen-mul-tables.cc # And then, language-specific files gcc/cp/cfns.h: gcc/cp/cfns.gperf gcc/java/keyword.h: gcc/java/keyword.gperf
Re: [PATCH] New port for TILEPro and TILE-Gx: 5/7 libgcc port
Here is a resubmission of the libgcc patch, using soft-fp as the floating point library. I plan to do the benchmarking between the implementations as suggested, but I'd like to decouple that from the initial submission. * config.host: Handle tilegx and tilepro. * config/tilegx/sfp-machine.h: New file. * config/tilegx/sfp-machine32.h: New file. * config/tilegx/sfp-machine64.h: New file. * config/tilegx/t-softfp: New file. * config/tilegx/t-tilegx: New file. * config/tilepro/atomic.c: New file. * config/tilepro/sfp-machine.h: New file. * config/tilepro/softdivide.c: New file. * config/tilepro/softmpy.S: New file. * config/tilepro/t-tilepro: New file. libgcc.diff.gz Description: GNU Zip compressed data
[PATCH] New port for TILEPro and TILE-Gx 1/7: toplevel changes
Here are the toplevel changes. * MAINTAINERS (tilegx port): Add self. (tilepro port): Add self. diff -r -u -p -N /home/packages/gcc-4.7.0-179959/MAINTAINERS ./MAINTAINERS --- /home/packages/gcc-4.7.0-179959/MAINTAINERS 2011-10-14 01:12:54.0 -0400 +++ ./MAINTAINERS 2011-10-14 18:14:11.075846000 -0400 @@ -102,6 +102,8 @@ sparc port Eric Botcazou ebotcazou@lib spu port Trevor Smigiel trevor_smig...@playstation.sony.com spu port David Edelsohn dje@gmail.com spu port Ulrich Weigand uweig...@de.ibm.com +tilegx portWalter Lee w...@tilera.com +tilepro port Walter Lee w...@tilera.com v850 port Nick Cliftonni...@redhat.com vax port Matt Thomas m...@3am-software.com x86-64 portJan Hubicka j...@suse.cz
[PATCH] New port for TILEPro and TILE-Gx 2/7: changes in contrib
Here are the contrib changes. * config-list.mk (tilegx-linux-gnu): Add. (tilepro-linux-gnu): Add. diff -r -u -p -N /home/packages/gcc-4.7.0-179959/contrib/config-list.mk ./contrib/config-list.mk --- /home/packages/gcc-4.7.0-179959/contrib/config-list.mk 2011-10-14 01:08:51.0 -0400 +++ ./contrib/config-list.mk2011-10-14 18:14:11.064775000 -0400 @@ -59,7 +59,8 @@ LIST = alpha-linux-gnu alpha-freebsd6 al sparc-leon3-linux-gnuOPT-enable-target=all sparc-netbsdelf \ sparc64-sun-solaris2.10OPT-with-gnu-ldOPT-with-gnu-asOPT-enable-threads=posix \ sparc-wrs-vxworks sparc64-elf sparc64-rtems sparc64-linux sparc64-freebsd6 \ - sparc64-netbsd sparc64-openbsd spu-elf v850e-elf v850-elf vax-linux-gnu \ + sparc64-netbsd sparc64-openbsd spu-elf tilegx-linux-gnu tilepro-linux-gnu \ + v850e-elf v850-elf vax-linux-gnu \ vax-netbsdelf vax-openbsd x86_64-apple-darwin \ x86_64-pc-linux-gnuOPT-with-fpmath=avx \ x86_64-elfOPT-with-fpmath=sse x86_64-freebsd6 x86_64-netbsd \
[PATCH] New port for TILEPro and TILE-Gx 4/7: libcpp port
Here is the libcpp port. * configure.ac: Require 64-bit hwint for tilegx and tilepro. * configure: Regenerate. diff -r -u -p -N /home/packages/gcc-4.7.0-179959/libcpp/configure ./libcpp/configure --- /home/packages/gcc-4.7.0-179959/libcpp/configure2011-10-14 01:12:52.0 -0400 +++ ./libcpp/configure 2011-10-14 18:14:11.161721000 -0400 @@ -7320,7 +7320,8 @@ case $target in s390*-*-* | \ sparc*-*-* | \ spu-*-* | \ - sh[123456789lbe]*-*-* | sh-*-*) + sh[123456789lbe]*-*-* | sh-*-* | \ + tilegx-*-* | tilepro-*-* ) need_64bit_hwint=yes ;; *) need_64bit_hwint=no ;; diff -r -u -p -N /home/packages/gcc-4.7.0-179959/libcpp/configure.ac ./libcpp/configure.ac --- /home/packages/gcc-4.7.0-179959/libcpp/configure.ac 2011-10-14 01:12:52.0 -0400 +++ ./libcpp/configure.ac 2011-10-14 18:14:11.141771000 -0400 @@ -158,7 +158,8 @@ case $target in s390*-*-* | \ sparc*-*-* | \ spu-*-* | \ - sh[123456789lbe]*-*-* | sh-*-*) + sh[123456789lbe]*-*-* | sh-*-* | \ + tilegx-*-* | tilepro-*-* ) need_64bit_hwint=yes ;; *) need_64bit_hwint=no ;;
[PATCH] New port for TILEPro and TILE-Gx: 5/7 libgcc port
Here is the libgcc port. * config.host: Handle tilegx and tilepro. * config/tilegx/t-tilegx: New file. * config/tilepro/atomic.c: New file. * config/tilepro/milieu.h: New file. * config/tilepro/softdivide.c: New file. * config/tilepro/softfloat.c: New file. * config/tilepro/softfloat.h: New file. * config/tilepro/softfloat_macros.h: New file. * config/tilepro/softfloat_specialize.h: New file. * config/tilepro/softmpy.S: New file. * config/tilepro/softtile.h: New file. * config/tilepro/t-tilepro: New file. libgcc.diff.gz Description: GNU Zip compressed data
[PATCH] New port for TILEPro and TILE-Gx: 6/7 libgomp port
Here is the libgomp port.
* configure.tgt: Handle tilegx and tilepro.
* config/linux/tile/futex.h: New file.
diff -r -u -p -N
/home/packages/gcc-4.7.0-179959/libgomp/config/linux/tile/futex.h
./libgomp/config/linux/tile/futex.h
--- /home/packages/gcc-4.7.0-179959/libgomp/config/linux/tile/futex.h
1969-12-31 19:00:00.0 -0500
+++ ./libgomp/config/linux/tile/futex.h 2011-10-14 18:14:11.65774 -0400
@@ -0,0 +1,73 @@
+/* Copyright (C) 2011
+ Free Software Foundation, Inc.
+ Contributed by Walter Lee (w...@tilera.com)
+
+ This file is part of the GNU OpenMP Library (libgomp).
+
+ Libgomp is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ http://www.gnu.org/licenses/. */
+
+/* Provide target-specific access to the futex system call. */
+
+#include sys/syscall.h
+#include linux/futex.h
+
+static inline void
+sys_futex0 (int *addr, int op, int val)
+{
+ long _sys_result;
+ long _clobber_r2, _clobber_r3, _clobber_r4, _clobber_r5, _clobber_r10;
+ int err;
+
+ __asm__ __volatile__ (
+swint1
+: =R00 (_sys_result), =R01 (err), =R02 (_clobber_r2),
+ =R03 (_clobber_r3), =R04 (_clobber_r4), =R05 (_clobber_r5),
+ =R10 (_clobber_r10)
+: R10 (SYS_futex), R00 (addr), R01 (op), R02 (val),
+ R03 (0)
+: r6, r7,
+ r8, r9,r11, r12, r13, r14, r15,
+ r16, r17, r18, r19, r20, r21, r22, r23,
+ r24, r25, r26, r27, r28, r29, memory);
+}
+
+static inline void
+futex_wait (int *addr, int val)
+{
+ sys_futex0 (addr, FUTEX_WAIT, val);
+}
+
+static inline void
+futex_wake (int *addr, int count)
+{
+ sys_futex0 (addr, FUTEX_WAKE, count);
+}
+
+static inline void
+cpu_relax (void)
+{
+ __asm volatile ( : : : memory);
+}
+
+static inline void
+atomic_write_barrier (void)
+{
+ __sync_synchronize ();
+}
diff -r -u -p -N /home/packages/gcc-4.7.0-179959/libgomp/configure.tgt
./libgomp/configure.tgt
--- /home/packages/gcc-4.7.0-179959/libgomp/configure.tgt 2011-10-14
00:46:46.0 -0400
+++ ./libgomp/configure.tgt 2011-10-14 18:14:11.167723000 -0400
@@ -51,6 +51,10 @@ if test $enable_linux_futex = yes; then
config_path=linux/s390 linux posix
;;
+tile*-*-linux*)
+ config_path=linux/tile linux posix
+ ;;
+
# Note that bare i386 is not included here. We need cmpxchg.
i[456]86-*-linux*)
config_path=linux/x86 linux posix
[PATCH] New port for TILEPro and TILE-Gx: 7/7 wwwdocs changes
Here are the wwwdocs changes, with the news date TBD. Index: backends.html === RCS file: /cvs/gcc/wwwdocs/htdocs/backends.html,v retrieving revision 1.41 diff -u -p -r1.41 backends.html --- backends.html 15 Jul 2011 09:48:14 - 1.41 +++ backends.html 15 Oct 2011 00:57:04 - @@ -98,6 +98,8 @@ sh | Q CB qr da sparc| Q CB qr pda spu | ? Q *C p g bd stormy16 | ???L FIC D l p m a +tilegx | S Q Cq p g bda e +tilepro | S F C p g bda e v850 | ??FI cp gm d s vax | M?I cp a e xtensa | ? C p bd Index: index.html === RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v retrieving revision 1.814 diff -u -p -r1.814 index.html --- index.html 12 Oct 2011 04:48:22 - 1.814 +++ index.html 15 Oct 2011 00:57:04 - @@ -53,6 +53,11 @@ mission statement/a./p dl class=news +dtspanTILE-Gx and TILEPro processor support/span +span class=date[2011-??-??]/span/dt +ddPorts for the TILE-Gx and TILEPro families of processors have been +contributed by Tilera./dd + dtspanOpenMP v3.1/span span class=date[2011-08-02]/span/dt ddAn implementation of the a Index: readings.html === RCS file: /cvs/gcc/wwwdocs/htdocs/readings.html,v retrieving revision 1.215 diff -u -p -r1.215 readings.html --- readings.html 15 Jul 2011 09:48:15 - 1.215 +++ readings.html 15 Oct 2011 00:57:04 - @@ -257,6 +257,16 @@ Intelreg;64 and IA-32 Architectures Sof br /Acronym stands for: Scalable Processor ARChitecture /li + litilegx + br /Manufacturer: Tilera + br /a href=http://www.tilera.com/scm/docs/index.html;Documentation/a + /li + + litilepro + br /Manufacturer: Tilera + br /a href=http://www.tilera.com/scm/docs/index.html;Documentation/a + /li + liv850 br /Manufacturer: NEC /li
