And my main question is it possible to rely on this fact when
compiling with gcc and different levels of optimizations?
No it is not , the compiler (especially trunk) is free to use LR as a
temporary after epilogue has been generated at higher optimization
levels.
Is it
possible to generate
On Mon, Jul 1, 2013 at 5:31 PM, Paulo Matos pma...@broadcom.com wrote:
Hi,
Near the start of schedule_block, find_modifiable_mems is called if
DONT_BREAK_DEPENDENCIES is not enabled for this scheduling pass. It seems on
c6x backend currently uses this.
However, it's quite strange that this
On Tue, Dec 10, 2013 at 9:44 PM, Maxim Kuvyrkov ma...@kugelworks.com wrote:
On 11/12/2013, at 5:17 am, Ramana Radhakrishnan ramana@googlemail.com
wrote:
On Mon, Jul 1, 2013 at 5:31 PM, Paulo Matos pma...@broadcom.com wrote:
Hi,
Near the start of schedule_block, find_modifiable_mems
On Wed, Dec 11, 2013 at 12:02 AM, Maxim Kuvyrkov ma...@kugelworks.com wrote:
On 11/12/2013, at 11:14 am, Ramana Radhakrishnan ramana@googlemail.com
wrote:
On Tue, Dec 10, 2013 at 9:44 PM, Maxim Kuvyrkov ma...@kugelworks.com wrote:
On 11/12/2013, at 5:17 am, Ramana Radhakrishnan ramana
On Mon, Dec 30, 2013 at 3:23 AM, Yangfei (Felix) felix.y...@huawei.com wrote:
Thanks for the reply. I found it in GCC-4.8.
The gcc version I look at is GCC-4.7. Seems this pattern is not there for
this version.
That will be because this was added in time for GCC 4.8. If you need
to find such
On 02/06/14 18:25, David Howells wrote:
Is it worth considering a move towards using C11 atomics and barriers and
compiler intrinsics inside the kernel? The compiler _ought_ to be able to do
these.
It sounds interesting to me, if we can make it work properly and
reliably. + gcc@gcc.gnu.org
On Wed, Feb 19, 2014 at 11:19 PM, Andrew Pinski pins...@gmail.com wrote:
On Wed, Feb 19, 2014 at 3:17 PM, Renato Golin renato.go...@linaro.org wrote:
On 19 February 2014 11:58, Richard Sandiford
rsand...@linux.vnet.ibm.com wrote:
I agree that having an unrecognised asm shouldn't be a hard
On Wed, Feb 19, 2014 at 11:26 PM, Renato Golin renato.go...@linaro.org wrote:
On 19 February 2014 23:19, Andrew Pinski pins...@gmail.com wrote:
With the unified assembly format, you should not need those
.arm/.thumb and in fact emitting them can make things even worse.
If only we could get
On Wed, May 14, 2014 at 5:38 PM, Richard Sandiford
rdsandif...@googlemail.com wrote:
Vladimir Makarov vmaka...@redhat.com writes:
On 2014-05-13, 6:27 AM, Kyrill Tkachov wrote:
Hi all,
In haifa-sched.c (in rank_for_schedule) I notice that live range
shrinkage is not performed when
On Thu, May 15, 2014 at 8:36 AM, Maxim Kuvyrkov
maxim.kuvyr...@linaro.org wrote:
On May 15, 2014, at 6:46 PM, Ramana Radhakrishnan ramana@googlemail.com
wrote:
I'm not claiming it's a great heuristic or anything. There's bound to
be room for improvement. But it was based on reality
On Mon, May 19, 2014 at 1:02 PM, Andrew Haley a...@redhat.com wrote:
On 05/16/2014 05:20 PM, Ian Bolton wrote:
On 05/16/2014 12:05 PM, Kugan wrote:
On 16/05/14 20:40, pins...@gmail.com wrote:
On May 16, 2014, at 3:23 AM, Kugan
kugan.vivekanandara...@linaro.org wrote:
I would like to
On 24/06/14 15:11, Vladimir Makarov wrote:
A few people asked me about new performance comparison of latest GCC
and LLVM. So I've finished it and put it on my site
http://vmakarov.fedorapeople.org/spec/
The comparison is achievable from 2014 link and links under it in
the left frame.
The ball-park number you have probably won't change much.
Unfortunately, that is the configuration I can use on my system because
of lack of libraries for other configurations.
Using --with-fpu={neon / neon-vfpv4} shouldn't cause you ABI issues with
libraries for any other configurations.
I wonder how much of that is due to auto-vectorization (on LLVM, -O2+
turns it on, I suppose GCC is only on -O3?). From Ramana's point,
there may be nothing serious if you haven't enabled NEON, though.
Auto-vec is turned off when you have -mfpu=vfpv3-d16 . That implies No Neon.
Ramana
On 01/07/14 20:58, John David Anglin wrote:
On 1-Jul-14, at 5:32 AM, Jonathan Wakely wrote:
On 1 July 2014 09:40, Matthias Klose wrote:
- HPPA (build log [2]), is missing all the future_base symbols and
exception_ptr13exception symbols, current_exception and
rethrow_exception.
This
On 01/07/14 09:40, Matthias Klose wrote:
on some linux architectures there are some symbols missing in libstdc++.so.6
built from the 4.9 branch. I didn't notice before due to a packaging bug.
affected are ARM32, HPPA, SPARC.
- ARM32 (build log [1], both soft and hard float) are missing
On 22/07/14 14:14, Kyrill Tkachov wrote:
Hi all,
In the arm backend we've got this TARGET_UNIFIED_ASM macro that is
currently on for TARGET_THUMB2 with a comment that says:
/* We could use unified syntax for arm mode, but for now we just use it
for Thumb-2. */
I've been doing some work
On 04/08/14 23:34, Evandro Menezes wrote:
I noticed that when -mgeneral-regs-only FP registers are still used by the
LRA for spilling. Though in rare cases I saw an ICE because of it, even
when it works it seems to me that the compiler should follow the desires of
its user.
If you've
On Tue, Nov 11, 2014 at 3:16 PM, Joel Sherrill
joel.sherr...@oarcorp.com wrote:
Fix is committed to trunk at
https://gcc.gnu.org/viewcvs/gcc?view=revisionrevision=217341.
BR,
Terry
That got past libgcc2 but now it fails building newlib for arm-eabi.
This is just a build of gcc with newlib
place that the object pointed to also
should also have the same type qualifiers as the pointer being used to
access this.
Thanks in advance
Ramana
--
Ramana Radhakrishnan
Hi Richard,
On 7/10/07, Richard Guenther [EMAIL PROTECTED] wrote:
On 7/10/07, Ramana Radhakrishnan [EMAIL PROTECTED] wrote:
Hi,
While upgrading a port of mine to trunk for a testcase I noticed the
following . Its more of a question for a language lawyer I guess.
The test looks like
Hi,
Based on this morning's announcement by David at the Steering commitee
panel .
Here's the link to the slides online for folks to look at .
http://www.cse.iitb.ac.in/~uday/gcc-workshop/?file=downloads
--
cheers
Ramana
--
Ramana Radhakrishnan
Besides, what happens if I move the insertion of instrumentation
before register allocation, or even before the 1st scheduling pass,
can I identify load/store instructions that early?
--
Ramana Radhakrishnan
, but those are all fixed in 4.4 and so
forth.
Previous Report
===
http://gcc.gnu.org/ml/gcc/2007-08/msg00181.html
--
Mark Mitchell
CodeSourcery
[EMAIL PROTECTED]
(650) 331-3385 x713
--
Ramana Radhakrishnan
backend.
HTH
cheers
Ramana
--
Ramana Radhakrishnan
suggestion is greatly appreciated.
Bingfeng Mei
Broadcom UK
--
Ramana Radhakrishnan
GNU Tools
Celunite Inc.
and other
information so that people can help understand where the problem is .
Please read http://gcc.gnu.org/bugs.html about how to report a bug.
cheers
Ramana
Thanks very much.
huamama
--
Ramana Radhakrishnan
all the information as specified here .
http://gcc.gnu.org/bugs.html#detailed
Thanks
Ramana
The host platform is cygwin (1.5.24).
I build the toolchains use buildroot.
Thanks.
On Nov 13, 2007 5:02 PM, Ramana Radhakrishnan [EMAIL PROTECTED] wrote:
Hi,
On Nov 13, 2007 2:29 PM, 马骅
--thanks, Praveen
--
Ramana Radhakrishnan
the optimization
level
to -Os and -O3.
I will be away on vacation from December 3-8th, and not reading mail during
that time.
--
Michael Meissner, AMD
90 Central Street, MS 83-29, Boxborough, MA, 01719, USA
[EMAIL PROTECTED]
--
Ramana Radhakrishnan
GNU Tools
Celunite Inc.
(cold) and attribute(hot) will set the optimization
level
to -Os and -O3.
I will be away on vacation from December 3-8th, and not reading mail during
that time.
--
Michael Meissner, AMD
90 Central Street, MS 83-29, Boxborough, MA, 01719, USA
[EMAIL PROTECTED]
--
Ramana Radhakrishnan
of the proposal for the inline cloner.
cheers
Ramana
cheers
Ramana
Karthik
--
Ramana Radhakrishnan
GNU Tools
Celunite Inc.
without
the prerequisite move, add, and control flow insns in the .md.
brgds, H-P
--
Ramana Radhakrishnan
and Computer Engineering,
North Carolina State University.
-Original Message-
From: Ramana Radhakrishnan [mailto:[EMAIL PROTECTED]
Sent: Tuesday, January 01, 2008 12:47 AM
To: Balaji V. Iyer
Cc: [EMAIL PROTECTED]
Subject: Re: GNU Assembler Start of Function basic block
Hi,
On Jan 1
On 16 August 2011 16:24, Richard Sandiford richard.sandif...@linaro.org wrote:
Ramana Radhakrishnan ramana.radhakrish...@linaro.org writes:
I can't see how it is right to construct essentially 2 chains for the
same register that have overlapping live ranges without an intervening
conditional
I appreciate any advise of how to resolve this -- should I add
(*fun) (XEXP (dest, 0), data); ?
Actually I don't see why not - a zero_extract on the LHS of an
expression is supposed to be a bit field insert on that register.
Isn't there an implicit read of the destination register involved in
surprises performance wise.
cheers
Ramana
---
Ramana Radhakrishnan
PDSW Tools
ARM Ltd.
On Mon, Jan 30, 2012 at 6:56 AM, Jon Masters jonat...@jonmasters.org wrote:
The __sync_synchronize legacy sync function is intended to be used to
perform an expensive data memory barrier operation. It is defined within
libgcc in such a way that I *believe* means that, on most architectures,
it
Hi,
A colleague noticed that we were not vectorizing loops that had end of
loop computations that were MIN type operations that weren't expressed
in the form of a typical min operation. A transform from (i x )
( i y) to ( i min (x, y)) is only something that we should do in
these situations
Sorry about the delayed response, I've been away for some time.
I don't exactly understand why the general transform is not advisable.
We already synthesize min/max operations.
Can you elaborate on why you think that better code might be generated
when not doing this transform?
The
On Fri, Apr 27, 2012 at 9:24 PM, David Sehr s...@google.com wrote:
Hello All,
We are using gcc trunk as of 4/27/12, and are attempting to add
support to the ARM gcc compiler for Native Client.
We are trying to get gcc -march=armv7-a to use movw/movt consistently
instead of minipools. The
found where it is
described, maybe I searched in wrong place.
Thanks all you
--
Ramana Radhakrishnan
not clear where one could do this and how to
improve this particular case of code generation. Any suggestions would
be most helpful.
cheers
Ramana
--
Ramana Radhakrishnan
Hi Andrew,
On Mon, Apr 7, 2008 at 4:41 PM, Andrew Pinski [EMAIL PROTECTED] wrote:
On Mon, Apr 7, 2008 at 3:31 AM, Ramana Radhakrishnan [EMAIL PROTECTED]
wrote:
The basic case is as explained below.
for (i = 0; i 100; i ++)
{
if ()
{
a[i] = something
Hi Andrew,
I've been looking at doing this possibly in the store sinking pass and
have the following query as below.
On Mon, Apr 7, 2008 at 9:11 PM, Andrew Pinski [EMAIL PROTECTED] wrote:
On Mon, Apr 7, 2008 at 3:31 AM, Ramana Radhakrishnan [EMAIL PROTECTED]
wrote:
The basic case
to be faster on modern workstation
cpus.
--
Ramana Radhakrishnan
is will GCC allocate callee save
registers for function even if the function doesn't call any other
function?
Or is this a gcc bug?
Hope my question is clear.
Regards,
Shafi
--
Ramana Radhakrishnan
?
Or is this a gcc bug?
Hope my question is clear.
Regards,
Shafi
--
Ramana Radhakrishnan
--
Ramana Radhakrishnan
to see the mt backend for some example as to how to
do it . It looks similar to how we do it in ours.
cheers
Ramana
Ramana Radhakrishnan
Icera Semiconductor
On Wed, Jul 16, 2008 at 12:05 PM, Bingfeng Mei [EMAIL PROTECTED] wrote:
Hello,
I tried to use doloop_end pattern to reduce loop
scalar evolution
changes.
b) phi_nodes_info - Link list, whose each node contains a PHI node
and a count indicating the number of statements that replaced this
phi node as a result of scalar evolution analysis.
--
Ramana Radhakrishnan
performed
(e.g., loop reversal), the final value of the ssa name might have
changed.
Could you give an example for this ? Is there anything else you might
suggest in terms of undoing the transformations from scalar cprop.?
cheers
Ramana
Zdenek
--
Ramana Radhakrishnan
is good enough for the time being.
Zdenek
--
Ramana Radhakrishnan
change then
clearly the hash values at the time of storing and restoring would be
different . So if the assignment to D.10_1 has changed in some form,
the hashvalues would be different.
Zdenek
--
Ramana Radhakrishnan
+= SSA_NAME_VERSION (op0);
val += gen_hash (SSA_NAME_DEF_STMT (op0));
}
cheers
Ramana
Zdenek
--
Ramana Radhakrishnan
--
Ramana Radhakrishnan
,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
--
Ramana Radhakrishnan
Hi Jeffrey,
I'm seeing a few performance regressions similar to
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32306 and
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=33315 in a port where I'm
working off the 4.3 branch. These regressions are caused by the
decision to stop iterating DOM on identifying
: in find_reloads, at reload.c:3672
Please submit a full bug report,
with preprocessed source if appropriate.
See URL:http://gcc.gnu.org/bugs.html for instructions.
--
Ramana Radhakrishnan
GNU Tools
codito ergo sum (http://www.codito.com)
On Thu, 2006-04-13 at 22:37 +0530, Ramana Radhakrishnan wrote:
Right : A way to work around this would be to hold to not match this
instruction until reload has been completed and have a define_split to
convert this to a cmp , bne when its a memory operand matching . Look at
rs6000.md
TARGET_ADDRESS_COST to return 0 always as
well as specifically for POST_INC, POST_DEC and friends , but this did not help
.
Any suggestions would be great ! Thanks for your time .
cheers
Ramana
---
Ramana Radhakrishnan
GNU Tools
Celunite Inc
memcpyreduced.i
Description: Binary data
Hi Zdenek,
I can't seem to reproduce this on 4.1.x with any other port. Maybe I need a sync
up with the latest svn of 4.1.x . I'll try looking at 4.2 head also to spot
differences if any.
Thanks for your time
cheers
Ramana
Ramana Radhakrishnan
GNU Tools
Celunite Inc
On Wed Jul 19 8:09
On Wed, 2009-12-23 at 16:00 +0100, Paolo Bonzini wrote:
On 12/23/2009 03:27 PM, Bingfeng Mei wrote:
Do you mean if TARGET_ADDRES_COST (non-x86) is defined properly,
this should be fixed? Or it requires extra patch?
No, if TARGET_ADDRESS_COST was fixed for x86 (and of course defined
module Utils
It sounds like a configuration issue but given my rather rusty ocaml
skills - I'm not sure where to look. Googling around doesn't show me
anything obvious. I see this both with v. 3.09.3 and v 3.11 (on
karmic).
Any help would be appreciated.
Cheers,
Ramana
--
Ramana Radhakrishnan
Ramana
--
Ramana Radhakrishnan
GNU Tools
ARM Ltd.
On Sat, 2010-01-16 at 16:23 +0100, Jakub Jelinek wrote:
The branch is now frozen and all checkins until after the final release
of GCC 4.4.3 require explicit RM approval.
I would like to backport this patch http://gcc.gnu.org/PR38697
from mainline into the 4.3 and 4.4 branches, so that some
42509, arm-gnueabi doesn't bootstrap but is a primary target
I haven't had the time in the past few weeks to work on this
effectively. I'll be able to find some time to work on this during this
week and will get back on this.
cheers
Ramana
Hi Kenneth,
The documentation of auto-inc-dec still refers to flow and when I
raised this on IRC folks suggested that you might have some
documentation fixes if any, in this area.
http://gcc.gnu.org/onlinedocs/gccint/Incdec.html#Incdec
The lines in the doco are as below :
These embedded side
On Wed, 2010-06-16 at 15:52 +, Siarhei Siamashka wrote:
Hello,
Currently gcc (at least version 4.5.0) does a very poor job generating single
precision floating point code for ARM Cortex-A8.
The source of this problem is the use of VFP instructions which are run on a
slow
a char or a short.
~ramana
Mircea
--
Ramana Radhakrishnan
cse do in this area,
but at the tree level. It's something I've always wanted to see
implemented, but never bothered to do...
jeff
--
Ramana Radhakrishnan
and mpfr to automatically get
statically linked into the compiler.
I know that there are many ways to handle this but the point is that
it should work easily and conveniently without extra work.
Ian
--
Ramana Radhakrishnan
with using
gcc.
cheers
Ramana
--
Ramana Radhakrishnan
GNU Tools
codito ergo sum (www.codito.com)
Errr, you need to change the assembler to do this . GCC does not care
about what sits inside __asm__ .
cheers
Ramana
On Fri, 2005-12-16 at 09:18 -0500, Burt Walsh wrote:
I am using SimpleScalar (ARM ISA) to do some simulations. I have
added an
instruction to the SimpleScalar machine
Hi Mark,
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39076 appears to be an
reappearance of the failure reported originally at
http://gcc.gnu.org/ml/gcc-patches/2008-04/msg01577.html . and detailed
discussion in the thread that ends at
http://gcc.gnu.org/ml/gcc-patches/2008-06/msg00907.html .
Is
-tree-dominator-opts -fno-gcse
I'm not sure about the best way to fix this but I've filed this for
the moment as
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39468
cheers
Ramana
---
Ramana Radhakrishnan
ARM Ltd.
[Resent because of account funnies. Apologies to those who get this twice]
Hi,
This problem is reported every once in a while, all targets with
small
load-immediate instructions suffer from this, especially since GCC
4.0
(i.e. since tree-ssa). But it seems there is just not enough
To aid testing, I'd like people to help bootstrapping bootstrappable
targets -- arm, alpha, ia64, pa, s390, x86_64.
I'm bootstrapping the branch on an arm-linux-gnueabi target.
Ramana
On Tue, Apr 7, 2009 at 11:03 AM, Ramana Radhakrishnan
raman...@gmail.com wrote:
To aid testing, I'd like people to help bootstrapping bootstrappable
targets -- arm, alpha, ia64, pa, s390, x86_64.
I'm bootstrapping the branch on an arm-linux-gnueabi target.
bootstrap on arm-linux-gnueabi
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
Ramana Radhakrishnan
Sent: 08 April 2009 23:30
To: Paolo Bonzini
Cc: GCC Development; Ian Lance Taylor; Andreas Krebbel; Uros Bizjak
Subject: Re: [cond-optab] svn branch created, looking
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
Nitin Garg
Sent: 01 May 2009 14:11
To: gcc@gcc.gnu.org; gcc-h...@gcc.gnu.org
Subject: Problem with gcc-4.4.0 with Cortex-m3 and cortex-a9 cpu
I am working on Cortex-A9 and M3 of ARM. I am
On Wed, May 6, 2009 at 4:10 PM, Mark Mitchell m...@codesourcery.com wrote:
Richard Earnshaw wrote:
The slush that I requested last week has been lifted. However, I have
asked for relative calm until the cond-optab branch has been merged to
mainline, which will hopefully occur on Friday,
-Original Message-
From: Michael Matz [mailto:m...@suse.de]
Sent: 06 May 2009 18:00
To: Richard Earnshaw
Cc: Paolo Bonzini; Joern Rennecke; Ramana Radhakrishnan;
m...@codesourcery.com; gcc@gcc.gnu.org
Subject: Re: Setting ARM PIC register (Was: RE: GCC 4.5.0 Status Report
(2009
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
Samuel Tardieu
Sent: 06 May 2009 11:06
To: gcc@gcc.gnu.org
Subject: Multilib for ARM in thumb2 mode
Right now, to be able to compile a mutilib-enabled ARM-targeted
compiler
supporting
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
Paolo Bonzini
Sent: 07 May 2009 14:53
To: m...@codesourcery.com
Cc: gcc@gcc.gnu.org; Ramana Radhakrishnan; Richard Earnshaw
Subject: cond-optab merge delay? [was Re: GCC 4.5.0 Status Report
On Fri, Jun 5, 2009 at 11:11 PM, Graham Reitzgrahamre...@gmail.com wrote:
Is there a machine description template in the gcc file source tree?
There is no template as such but you could look at existing ports for
the basic templates. Google should give you results for previous
questions on this
On Fri, Aug 7, 2009 at 1:33 PM, Florent Defayspira.inhabit...@gmail.com wrote:
Hi,
I am working on a new port.
The target machine supports post-increment and pre-decrement
addressing modes. These modes are twice faster than indexed mode.
It is important for us that GCC consider them well.
for the answers.
cheers
Ramana
Attachments
1. Patch to turn on predicable attributes on all the ARM call patterns.
2. Dumps of the testcase that are relevant, test.c.*.peephole2,
test.c.*.dse2, test.c.*.ce3. (dumps.tar.bz2)
3. Testcase test.c
--
Ramana Radhakrishnan
GNU Tools
ARM Ltd
On Mon, 2009-08-10 at 15:09 +0200, Steven Bosscher wrote:
On Mon, Aug 10, 2009 at 1:16 PM, Ramana
Radhakrishnanramana.radhakrish...@arm.com wrote:
I wonder if the best way to fix this is to teach ifcvt.c to handle
conditional returns.
Yes. This is a bug in the middle-end. I can only
On Wed, Aug 19, 2009 at 1:27 PM, Diego Novillodnovi...@google.com wrote:
I haven't been able to connect to #gcc today. Is anyone else having
trouble connecting?
Wonder if it is something else . I've been connected pretty much all
day and things seem to be working.
Ramana
Diego.
GCC bootstrap :
Total number of zero-extension instructions before : 1456
Total number of zero-extension instructions after : 5814
No impact on boot-strap time.
You sure you have these numbers the right way around ? Shouldn't the
number of zero-extension instructions after the patch
On Wed, 2010-12-08 at 14:42 +0100, Richard Guenther wrote:
A release candidate for GCC 4.5.2 is available from
ftp://gcc.gnu.org/pub/gcc/snapshots/4.5.2-RC-20101208
and shortly its mirrors. It has been generated from SVN revision 167585.
I have so far bootstrapped and tested the
Index: config/arm/thumb2.md
===
--- config/arm/thumb2.md (revision 168424)
+++ config/arm/thumb2.md (working copy)
+ ??? The possible introduction of a new block to initialize the
+ new IV can potentially
Hi Michael,
Thanks for running these. I spent some time this morning looking
through the results, they largely look ok though I don't have much
perspective on the
the objc/ obj-c++ failures.
These failures here
For v7-a , A9 and Neon - these failures below:
Running target unix
FAIL:
On Thu, Jan 15, 2015 at 4:11 AM, Andrew Pinski pins...@gmail.com wrote:
Hi,
I have some code where we generate some weird code that has stores
followed by a load from the same location.
For an example we get:
add x14, sp, 240
add x15, sp, 232
str x14, [sp, 136]
mov w2, w27
ldr w1, [sp,
On Thu, Feb 19, 2015 at 9:17 AM, Marat Zakirov m.zaki...@samsung.com wrote:
Hi all!
During my investigation I found that GCC does not performs load/store
widening (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65088). Could you
please answer is it so? And is there any plans to make it? I also
;; Crude Advanced SIMD approximation.
(define_insn_reservation cortex_53_advsimd 4
(and (eq_attr tune cortexa53)
(eq_attr:q is_neon_type yes))
cortex_a53_simd0)
Does it mean that all AdvSIMD instructions
On Thu, Feb 12, 2015 at 3:18 PM, Ulrich Weigand uweig...@de.ibm.com wrote:
Hello,
we're running into a problem related to use of initial-exec access to
TLS variables in dynamically-loaded libraries. Now, in general, this
is actually not supported. However, there seems to an inofficial
On 29/04/2015 09:24, Christian Bruel wrote:
Hi Ramana, Richard
After playing with the attritute ((target ([thumb,arm])), during the
pending review, I added the default selector to neutralize
-mflip-thumb for the setjmp/longjmp based tests.
I was wondering it there would be an interest
On 20/05/15 14:37, David Howells wrote:
Paul E. McKenney paul...@linux.vnet.ibm.com wrote:
I was thinking of y as a simple variable, but if it is something more
complex, then the compiler could do this, right?
char *x;
y;
x = z;
Yeah. I presume it has to maintain
On 20/05/15 15:03, Paul E. McKenney wrote:
On Wed, May 20, 2015 at 02:44:30PM +0100, Ramana Radhakrishnan wrote:
On 20/05/15 14:37, David Howells wrote:
Paul E. McKenney paul...@linux.vnet.ibm.com wrote:
I was thinking of y as a simple variable, but if it is something more
complex
1 - 100 of 1493 matches
Mail list logo
