On Fri, Sep 2, 2011 at 9:18 AM, Stephen Ecob
wrote:
> On Fri, Sep 2, 2011 at 10:54 PM, Tom Pope wrote:
>> Why not make one? Seeedstudio's PCB manufacturing service will give
>> you (10x)100cm^2 boards for ~$25.
>> http://www.seeedstudio.com/depot/fusion-pcb-service-p-835.html?cPath=185
>
> I've d
Hi folks!
Do any of you know of a through-hole perfboard or protoboard that has
a 50 mil pitch?
I have a 128 pin through-hole connector arranged as 2 rows of 64 pins,
spaced on a 0.05" pitch. (The two rows are space 0.25" apart.) I
could solder wires onto each of these pins and attach them to a
I don't know if this will help or not, but here goes...
I've never used net highlighting in PCB before, but I had a similar
problem in an ASIC designed using Cadence's Virtuoso layout editor. I
ultimately tracked it down using the "highlight trace" feature of the
program, which included the nifty
On Mon, May 30, 2011 at 1:39 PM, DJ Delorie wrote:
>
>> git remote update origin would be the easiest way.
>
How about
$ git remote show origin
--wpd
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/ged
On Fri, May 27, 2011 at 12:33 PM, DJ Delorie wrote:
>
> How hard is it to install Ruby on Windows, or Mac, and use it from our
> ports of gEDA and PCB ?
>
> I think "readily available on all platforms" is just as important as
> "many people know how to use it" and "it meets our technical needs".
>
On Fri, May 27, 2011 at 11:54 AM, DJ Delorie wrote:
>
> This is more anecdotal than anything else...
>
>> > I'm a Perl fan myself.
>>
>> (shudder)
>
Oh goody! flame war bate!
I stopped liking perl when I learned why this script didn't do what I
expected it to do:
#!/usr/bin/perl -w
my @array =
ving me more to
chew on. The GA144 sounds quite interesting for a very specific
application that may be coming down the pike pretty soon, but I don't
have any good killer app ideas for it.
--wpd
On Tue, Apr 5, 2011 at 9:47 AM, rickman wrote:
> On 3/26/2011 8:50 PM, Patrick Doyle wrote:
&g
Hi Folks,
I'm looking for a US distributor for a Balloon Board
(http://www.balloonboard.org/) or it's equivalent -- perhaps one of
you may have designed and sell your own equivalent. Basically, I'm
looking for a standalone board with a processor (with it's associated
flash & SDRAM) and an FPGA. I
On Fri, Jan 14, 2011 at 8:59 PM, al davis wrote:
>> >> However we will also explore the possibility of publishing
>> >> the files for one of the Open ECAD packages such as gEDA.
>>
>> How would the conversion be performed?
>
> That's obvious. They are waiting for us to provide a conversion
> util
Hello Florian,
I wish I could say that I could help, but instead I'd like to say "I
too am interested in learning what's involved in using gEDA for chip
design."
I'm not even sure where to begin, other than to share the few things
I've thought about so far (however naive or clueless those thoughts
I just noticed on the gEDA Launchpad page
(https://code.launchpad.net/geda) that it says:
You can browse the source code for the development focus branch or get
a copy of the branch using the command:
bzr branch lp:geda
Shouldn't that be
git clone git://git.gpleda.org/gaf.git
--wpd
__
Apologies if this is a FAQ... I didn't see anything recent in my mail
archives...
Has anybody done any work to translate between gEDA file formats and
Open Access?
At a minimum, it would be awfully nice to be able to point a script at
an OA library and pop out a bunch of .sch files that could be
On Sat, Dec 18, 2010 at 4:39 PM, Patrick Doyle wrote:
> Hi Folks!
>
> How much work would be involved in extending the extended data types
> in Icarus (http://www.geda.seul.org/wiki/geda:icarus_extensions) to
> support a bus of wire reals, e.g.
>
> wire real [9:0] rea
Hi Folks!
How much work would be involved in extending the extended data types
in Icarus (http://www.geda.seul.org/wiki/geda:icarus_extensions) to
support a bus of wire reals, e.g.
wire real [9:0] realbus;
wire real x = realbus[0];
wire real y = realbus[1];
etc...
I can poke around and see what
On Fri, Nov 19, 2010 at 1:23 PM, Peter Clifton wrote:
> On Fri, 2010-11-19 at 17:43 +, Peter Clifton wrote:
>> On Fri, 2010-11-19 at 06:15 -0500, Patrick Doyle wrote:
>> > Not knowing anything of which I speak (write?), would COLLADA
>> > (https://collada.org/m
On Thu, Nov 18, 2010 at 10:01 PM, kai-martin knaak wrote:
>
> Looks like there is no open 3D exchange format that fits the
> need of pcb:
>
> a) render a beautiful image of a populated board
>
> b) integrate pcb in a 3D work-flow to fit the board into some
> tight space.
>
> The existing formats a
On Wed, Aug 4, 2010 at 2:02 PM, Stephen Williams wrote:
>
> This looks like a bug in Icarus Verilog, I'm afraid. Since all the
> values in your expression have explicit sizes, the bit width need
> not have carry space tacked on and the width should be 26bits.
> In fact, in your example the bus is
On Wed, Aug 4, 2010 at 11:46 AM, Larry Doolittle
wrote:
> On Wed, Aug 04, 2010 at 10:58:51AM -0400, Patrick Doyle wrote:
>> Can anybody tell me if the following is an Icarus feature or a Verilog
>> feature.
>
> Verilog. Probably.
>
>> reg [5:0] offset;
>>
Can anybody tell me if the following is an Icarus feature or a Verilog
feature. I would expect the two $display statements to show the same
results. For some reason, the first one expands the result to 27 bits
instead of the 26 bits I would have expected. The only difference
(hopefully) between
On Tue, Aug 3, 2010 at 12:59 PM, Stephen Williams wrote:
>
> I'm a little surprised that Icarus Verilog doesn't already pay
> attention to the "4" in your "%4b". In any case, this should do
> the trick for you:
>
> integer result;
> ... $display("%b", result[3:0]); ...
>
Oh, of course
B
On Tue, Aug 3, 2010 at 12:33 PM, Larry Doolittle
wrote:
> On Tue, Aug 03, 2010 at 09:12:00AM -0400, Patrick Doyle wrote:
>> I have some verilog test code in which I would like to display an
>> integer value, which is known to be between 0 and 15, as a binary
>> vector, i.e.
Sorry to pester you folks with this, but I'm not sure whom else to ask.
I have some verilog test code in which I would like to display an
integer value, which is known to be between 0 and 15, as a binary
vector, i.e.
integer result;
$display("%4b", result);
of course I get a 64 bit vector displa
On Fri, Jul 9, 2010 at 3:55 PM, Stephen Williams wrote:
> I instead recommend either installing with a unique prefix, or
> install with a unique suffix.
ok, thanks.
--wpd
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/
On Fri, Jul 9, 2010 at 3:20 PM, Stephen Williams wrote:
> Patrick Doyle wrote:
>> If I want to compile and test a particular version of Icarus Verilog
>> without messing my existing working installation, what's the best way
>> to do that?
>>
>> I could c
If I want to compile and test a particular version of Icarus Verilog
without messing my existing working installation, what's the best way
to do that?
I could configure it with a prefix of some temp directory and add that
directory (/bin) to my path.
Or I could just run it in the compile director
When I run the following code in Icarus Verilog:
`define Tnom 140e-9
`define Rele 2e3
`define Cele 0.3e-6
`define Vdd1p8 1.7
`define DrvIstep 1e-6
`define ADCScale (1024/`Vdd1p8*`DrvIstep)
module check_this();
integer pulse_dur = 15;
integer delta3 = 1;
integer drvw1 = -20;
initial begin
$displ
For those of you who might be interested... I found the bug in my
verilog code that was triggering the crash. I had a spelling mistake
in one of my nets that resulted in a net being implicitly declared.
Personally, I don't think that this should trigger a crash of the
compiler (and perhaps it does
Hello, I am having a problem running a Verilog simulation using Icarus
verilog on my Mac. I have download and compiled the latest 0.9.1
snapshot as well as a few other snapshots. I fully expect that the
problem has to do with my verilog code, or, more likely, with my
development environment, but
Hello,
I am reviewing some Verilog code written by somebody else and run
through some other Verilog simulation tool, so I know this is a little
off topic, but I'm not sure where else to ask.
Anyway, I see code that looks like this:
reg [7:0] unit_matrix [12:0];
for (j = 0; j<8
When I try to target an FPGA with the 20081118 snapshot of Icarus
Verilog on a Windows platform, I get:
iverilog -tfpga -parch=virtex2 -o core_sm.edif broken.v
ERROR: Unable to read config file: c:\iverilog\lib\ivl\fpga.conf
error: failed to load.
: The specified module could no
Would somebody point me in the right direction for learning more about
synthesis with Icarus Verilog? I'm happy to read the source, but
synth.cc doesn't seem like the right place to start.
Specifically, I am curious to learn if anybody has used Icarus Verilog
to target a custom ASI
On Tue, Mar 3, 2009 at 6:03 PM, Stephen Williams <[1]st...@icarus.com>
wrote:
Larry Doolittle wrote:
> Patrick -
>
> On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote:
>> Should I have been able to find that somewhere else? (I am
>
here to look for
answers such as these so I don't have to pester the mailing list" and
not in a whiny tone of voice of "where's the docs?")
On Tue, Mar 03, 2009 at 11:39:28AM -0500, Patrick Doyle wrote:
>I have an Icarus Verilog question (which m
Hello gEDA-ites... it's been a while since I've hung out on this list,
but I'm glad to see you're all still alive and kicking :-)
I have an Icarus Verilog question (which may, perhaps be a more
general Verilog question). I would like to write a test bench that
exits with a non-zero
On 9/4/07, Stuart Brorson <[EMAIL PROTECTED]> wrote:
> Ummm, the gathering is on the 6th. I made a mistake and put a wrong
> date in the subject the last time. :-(
>
Either way, it's not the 5th, the one day I could actually join you
this week. :-(
Sigh... yet another month goes by
--wpd
On 7/11/07, Levente <[EMAIL PROTECTED]> wrote:
> Hi all,
>
>
> I have a few question about git.
>
> 1. Does git handles symbolic links?
I just did a quick check, and 1.5.2.2 (which is what I'm using)
certainly appears to handle symbolic links.
> 2. Does git handles file modes?
>
yes
> I am asking
On 5/22/07, Ales Hvezda <[EMAIL PROTECTED]> wrote:
>
> Hi,
>
> I am seeing some weirdness with the geda lists, so this is just
> a test, please ignore. Thanks.
>
> -Ales
Oops, I accidentally didn't ignore it.
Sorry 'bout that chief!
--wpd
___
How about a gumstix? (http://www.gumstix.com). It puts you into the
"couple of hundred dollars" realm, though not by much.
--wpd
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
How about www.projectsunlimited.com?
--wpd
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
On 5/21/07, Bogdan Petrisor <[EMAIL PROTECTED]> wrote:
Hi all
I have uploaded the images and moved the warmup page to:
http://geda.seul.org/wiki/geda:gschem_warmup
I added a link to it from:
http://geda.seul.org/wiki/geda:documentation
tutorials section.
Ales, I couldn't find the gsch2pcb w
On 5/20/07, Bogdan Petrisor <[EMAIL PROTECTED]> wrote:
Hello
gschem Warmup (wiki edition) is available at:
http://geda.seul.org/wiki/playground:gschem_warmup
Please comment.
I couldn't find any image upload option so if anybody can shed some light on
how to do it I would
be very grateful.
It
On 5/18/07, Bogdan Petrisor <[EMAIL PROTECTED]> wrote:
I could do it. I did some wiki-editing in my younger days
However I cannot quite understand what you need. Is it like a copy-paste of the
html in the wiki
format and the result should look the same as the presented links?
What I did f
Also, if anybody has some time, getting:
http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html
http://geda.seul.org/docs/current/tutorials/gsch2pcb/transistor-guide.html
into wiki would be nice too, if not I'll do it. :)
If you promise to let me know when/
On 5/17/07, Kai-Martin Knaak <[EMAIL PROTECTED]> wrote:
On Wed, 16 May 2007 22:00:47 -0400, Patrick Doyle wrote:
> OK, it's in. In certainly needs some cleanups, and I'm sorry to have
> lost Bill's nice formatting, but it's out there and ready for folks to
&
Follow the "Documentation" link at the top.
Alternatively, look at http://geda.seul.org/wiki/geda:gsch2pcb_tutorial
--wpd
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
OK, it's in. In certainly needs some cleanups, and I'm sorry to have
lost Bill's nice formatting, but it's out there and ready for folks to
pick away at it. I'll keep picking away at fixing the obvious markup
issues that remain.
Ales -- when you mentioned about moving the playground page into t
On 5/13/07, Ales Hvezda <[EMAIL PROTECTED]> wrote:
> Hi Folks!
> I've completed my first pass at converting Bill Wilson's tutorial from
> HTML syntax to dokuwiki syntax. It may be viewed at
> http://www.geda.seul.org/wiki/playground:playground. I wrote a perl
> script to do the conversion and
Hi Folks!
I've completed my first pass at converting Bill Wilson's tutorial from
HTML syntax to dokuwiki syntax. It may be viewed at
http://www.geda.seul.org/wiki/playground:playground. I wrote a perl
script to do the conversion and have attached it for your
entertainment. I don't know if I hat
Hi folks,
Do any of you make (and sell) a (3V) TTL to RS232 converter? Yes, I
know it's just a Maxim chip and 3 caps that anybody could make in
his/her basement. In fact, looking around, it seems that a fair
number of folks _have_ made these in their basements and sell them.
Since I'm short on
On 4/20/07, Patrick Doyle <[EMAIL PROTECTED]> wrote:
> Yeah, I broke this. Fixed now. At some point, I would really
> like to get this tutorial into the wiki and then all the docs will be
> in the wiki. Any volunteers?
>
Hmmm... I've been looking for something t
Yeah, I broke this. Fixed now. At some point, I would really
like to get this tutorial into the wiki and then all the docs will be
in the wiki. Any volunteers?
Hmmm... I've been looking for something to do to contribute back. Now
that I have my wiki login, it's even possible. Howeve
This is supposed to work.
I will be unable to work on it for 2 weeks. Until then ...
Don't put commands in the middle of the netlist in a file.
ok... no problem. The only reason I did it before was because that
was the way the spice-sdb backend to gnetlist embedded simulation
commands in the
* gnetlist -g spice-sdb -o spice.netlist.wpd TwoStageAmp.sch
.model 2N3904 NPN(IS=1E-14 VAF=100
+ Bf=300 IKF=0.4 XTB=1.5 BR=4
+ CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1
+ TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40
+ Icrating=200m mfg=Philips)
R5 Vin 1 10
.OP
RE1 0 Vem1 100
Q1 Vcoll1 Vbase1
Hello Al and other Gnucap developers on this list...
I posted a message similar to this to the gnucap list a few days ago,
but I suspect the list manager bounced me since I'm not on the list --
I don't see it in the archives anyway. Since then, I've learned some
more, so hear I go again...
The
Since you mentioned it, and I didn't think of it before, it is
easy to change it, so I did ..
Here's the patch ..
in the file "d_bjt.model"
Find:
public_keys {
NPN polarity=pN;
PNP polarity=pP;
}
Change it to:
public_keys {
NPN polarity=pN;
PNP polarity=pP;
NPN1 polarity
On 4/3/07, David Kerber <[EMAIL PROTECTED]> wrote:
As a windows user who does java programming (which is case-sensitive), I can
understand being used to it, but why would you actually prefer it?
habit, comfort, discipline, golly I've never really thought too much
about it before.
--wpd
_
On 4/3/07, al davis <[EMAIL PROTECTED]> wrote:
One more point ...
Node names are case sensitive.
I suppose I should change it, but that part of the code is
planned for major rework anyway, and Verilog is supposed to be
case sensitive.
I'm a 20 year Unix veteran. I prefer case sensitivity :-)
On 4/3/07, al davis <[EMAIL PROTECTED]> wrote:
On Tuesday 03 April 2007 14:08, al davis wrote:
> It still gets a warning on the "NK"
> parameter, and ignores it. That is the same in gnucap or
> ngspice, or in gnucap with spice3f5 of ngspice models.
Actually, it is a one-liner to add the paramete
The reason it works with ng-spice and not gnucap is that it was
written for ng-spice not gnucap.
Gnucap doesn't have levels for the BJT unless you use plugins.
You uncovered a bug that came about with the plugins -- in how
it handles that. The old version would just ignore the level
keyword. Th
> 3) I fetched the spice model for an MMBT3640 from
> Fairchild, and saw that my simple circuit loaded up in
> ngspice, but when I attempt to load it in Gnucap, I get:
>
> * gnetlist -g spice-sdb -s -o mictest.ckt mictest.sch
> .MODEL MMBT3640 PNP LEVEL = 1 IS= 1.41E-15 ISE
>
On 4/3/07, al davis <[EMAIL PROTECTED]> wrote:
On Tuesday 03 April 2007 09:20, Stuart Brorson wrote:
> >> Here's what crashes for me:
> >>
> >> $ ~/local/bin/gnucap spice.netlist.wpd
> >> gnucap> plot ac v(Vout)
> >> gnucap> ac dec 1Hz 1MegHz
> >>
> >> #Freq
> >> Segmentation fault
> >
> > 1. You
With gnucap you can use "fault", "modify", "param" to
interactively change component values. You can also sweep them
with the "DC" command. Spice can sweep sources. Gnucap can
sweep any single value.
How about .. "R1 (2 4) foo"
param foo=10k
op
param foo=47l
That sounds _exactly_ like what I
> Also, FWIW, the 3-29 snapshot crashes when I try to analyze
> the netlist from Stuarts TwoStageAmp example... at least it
> does when I try to run the version I built today. I have,
> perhaps, attached the netlist for your review. If it works
> fine for you, then I'll try rebuilding and paying m
OK, now that I have the slightest inkling of an idea of what I'm
doing, I thought I would ask for some direction...
I want to model a fairly simple circuit consisting of a handful of R's
and C's, a transistor, a diode, a couple of microphones (which I'm
planning on modeling as current sinks), and
On 4/2/07, al davis <[EMAIL PROTECTED]> wrote:
On Monday 02 April 2007 16:08, Patrick Doyle wrote:
> >From you comment, it sounds as if I may not have needed to
> > compile the
>
> ngspice17-modles, and perhaps I could have loaded my spice
> netlists directly. (They
On 4/2/07, al davis <[EMAIL PROTECTED]> wrote:
On Monday 02 April 2007 15:47, Patrick Doyle wrote:
> $ gnucap try1.cir
>
> I get messages that look like:
>
> V1 in 0 PULSE(0 1 10ms 0 0 1s 2s)
> ^ ? need 2 more nodes
> V1 in 0 PULSE(0 1 10ms 0 0 1s 2s)
> ^ ? what&#x
I suggest you play around with both Gnucap and ngspice, and see which
one suits your purposes. I believe Gnucap still accepts SPICE syntax
netlists, so you can netlist using spice-sdb and then use either
Gnucap or ngspice for simulation.
So far, I think that the yum installed FC6 gnucap doesn't
The plugins allow it to be customized. The core will have no
devices, no commands, and no languages. It's all in plugins.
You attach what you want to use. The default will be
Verilog-AMS all the way.
Being somewhat hampered by a total lack of experience in analog
simulation, and the warning of
On 4/2/07, al davis <[EMAIL PROTECTED]> wrote:
On Monday 02 April 2007 12:44, Patrick Doyle wrote:
> I'll take a look at that. I read on Stuart's web page that
> ngspice "experienced a burst of development during 2004, and
> incorporates a number of new pa
On 4/2/07, Chitlesh GOORAH <[EMAIL PROTECTED]> wrote:
On 4/2/07, Patrick Doyle wrote:
> As long as I'm thinking about this and playing with it... does anybody
> know if ngspice can be compiled with readline support? The one I have
> (installed on my FC6 box via yum) does
On 4/2/07, al davis <[EMAIL PROTECTED]> wrote:
How about gnucap?
It has readline, better probe capability, better interactivity,
active development. That's where the future is.
I'll take a look at that. I read on Stuart's web page that ngspice
"experienced a burst of development during 2004,
As long as I'm thinking about this and playing with it... does anybody
know if ngspice can be compiled with readline support? The one I have
(installed on my FC6 box via yum) doesn't support it and I miss the
command line history and editing features. I'll go look into it
shortly, but I figured
On 4/2/07, Stuart Brorson <[EMAIL PROTECTED]> wrote:
> I've tried
>
> tran 100us 100ms
> plot vout 10*vin
>
> and I see a couple of pretty sinewaves. That's enough to get me
> started. So, I guess I'll say I get sensible results.
Sounds good.
You can also try
ac dec 10 1Hz 1MegHz
plot vout vi
> Should I expect more out of the simulation than this?
Since ngspice is kinda bare-bones, what you're getting sounds
reasonable so far.
What happens when you run an analysis? Do you get sensible results?
Hi Stuart,
Thanks for the reply and the explanation. As the purpose of this
exercise wa
OK, recognizing that I'm trying to learn something here without having
done any homework ahead of time, I have my next question...
I grabbed the 2N3904.mod model from Stuart's tarball, tossed in th the
models directory, reran the netlist, and now when I invoke ngspice, I
get:
Warning -- Level no
Look inside the model file and see what it's called inside. It should
look something like
.model 2n3904 NPN(
Ah ha!!!
The model file starts off with:
http://www.w3.org/TR/REC-html40/loose.dtd";>
and degenerates from there... :-)
(wpd crawls sheepishly back into his den)
Thanks. I'll
Here's a step-by-step:
1. Find a 2N3904 model via Google.
2. Save it to a sub-directory directory of your project directory,
say ${PROJ_DIR}/models/2N3904.mod
3. Place a spice-model symbol (in the SPICE directory) into your
schematic. Set its file-name attribute to
${PROJ_DIR}/models/2N3904
OK, it's late, and my frain is pretty bried right now but...
Has anybody played with the TwoStageAmp example recently? I looked at
it tonight in an attempt to start learning something about spice and
I've run into a couple if issues:
1) There is no "models" directory in the example, yet the "SP
Since it's quite common to get reference designs that include gerbers, I
was wondering if it would be feasible to to convert these back into,
effectively, a pcb footprint. I'd have thought there was enough
information in the gerber and drill files to do this - but I admit I
haven't thought it thro
On 3/1/07, Arthur Baldwin <[EMAIL PROTECTED]> wrote:
Oooops! Not all of the data files in OrCAD are text files! The .olb data
files are in binary format. Does anybody know anything about the structure
of .olb data files?
Sincerely,
Arthur
Therein lies the problem. The last time I looked a
On 2/28/07, Arthur Baldwin <[EMAIL PROTECTED]> wrote:
My company is interested in being able to take existing OrCAD schematics and
PCB layouts and converting them into gEDA format(s). If there is someone
working on this already, I'm "all ears" and ready to begin assisting them in
the developmen
I've had good luck with PCB Express (now called Sunstone) and
Advanced Circuits (4pcb.com) for quick-turn small quantity stuff.
I just got a board back from Advanced Circuits and they included a bag
of microwave popcorn in the box along with the 10 PCB's I ordered.
That made my day :-)
Of cours
What I've done is to create a new 2 terminal symbol, called "GNDTIE"
(or something like that) and place that in my schematic. Now I have a
virtual part that the layout guy can play with. I don't know if/how
PCB would handle such a part (never having actually laid out a board
in my life), but I k
On 12/15/06, DJ Delorie <[EMAIL PROTECTED]> wrote:
> You could try some DC-DC chips like the ON-Semi NCP1523, 8 pins and
> only five or six passives. TI or National may have others.
Hey, I could actually use one of those in the furnace board to make
3.3v from 5v. Do they make one that can do 5
On 11/27/06, Patrick Doyle <[EMAIL PROTECTED]> wrote:
Here's a to which question I'll bet somebody on this list knows an answer...
Of course, I meant "Here's a question to which I'll bet..."
It's been a long day :-)
--wpd
Here's a to which question I'll bet somebody on this list knows an answer...
Does anybody know of a comprehensive (or even a not so comprehensive
-- at this point I'll settle for anything) list mapping FLASH
manufacturer/device ID's to devices? Right now, I have a single
number, 20005F22, which
I hate rereading my emails _after_ I've clicked "send"!!!
things like references to librarys on my PC, instructions for drawin
Of course, that would be "libraries" and "drawing"
:-)
Perhaps I'll click "Check spelling" now...
At least this one might be legible :-)
--wpd
__
On 10/30/06, Dan McMahill <[EMAIL PROTECTED]> wrote:
Stuart Brorson wrote:
>> Does an EDIF<->gschem translator exist?
>> Would it be ridiculous to write one? (Anybody can step in here and
>> say, "Well, you could write one, but you would never get the library
>> interface to Orcad to work becau
On 10/27/06, Patrick Doyle <[EMAIL PROTECTED]> wrote:
Hello Friends,
Does anybody on this list know where I could learn the binary file
format of Orcad schematic files? Ultimately, I would like to create a
set of tools to convert back and forth between gschem and Orcad
designs. (I
Hello Friends,
Does anybody on this list know where I could learn the binary file
format of Orcad schematic files? Ultimately, I would like to create a
set of tools to convert back and forth between gschem and Orcad
designs. (Ideally, somebody has already done this, and I don't have
to). I've
I hope to make it to a gathering and meet all of you sometime soon,
but alas, I will be camping with my two boys next weekend. Have
fun... (and pray for nicer weather than this weekend for us) :-)
--wpd
___
geda-user mailing list
geda-user@moria.seul
On 9/22/06, Kai-Martin Knaak <[EMAIL PROTECTED]> wrote:
On Fri, 22 Sep 2006 10:56:16 -0400, Patrick Doyle wrote:
> The thought I've had for title blocks is to define a couple of new
> attributes (after first checking to see if they haven't already been
> defined) calle
On 9/22/06, Alessandro Baretta <[EMAIL PROTECTED]> wrote:
So, fellow coders, how and when shall we address them?
1) Effective support for multipage schematics, with a common "layer 0" for
titleblocks and automatic page numbering.
The thought I've had for title blocks is to define a couple of n
Let's not even THINK about dumbing down the impressive power of PCB
by changing its UI to make it take a few hours instead of a few days to
learn. The trade-off is one that every serious engineer or even
spare-time tinkerer should be more than willing to make.
-Dave
I will alway
On 9/20/06, Vaughn Treude <[EMAIL PROTECTED]> wrote:
As a rank newbie to the gEDA suite, I'd like to weigh in on this. I
downloaded the ISO image install of gEDA, and it went incredibly
smoothly for me. I thought that bundling it all was a clever idea,
because I've gone to dependency hell many
On 9/7/06, DJ Delorie <[EMAIL PROTECTED]> wrote:
> Thanks super, D.J.
It's DJ, not D.J.
It's "super DJ", not "super, D.J." :-)
--wpd
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Take a look at gumstix (www.gumstix.com). It's not a kit in the
manner that you describe, but they've got all the pieces you would
need to construct your own player.
--wpd
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bi
On 9/1/06, Jeff Webb <[EMAIL PROTECTED]> wrote:
David Rowe wrote:
> I use octave (a matlab clone) for plotting, it comes with most linux
> systems:
> ...
> It doesn't have a mouse interface for zooming.
If your version of gnuplot supports it (>= 3.8, I think...), you can have some
mouse zooming
That's strange... how/why did you do that? -- Not that I'm a web
expert, by any means, but I'm just curious about the mechanism in play
when I click on a link in gmail, versus copying and pasting that same
link into the location bar -- they look like they are spelled exactly
the same, and yet, th
Is it just me? When I click on the link's to the photos, I get an
image that says: "Please do not hotlink to images on this site".
Is this a feature of gmail (with which I use to to read public mailing lists)?
--wpd
___
geda-user mailing list
geda-u
1 - 100 of 125 matches
Mail list logo
