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(Updated July 14, 2015, 9:35 a.m.)
Review request for Default.
Repository: gem5
Hi,
the SystemC based simulation is locked when an input event on the terminal
happens. It is easy to reproduce:
build the gem5 SystemC version as described in utils/systemc. Then, run this in
utils/systemc to generate the gem5 config:
../../build/ARM/gem5.opt ../../configs/example/fs.py
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Review request for Default.
Repository: gem5
Description
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Changeset
On July 13, 2015, 8:16 p.m., Joel Hestness wrote:
src/mem/protocol/MESI_Three_Level-L0cache.sm, line 147
http://reviews.gem5.org/r/2957/diff/1/?file=47973#file47973line147
Minor: Convention in other SLICC controller functions is to name
function arguments using lower_underscore
On July 14, 2015, 3:01 p.m., Nilay Vaish wrote:
Are you assuming that physical memory size is a power of 2?
If the physical memory size is not a power of 2, the issue still arises. The
problem lies with how the addresses are assigned to L2 caches.
- David
On Tue, 14 Jul 2015, David Hashe wrote:
On July 14, 2015, 3:01 p.m., Nilay Vaish wrote:
Are you assuming that physical memory size is a power of 2?
If the physical memory size is not a power of 2, the issue still arises. The
problem lies with how the addresses are assigned to L2 caches.
As currently implemented, the parameters you describe result in only 2 of the
L2 caches being used, with the third being empty.
The configuration scripts limit the number of bits to the power of 2 below the
number of L2 caches. If we try to use the power of 2 above the number of L2
caches,
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed.
* build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing passed.
*
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Are you assuming that physical memory size is a power of 2?
- Nilay
On Tue, 14 Jul 2015, Hashe, David wrote:
As currently implemented, the parameters you describe result in only 2
of the L2 caches being used, with the third being empty.
The configuration scripts limit the number of bits to the power of 2
below the number of L2 caches. If we try to use the
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Ship it!
Ship It!
- Steve Reinhardt
On July 13, 2015, 8:15 a.m.,
On July 14, 2015, 9:32 a.m., Nilay Vaish wrote:
configs/ruby/MESI_Three_Level.py, line 89
http://reviews.gem5.org/r/2970/diff/1/?file=48161#file48161line89
To check for power of two, do (v (v-1)) == 0.
That's more efficient, but I'm not sure it's more readable, and I don't think
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configs/ruby/MESI_Three_Level.py (line 89)
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Ship it!
Ship It!
- Steve Reinhardt
On July 13, 2015, 8:16 a.m.,
On July 14, 2015, 9:39 a.m., Steve Reinhardt wrote:
Ship It!
Andreas Hansson wrote:
Out of curiosity...since you added the isSupplyExclusive usage for
writebacks Steve, did you consider this option?
Probably not, else I might have done it this way from the start---it was long
ago
On July 14, 2015, 4:39 p.m., Steve Reinhardt wrote:
Ship It!
Out of curiosity...since you added the isSupplyExclusive usage for writebacks
Steve, did you consider this option?
- Andreas
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