[gem5-dev] Change in gem5/gem5[master]: cpu: fix how a thread starts up in MinorCPU

Hello Giacomo Travaglini, Brandon Potter, Giacomo Gabrielli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/8182 to look at the new patch set (#4). Change subject: cpu: fix how a thread starts up in MinorCPU

[gem5-dev] Change in gem5/gem5[master]: sim: handle the case when there're not enough HW thread contexts

Hello Jason Lowe-Power, Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/9628 to look at the new patch set (#4). Change subject: sim: handle the case when there're not enough HW thread contexts

[gem5-dev] Change in gem5/gem5[master]: sim, cpu: make exit_group halt all threads in a group

Hello Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/9623 to look at the new patch set (#4). Change subject: sim,cpu: make exit_group halt all threads in a group ..

[gem5-dev] Change in gem5/gem5[master]: sim, kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops

Hello Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/9621 to look at the new patch set (#4). Change subject: sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops

[gem5-dev] Change in gem5/gem5[master]: sim: initialize RISC-V's thread pointer register in clone syscall

Hello Jason Lowe-Power, Alec Roelke, Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/9622 to look at the new patch set (#4). Change subject: sim: initialize RISC-V's thread pointer register in clone syscall

[gem5-dev] Change in gem5/gem5[master]: riscv: mark LR, SC and AMO instructions non-speculative

Tuan Ta has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/9643 ) Change subject: riscv: mark LR, SC and AMO instructions non-speculative .. riscv: mark LR, SC and AMO instructions non-speculative LR,

[gem5-dev] Change in gem5/gem5[master]: riscv: fix AMO, LR and SC instructions

Hello Alec Roelke, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/8189 to look at the new patch set (#3). Change subject: riscv: fix AMO, LR and SC instructions .. riscv: fix AMO,

Re: [gem5-dev] Bug for checkpoint by DistIface?

Hi Gabor, Thanks a lot! I did not realize that it is handled by configuration script. Regards, Ryan On Thu, May 17, 2018 at 1:49 AM, Gabor Dozsa wrote: > Hi Ryan, > > Checkpointing is handled in the python configuration scripts. The > configuration script should check the

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move reference count stats update to blk invalidation

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10428 ) Change subject: mem-cache: Move reference count stats update to blk invalidation .. mem-cache: Move reference

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Remove isTouched field from the CacheBlk

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10427 ) Change subject: mem-cache: Remove isTouched field from the CacheBlk .. mem-cache: Remove isTouched field from the

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move replacements stat to the base cache class

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10426 ) Change subject: mem-cache: Move replacements stat to the base cache class .. mem-cache: Move replacements stat to the

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingReq function

Hello Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10424 to look at the new patch set (#3). Change subject: mem-cache: Refactor the cache recvTimingReq function

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Adopt a more sensible cache class hierarchy

Hello Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10431 to look at the new patch set (#4). Change subject: mem-cache: Adopt a more sensible cache class hierarchy

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add a non-coherent cache

Hello Gabe Black, Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/8291 to look at the new patch set (#9). Change subject: mem-cache: Add a non-coherent cache

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Determine if an MSHR has requests from another cache

Hello Jason Lowe-Power, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10422 to look at the new patch set (#3). Change subject: mem-cache: Determine if an MSHR has requests from another cache

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingResp function

Hello Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10423 to look at the new patch set (#3). Change subject: mem-cache: Refactor the cache recvTimingResp function

[gem5-dev] Change in gem5/gem5[master]: base: Add M5 flag for [[nodiscard]] attribute

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10441 ) Change subject: base: Add M5 flag for [[nodiscard]] attribute .. base: Add M5 flag for [[nodiscard]] attribute This

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Simplify writeback for the tempBlock in recvTimingResp

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10421 ) Change subject: mem-cache: Simplify writeback for the tempBlock in recvTimingResp .. mem-cache: Simplify writeback

Re: [gem5-dev] Either delete arm github linux kernel mirrors, or setup auto update, remove issue tracker an link to upstream

On 16/05/2018 08:10, Ciro Santilli wrote: I recommend keeping them on GitHub but with fixes mentioned on title. https://github.com/gem5/linux-arm64-gem5 https://github.com/gem5/linux-arm-gem5 I would be OK removing these repositories as they contain the old kernels (they match

Re: [gem5-dev] RISC-V Full System Support?

Hi Jason and Alec, Thanks for your replies. I pulled the baremetal patches and created a simple system. It's able to run simple custom bootloader I have. Just had to comment this line [1] as it kept being printed out. [1]

Re: [gem5-dev] Bug for checkpoint by DistIface?

Hi Ryan, Checkpointing is handled in the python configuration scripts. The configuration script should check the simulation exit cause and if it is "checkpoint" then it write the checkpoint. If you use fs.py this just works seamlessly. If you use your own python script than you had to add that

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! *