[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! *

[gem5-dev] Change in gem5/gem5[master]: dev: Turn EtherObject into an interface class.

Hello Jason Lowe-Power, Nikos Nikoleris, Gabor Dozsa, Weiping Liao, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17028 to look at the new patch set (#3). Change subject: dev: Turn EtherObject into an interface

[gem5-dev] Change in gem5/gem5[master]: mem: Move the Port base class into sim.

Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17036 to look at the new patch set (#3). Change subject: mem: Move the Port base class into sim.

[gem5-dev] Change in gem5/gem5[master]: python: Change || to && for MessageBuffers in connectPorts.

Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17031 to look at the new patch set (#3). Change subject: python: Change || to && for MessageBuffers in connectPorts.

[gem5-dev] Change in gem5/gem5[master]: mem: Track the MemObject owner in MasterPort and SlavePort.

Hello Anthony Gutierrez, Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17032 to look at the new patch set (#3). Change subject: mem: Track the MemObject owner in MasterPort and

[gem5-dev] Change in gem5/gem5[master]: sim: Add a getPort function to SimObject.

Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17037 to look at the new patch set (#3). Change subject: sim: Add a getPort function to SimObject.

[gem5-dev] Change in gem5/gem5[master]: mem: Move bind() and unbind() into the Port class.

Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17038 to look at the new patch set (#3). Change subject: mem: Move bind() and unbind() into the Port class.

[gem5-dev] Change in gem5/gem5[master]: arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17040 to look at the new patch set (#3). Change subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort.

[gem5-dev] Change in gem5/gem5[master]: python: Improve how templated SimObject classes are handled.

Hello Jason Lowe-Power, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17228 to look at the new patch set (#2). Change subject: python: Improve how templated SimObject classes are handled.

Re: [gem5-dev] ToT build failures for ARM

Great, thanks for the quick fix! Gabe On Thu, Mar 14, 2019 at 12:33 PM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Hi Gabe, > > thanks for pointing that out. > We have addressed the issues with the following patches: > > https://gem5-review.googlesource.com/c/public/gem5/+/17288/1

Re: [gem5-dev] Port configuration overhaul

Definitely. This makes ports a lot more abstract, where they just represent a potential association between two objects. The nature and function of that association is up to either side of the connection, as implement in their Port subclasses. That *could* be the traditional MemObject style of

Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5

I think gem5 would benefit from it for the same reason SystemC simulations do, namely speeding up simulations when doing fast forwarding (perhaps with a binary translating CPU... hypothetically...). It would also be very nice to enable software development for not-yet-existing hardware that has

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Correct cast of template parameter

Andrea Mondelli has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/17308 ) Change subject: arch-arm: Correct cast of template parameter .. arch-arm: Correct cast of template parameter

[gem5-dev] Change in gem5/gem5[master]: arm: Correct cast of template parameter

Andrea Mondelli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17308 Change subject: arm: Correct cast of template parameter .. arm: Correct cast of template parameter Clang with

[gem5-dev] Change in gem5/gem5[master]: python: Teach cxxMethod how to set return_value_policy.

Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/17034 ) Change subject: python: Teach cxxMethod how to set return_value_policy. .. python: Teach cxxMethod how to

[gem5-dev] Change in gem5/gem5[master]: python: Teach PyBindMethod how to set return_value_policy.

Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/17033 ) Change subject: python: Teach PyBindMethod how to set return_value_policy. .. python: Teach PyBindMethod

Re: [gem5-dev] ToT build failures for ARM

Hi Gabe, thanks for pointing that out. We have addressed the issues with the following patches: https://gem5-review.googlesource.com/c/public/gem5/+/17288/1 https://gem5-review.googlesource.com/c/public/gem5/+/17289/1 Thanks Giacomo From: gem5-dev on behalf of

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix use of bitwise operators on booleans

Hello Javier, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17288 to review the following change. Change subject: arch-arm: Fix use of bitwise operators on booleans

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add missing fall-through defaults

Hello Javier, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17289 to review the following change. Change subject: arch-arm: Add missing fall-through defaults ..

[gem5-dev] Change in gem5/gem5[master]: mem: Removed circular include ref

Ryan Gambord has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17270 Change subject: mem: Removed circular include ref .. mem: Removed circular include ref If BasicLink.hh is

[gem5-dev] Change in gem5/gem5[master]: misc: Removed inconsistency in BPRED* debug msgs

Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17248 to look at the new patch set (#2). Change subject: misc: Removed inconsistency in BPRED* debug msgs

[gem5-dev] Change in gem5/gem5[master]: misc: Removed inconsistency in BPRED* debug msgs

Andrea Mondelli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17248 Change subject: misc: Removed inconsistency in BPRED* debug msgs .. misc: Removed inconsistency in BPRED*

[gem5-dev] Change in gem5/gem5[master]: cpu: Added namespace to O3 Cpu Model

Hello Anthony Gutierrez, Jason Lowe-Power, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16950 to look at the new patch set (#4). Change subject: cpu: Added namespace to O3 Cpu Model

[gem5-dev] Change in gem5/gem5[master]: cpu: Refactor of Physical Register implementation

Andrea Mondelli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16908 ) Change subject: cpu: Refactor of Physical Register implementation .. cpu: Refactor of Physical

[gem5-dev] Change in gem5/gem5[master]: sim-se: remove mem proxy in ThreadContext

Brandon Potter has uploaded a new patch set (#14). ( https://gem5-review.googlesource.com/c/public/gem5/+/12305 ) Change subject: sim-se: remove mem proxy in ThreadContext .. sim-se: remove mem proxy in ThreadContext Many

[gem5-dev] Change in gem5/gem5[master]: sim-se: change syscall function signature

Hello Jason Lowe-Power, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/12299 to look at the new patch set (#14). Change subject: sim-se: change syscall function signature

[gem5-dev] Change in gem5/gem5[master]: sim-se: add a faux-filesystem

Hello Anthony Gutierrez, Jason Lowe-Power, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/12119 to look at the new patch set (#15). Change subject: sim-se: add a faux-filesystem

Re: [gem5-dev] Port configuration overhaul

Hey Gabe, I'll need to think about this a bit more myself, but do you think these changes will increase the places we can use ports? Like Andreas was saying, it would be nice to use it for things like interrupt routing, connecting TLBs, and connecting all of the wavefronts in the GPU to the

Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5

Hi Gabe, one of the main reasons for DMI is to speedup simulations, similar to the temporal decoupling in TLM LT or debug transport in order to make the boot-loading. AFAIK DMI is mainly used in virtual platforms that target software development and not hardware architecture design space

Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5

Bump again. On Fri, Mar 1, 2019 at 2:31 PM Gabe Black wrote: > Bump... > > On Wed, Feb 27, 2019 at 9:13 PM Gabe Black wrote: > >> Hi folks. TLM is a communication protocol/mechanism built on top of >> systemc. It supports a mechanism called DMI which stands for direct memory >> interface. The

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! *

[gem5-dev] Change in gem5/gem5[master]: systemc: Delete extra code from src/systemc/tlm_bridge.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17233 Change subject: systemc: Delete extra code from src/systemc/tlm_bridge. .. systemc: Delete extra code from

[gem5-dev] Change in gem5/gem5[master]: systemc: Hook up gem5_getPort to the gem5 getPort mechanism.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17229 Change subject: systemc: Hook up gem5_getPort to the gem5 getPort mechanism. .. systemc: Hook up gem5_getPort to

[gem5-dev] Change in gem5/gem5[master]: systemc: Templatize the gem5/TLM bridge SimObjects.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17234 Change subject: systemc: Templatize the gem5/TLM bridge SimObjects. .. systemc: Templatize the gem5/TLM bridge

[gem5-dev] Change in gem5/gem5[master]: systemc: Provide a utility Port TLM socket wrapper class.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17230 Change subject: systemc: Provide a utility Port TLM socket wrapper class. .. systemc: Provide a utility Port TLM

[gem5-dev] Change in gem5/gem5[master]: python: Improve how templated SimObject classes are handled.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17228 Change subject: python: Improve how templated SimObject classes are handled. .. python: Improve how templated

[gem5-dev] Change in gem5/gem5[master]: python: Switch to the new getPort mechanism to connect ports.

Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17039 to look at the new patch set (#2). Change subject: python: Switch to the new getPort mechanism to connect ports.

[gem5-dev] Change in gem5/gem5[master]: tlm: Initial import of tlm/gem5 bridge code.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17231 Change subject: tlm: Initial import of tlm/gem5 bridge code. .. tlm: Initial import of tlm/gem5 bridge code. This

Re: [gem5-dev] Port configuration overhaul

Great, I'm glad you're in favor of this. I have a new, hopefully more final batch of patches incoming soon which also include application of the new mechanism to TLM sockets. Gabe On Thu, Mar 14, 2019 at 2:47 AM Andreas Sandberg wrote: > Hi Everyone, > > I remember talking to Andreas H about

[gem5-dev] ToT build failures for ARM

These look like issues exposed by compiler version and that (if that's what they are) have known fixes. They should be easy to fix, but I'm going to bed. If they haven't been fixed in the near future I'll send some patches. Representative compiler errors below. Gabe In file included from

[gem5-dev] Change in gem5/gem5[master]: python: Fix unknown params and proxy multiplication

Daniel Carvalho has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/17048 ) Change subject: python: Fix unknown params and proxy multiplication .. python: Fix unknown params and

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 ) Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support

Re: [gem5-dev] Port configuration overhaul

Hi Everyone, I remember talking to Andreas H about this many years ago. If I remember correctly, the main reason the patch wasn't committed at the time was performance related. IIRC, the patch series had a ~10%-20% performance hit. I suspect it the patch Jason pointed to isn't the main reason for