I made the requested changes, and I've maintained the code and it works ok
with the current repo. However, I didn't receive any other feedback, and
didn't get the requisite two ship its.
Cheers,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jan 5, 2015 at 6:27 PM, Andreas Hansson
changeset ab05a080d7c5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ab05a080d7c5
description:
arm: fix build_drive_system when not using default options
when trying to dual boot on arm build_drive_system will only use the
default
values for the
Yes. The source repos used to make those kernels is the same as the source
repos referenced here:
http://gem5.org/ARM_Linux_Kernel
Cheers,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Dec 2, 2014 at 1:02 PM, Guru Prasad gurup...@buffalo.edu wrote:
Hi,
Are the kernel sources
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Review request for Default.
Repository: gem5
Description
---
Changeset
Hello Everyone,
There are some new ARM kernels and disk images that work with gem5 for
both AArch32 (32-bit) and AArch64 (64-bit) on the download page on the gem5
website: http://www.gem5.org/Download
Changes for ARM AArch64 (64-bit):
* There is a new Ubuntu 14.04 based disk image. If you'd
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Ship it!
Ship It!
- Anthony Gutierrez
On Oct. 10, 2014, 10:34 p.m.,
After some inspection of gdb and gem5's source I found the problem. It
seems as though changeset 10037 broke support for gdb in 32 bit ARM.
Specifically the line:
const int MAX_NUMREGS = NUMREGS_64;
I know gem5 will only support AArch64 going forward, so is this something
we don't care about?
changeset f3e9fe1600d6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f3e9fe1600d6
description:
arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2
the Cortex-A15 has a random replacement policy for its L2 cache. see the
Cortex-A15
On July 22, 2014, 10:12 p.m., Andreas Hansson wrote:
src/dev/etherswitch.cc, line 55
http://reviews.gem5.org/r/2305/diff/2/?file=40411#file40411line55
Not sure what the style guide says about the spacing here, but I've
been using
for (auto i: list)
Does
On July 22, 2014, 10:12 p.m., Andreas Hansson wrote:
src/dev/etherswitch.cc, line 165
http://reviews.gem5.org/r/2305/diff/2/?file=40411#file40411line165
Could merge these
broadcasting() basically checks the number broadcasting, so after decrementing
broadcasting() could change.
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(Updated July 24, 2014, 7:44 p.m.)
Review request for Default.
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On July 22, 2014, 4:26 p.m., Anthony Gutierrez wrote:
Some style-related suggestions, for the rest it looks great. Feel free to
punt this to a later patch.
I'd prefer to put it in a later patch, this is all pre-existing code.
- Anthony
On July 22, 2014, 2:24 p.m., Ali Saidi wrote:
src/mem/cache/tags/lru.cc, line 177
http://reviews.gem5.org/r/2167/diff/5/?file=40401#file40401line177
why not unsigned?
I made it unsigned because CacheBlk's set field is an int, as well as the fact
that extractSet() returns an int,
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(Updated July 22, 2014, 6:36 p.m.)
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(Updated July 21, 2014, 6:45 p.m.)
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On July 20, 2014, 11:10 p.m., Steve Reinhardt wrote:
Hi Tony,
Sorry for taking so long to get around to this. I think your patch is
definitely a step in the right direction. My main concern is that it
doesn't go far enough, in the sense that there's still a lot of duplication
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(Updated July 21, 2014, 6:51 p.m.)
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I think this is not only a good idea, but a needed change. I think with
modern monitors one can comfortable fit a few text editors, all displaying
=100 columns, on one screen.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Jul 9, 2014 at 3:45 PM, Ali Saidi via gem5-dev
changeset c625a3c51bac in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c625a3c51bac
description:
base: fix operator== for comparing EthAddr objects
this operator uses memcmp() to detect if two EthAddr object have the
same
address, however memcmp()
I killed the jobs. I'll look into this.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jul 7, 2014 at 8:30 AM, Andreas Hansson via gem5-dev
gem5-dev@gem5.org wrote:
Hi all,
It seems that the regression
Found the problem. This happens because the NSGigE Ethernet controller's
packet filter relies on the overloaded == operator for comparing two
EthAddr objects. This operator returns a memcmp() of the left and right
hand sides, but memcmp returns 0 if each byte of the blocks being compared
are
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(Updated July 7, 2014, 9:52 p.m.)
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(Updated July 2, 2014, 3:51 p.m.)
Review request for Default.
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On July 2, 2014, 12:08 a.m., Steve Reinhardt wrote:
src/base/inet.hh, line 101
http://reviews.gem5.org/r/2304/diff/1/?file=40127#file40127line101
seems like it would be more consistent with the other code to do a loop
up to ETH_ADDR_LEN, but this works too.
fixed
- Anthony
If you just set the number of physical registers to 160 you will get a
deadlock because you're making it possible for the number of instructions
in flight to be greater than the number of registers available and you're
rename table is filling up.
0: system.cpu.rename: [tid:0]: *Stall: RenameMap
changeset 878f2f30b12d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=878f2f30b12d
description:
base: fix some bugs in EthAddr
per the IEEE 802 spec:
1) fixed broadcast() to ensure that all bytes are equal to 0xff.
2) fixed unicast() to
This could depend on a lot of factors. How are you running the benchmarks?
E.g., running SPEC 2k6's gcc to completion with the train input set in FS
mode yields a 6.45% miss rate for bi-mode, while the tournament predictor
yields a 7.12% miss rate.
Anthony Gutierrez
changeset cfb6b578a89a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cfb6b578a89a
description:
arm: make the bi-mode predictor the default for O3_ARM_v7a_BP
the branch predictor used in the Cortex-A15 is a bi-mode style
predictor,
see:
changeset d2deb51a4abf in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d2deb51a4abf
description:
cpu: implement a bi-mode branch predictor
diffstat:
src/cpu/o3/fetch_impl.hh|4 +-
src/cpu/pred/BranchPredictor.py |2 +-
src/cpu/pred/SConscript
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(Updated June 27, 2014, 6:24 p.m.)
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Hello everyone,
I posted a patch that adds an ethernet switch model to gem5. It's not 100%
complete, and I haven't extensively tested it, but it seems to be working
well.
Steve had asked me to post what I had so far to see if it would be a
suitable base switch model, with the hopes that parts of
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Ship it!
Ship It!
- Anthony Gutierrez
On June 3, 2014, 4:33 p.m.,
I strongly support this.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Thu, May 29, 2014 at 3:59 AM, Andreas Hansson via gem5-dev
gem5-dev@gem5.org wrote:
Hi all,
What are your thoughts on bumping the gcc requirement from 4.4 to 4.6?
From a syntactic sugar point of view this
',
which is why grepping just for 'EthAddr' makes it look less used than it
is.
Maybe I'm not looking at the same code you are, but I don't see what you're
saying about only operating on data[0].
Steve
On Thu, May 22, 2014 at 11:28 AM, Anthony Gutierrez via gem5-dev
gem5-dev@gem5.org wrote
()
as '!unicast() !broadcast()' for minimal redundancy.
Other than that though, it looks reasonable to me,
Steve
On Fri, May 23, 2014 at 3:49 AM, Anthony Gutierrez via gem5-dev
gem5-dev@gem5.org wrote:
I'll clarify the question. I built a simple Ethernet switch model and
wanted to use EthAddr
, 2014 at 9:06 AM, Anthony Gutierrez via gem5-dev
gem5-dev@gem5.org wrote:
Ah, I didn't notice the '' there before. The only changes I had to make
were to broadcast and to the constructors since I extract the MAC from
the
packet as an array of uint8_t.
I will probably put the switch
Hello,
Can someone tell me what EthAddr was supposed to be used for? grepping
shows that it isn't really used for anything? I'm curious as to why all the
constructors and methods only operate on data[0]. Is there any reason all 6
bytes are not used?
Thanks,
Anthony Gutierrez
changeset 54d3ef2009a2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=54d3ef2009a2
description:
config: remove unecessary assignment of etherlink interfaces
in makeDualRoot() the etherlink interfaces are set using the tsunami
interface
however, they
I like the idea of this patch as well. In fact, the templating doesn't
really help with extending the CPU model in my experience.
As far as splitting it up into multiple smaller patches, I don't think that
is necessary or really a good idea unless the changes are truly
independent. Instead of
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