[gem5-dev] Re: Incorrect disassembly/register width in Aarch64 ?

intWidth variable (or something similar) Kind Regards Giacomo *From: *Arthur Perais via gem5-dev *Date: *Tuesday, 30 November 2021 at 17:06 *To: *gem5-dev@gem5.org *Cc: *Arthur Perais *Subject: *[gem5-dev] Incorrect disassembly/register width in Aarch64 ? Hi all, I am using a fairly old gem5

[gem5-dev] Incorrect disassembly/register width in Aarch64 ?

addressing this but maybe this has been fixed already, or maybe this is known to happen under some specific configuration of an Aarch64 system. Best, Arthur Perais ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le..

[gem5-dev] Change in gem5/gem5[develop]: mem: Fix bandwidth-delay calculation in AMPM prefetcher

Arthur Perais has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46479 ) Change subject: mem: Fix bandwidth-delay calculation in AMPM prefetcher .. mem: Fix bandwidth-delay calculation in AMPM

[gem5-dev] Change in gem5/gem5[develop]: mem: Fix bandwidth-delay calculation in AMPM prefetcher

Arthur Perais has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46479 ) Change subject: mem: Fix bandwidth-delay calculation in AMPM prefetcher .. mem: Fix bandwidth-delay

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Annotate zero-idiom instructions in ISA parser

Arthur Perais has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46299 ) Change subject: arch-arm: Annotate zero-idiom instructions in ISA parser .. arch-arm: Annotate zero-idiom

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Prevent a mistarget from sending execution on an incorrect path

Arthur Perais has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46260 ) Change subject: cpu-o3: Prevent a mistarget from sending execution on an incorrect path .. cpu-o3: Prevent a mistarget

[gem5-dev] Change in gem5/gem5[develop]: mem: Fix Best Offset Prefetcher (BOP) learning phase code.

Arthur Perais has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46259 ) Change subject: mem: Fix Best Offset Prefetcher (BOP) learning phase code. .. mem: Fix Best Offset Prefetcher (BOP

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Prevent SW prefetches from forwarding from STQ

Arthur Perais has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46261 ) Change subject: cpu-o3: Prevent SW prefetches from forwarding from STQ .. cpu-o3: Prevent SW prefetches from forwarding

[gem5-dev] changeset in gem5: cpu: disallow speculative update of branch pr...

changeset f94c14fd6561 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f94c14fd6561 description: cpu: disallow speculative update of branch predictor tables (o3) The Minor and o3 cpu models share the branch prediction code. Minor relies on the

[gem5-dev] changeset in gem5: cpu: implement an L-TAGE branch predictor

ND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Vignyan Reddy, Dibakar Gope and Arthur Perais, + * fro

[gem5-dev] changeset in gem5: cpu: Clarify meaning of cachePorts variable i...

changeset 9af039ea0c1e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9af039ea0c1e description: cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3 cachePorts currently constrains the number of store packets written to the D-Cache each

Re: [gem5-dev] Review Request 3744: cpu: Remove branch predictor function predictInOrder

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3744/#review9165 --- Ship it! Ship It! - Arthur Perais On nov. 23, 2016, 4:10 après-midi

Re: [gem5-dev] Review Request 3743: cpu: implement L-TAGE branch predictor

r/3743/#review9160 --- On nov. 23, 2016, 2:52 après-midi, Arthur Perais wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://revie

Re: [gem5-dev] Review Request 3743: cpu: implement L-TAGE branch predictor

. Diffs (updated) - src/cpu/pred/BranchPredictor.py 1d085f66c4ca src/cpu/pred/SConscript 1d085f66c4ca src/cpu/pred/ltage.hh PRE-CREATION src/cpu/pred/ltage.cc PRE-CREATION Diff: http://reviews.gem5.org/r/3743/diff/ Testing --- Thanks, Arthur Perais

Re: [gem5-dev] Review Request 3710: cpu: Resolve targets of predicted 'taken' conditional direct branches at decode (o3)

---- On nov. 18, 2016, 3:21 après-midi, Arthur Perais wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3710/ > --

Re: [gem5-dev] Review Request 3743: cpu: implement L-TAGE branch predictor

quot;Jason Lowe-Power" <ja...@lowepower.com>, > "Arthur Perais" <arthur.per...@inria.fr> > Envoyé: Mardi 22 Novembre 2016 19:15:03 > Objet: Re: Review Request 3743: cpu: implement L-TAGE branch predictor > This is an automatically generated e-mail. To reply, visit: >

[gem5-dev] Review Request 3743: cpu: implement L-TAGE branch predictor

PRE-CREATION src/cpu/pred/ltage.cc PRE-CREATION Diff: http://reviews.gem5.org/r/3743/diff/ Testing --- Thanks, Arthur Perais ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Patches of TAGE branch predictor

I suppose it was called by the InOrder CPU once upon a time. Now the Minor CPU uses the same branch prediction code as the o3 CPU, which may have led to the current inconsistencies in how branch predictors handle out-of-order mispredictions (or not :)). I've submitted a patch regarding this

Re: [gem5-dev] Review Request 3710: cpu: Resolve targets of predicted 'taken' conditional direct branches at decode (o3)

://reviews.gem5.org/r/3710/diff/ Testing --- util/regress --modes=se build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: FAILED! (Python says "NameError: name 'TrafficGen' is not defined"). I'm guessing this is OK as I get the same error without my patch. Thanks, Art

[gem5-dev] Review Request 3727: cpu: disallow speculative update of the conditional branch predictor tables (o3)

rnament.hh 1d085f66c4ca src/cpu/pred/tournament.cc 1d085f66c4ca Diff: http://reviews.gem5.org/r/3727/diff/ Testing --- Fast regressions (SE) booting Linux (FS) Thanks, Arthur Perais ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.o

[gem5-dev] Review Request 3722: cpu: change comments in tournament branch predictor to reflect what the code does

1d085f66c4ca Diff: http://reviews.gem5.org/r/3722/diff/ Testing (updated) --- Modifying comments only. Thanks, Arthur Perais ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Branch prediction infrastructure rationale

High guys, We just noticed some interesting behavior in the branch prediction infrastructure (bpred_unit.cc). I was wondering if some of you could shed light on it. When a branch is mispredicted at execute, all younger branches in the history of branches are removed. Then, the predictor is

Re: [gem5-dev] Review Request 3453: o3: Clarify meaning of cachePorts variable in lsq_unit.hh

disagree with the changes? Cheers, Arthur. Le 05/05/2016 15:01, Nathanael Premillieu a écrit : This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3453/ Ship it! Ship It! - Nathanael Premillieu On April 26th, 2016, 12:42 p.m. UTC, Arthur Perais wrote: Revi

[gem5-dev] Review Request 3298: arm: Implement store-pair (aarch64) as a single micro-op

/str64.isa 3d7a85d71bd1 Diff: http://reviews.gem5.org/r/3298/diff/ Testing --- FS: Boots linux (3.16) SE: Runs olden benchmarks Thanks, Arthur Perais ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev