* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed.
*
Hello Andreas
Thank your for answering me so quickly
I used gprof in FS mode but the information i get wasn't as detailed as i
want too.
By profiling my application i'm looking for the number of read and write
acces to L1,L2 caches and acces time.
Is it possible on gem5 ? and how can i do to get
Reponses below marked with [BB]:
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Nilay Vaish
Sent: Tuesday, May 19, 2015 3:41 PM
To: Default
Subject: Re: [gem5-dev] Review Request 2808: slicc: improved stalling support
in protocols
On Tue, 19 May 2015,
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(Updated May 21, 2015, 1:42 p.m.)
Review request for Default.
Repository: gem5
On May 11, 2015, 8:50 p.m., Nilay Vaish wrote:
Why do we need this special case?
Shuai Che wrote:
This case is used to get the application current running path.
Nilay Vaish wrote:
If I have read the patch correctly, the behaviour now will be that
current working
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(Updated May 21, 2015, 1:41 p.m.)
Review request for Default.
Summary (updated)
Hello Andreas
I'm may be wrong but i thing all those informations that i want can be
extracted from stats.txt file !
Please fell free to correct me if i'm mistaken
Tanks !
2015-05-21 10:59 GMT+02:00 ESPERANCE ASNGAR esperance.asn...@gmail.com:
Hello Andreas
Thank your for answering me so
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Ship it!
Ship It!
- Jason Power
On May 21, 2015, 1:58 p.m., Marco
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Review request for Default.
Repository: gem5
Description
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Changeset
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http://reviews.gem5.org/r/2842/
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Review request for Default.
Repository: gem5
Description
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Changeset
On May 14, 2015, 7:33 p.m., Joel Hestness wrote:
From experience with the O3 CPU, this is a VERY important change for
simulated CPU performance. I appreciate the effort to finally fix this.
It would be nice for the Ruby and gem5-classic memory hierarchies to
provide the same access
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src/mem/ruby/system/Sequencer.cc (line 588)
On May 14, 2015, 7:33 p.m., Joel Hestness wrote:
From experience with the O3 CPU, this is a VERY important change for
simulated CPU performance. I appreciate the effort to finally fix this.
It would be nice for the Ruby and gem5-classic memory hierarchies to
provide the same access
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Review request for Default.
Repository: gem5
Description
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Changeset
On Wed, 20 May 2015, Brad Beckmann wrote:
On May 12, 2015, 8:47 p.m., Nilay Vaish wrote:
There are two problems I have with this patch. Firstly, it changes the
generally
accepted meaning of '*'. Secondly, it is adding another keyword to the language
which is, in my opinion, not required.
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