Tuan Ta has submitted this change and it was merged. (
https://gem5-review.googlesource.com/9261 )
Change subject: riscv: throw IllegalInstFault when decoding invalid
instructions
..
riscv: throw IllegalInstFault when
This is on an chromebook based on the RK3399 with only ~4GB of RAM which is
not ideal, although we have a bigger machine in the works for the future. I
agree with your reasoning and don't think option 1 is a problem. We're
using static DTBs so I don't think that's an issue either. In my script,
Robert Scheffel has uploaded this change for review. (
https://gem5-review.googlesource.com/9281
Change subject: arch-riscv: implement bare metal specific system class
..
arch-riscv: implement bare metal specific system
Robert Scheffel has uploaded this change for review. (
https://gem5-review.googlesource.com/9282
Change subject: arch-riscv: enable rudimentary fs simulation
..
arch-riscv: enable rudimentary fs simulation
The RiscvSystem
Giacomo Travaglini has uploaded a new patch set (#8) to the change
originally created by Chun-Chen TK Hsu. (
https://gem5-review.googlesource.com/9101 )
Change subject: arch, arm: Fix implicit-fallthrough GCC warnings
..
Hello Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/8981
to look at the new patch set (#4).
Change subject: mem-cache: Create BRRIP Replacement Policy
..
Daniel Carvalho has uploaded a new patch set (#2). (
https://gem5-review.googlesource.com/9001 )
Change subject: mem-cache: Create NRU Replacement Policy
..
mem-cache: Create NRU Replacement Policy
Implementation of a Not
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/8891
to look at the new patch set (#3).
Change subject: mem-cache: Create RRIP replacement policy
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/8889
to look at the new patch set (#3).
Change subject: mem-cache: Create MRU replacement policy
Hello Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/9003
to look at the new patch set (#2).
Change subject: mem-cache: Create BIP Replacement Policy
..
mem-cache:
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/
to look at the new patch set (#4).
Change subject: mem-cache: Create FIFO replacement policy
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/8890
to look at the new patch set (#3).
Change subject: mem-cache: Create LFU replacement policy
Hmm, OK, this is very strange.
What type of hardware are you running on? Is it an A57-based chip or something
else? Also, what's your simulation quantum? I have been able to run with a
0.5ms quantum (5e8 ticks).
I think the following trace of two CPUs running in KVM should be roughly
Hello Nikos Nikoleris, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/8501
to look at the new patch set (#12).
Change subject: mem-cache: Split array indexing and replacement policies.
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing:
FAILED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic:
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing:
FAILED!
*
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