Robert Scheffel has uploaded this change for review. (
https://gem5-review.googlesource.com/9282
Change subject: arch-riscv: enable rudimentary fs simulation
......................................................................
arch-riscv: enable rudimentary fs simulation
The RiscvSystem class is extended with a variable, that indicates, if we
execute a bare metal system or not.
Change-Id: I973793fe723ce0b2d58d3f3cfd920d3c7106fc63
---
M src/arch/riscv/RiscvSystem.py
M src/arch/riscv/system.cc
M src/arch/riscv/system.hh
M src/arch/riscv/tlb.cc
4 files changed, 82 insertions(+), 37 deletions(-)
diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index 89e6cf0..a9eca6e 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -28,6 +28,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Alec Roelke
+# Robert Scheffel
from m5.params import *
from System import System
@@ -36,6 +37,7 @@
class RiscvSystem(System):
type = 'RiscvSystem'
cxx_header = 'arch/riscv/system.hh'
+ bare_metal = Param.Bool(False, "Using Bare Metal Application?")
resetVect = Param.Addr(0x0, 'Reset vector')
load_addr_mask = 0xFFFFFFFFFFFFFFFF
@@ -44,3 +46,5 @@
type = 'BareMetalRiscvSystem'
cxx_header = 'arch/riscv/bare_metal/system.hh'
bootloader = Param.String("File, that contains the bootloader code")
+
+ bare_metal = True
diff --git a/src/arch/riscv/system.cc b/src/arch/riscv/system.cc
index c36aa99..2b33923 100644
--- a/src/arch/riscv/system.cc
+++ b/src/arch/riscv/system.cc
@@ -29,6 +29,7 @@
* Authors: Ali Saidi
* Nathan Binkert
* Jaidev Patwardhan
+ * Robert Scheffel
*/
#include "arch/riscv/system.hh"
@@ -46,6 +47,7 @@
RiscvSystem::RiscvSystem(Params *p)
: System(p),
+ _isBareMetal(p->bare_metal),
_resetVect(p->resetVect)
{
}
@@ -63,6 +65,15 @@
return dynamic_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect();
}
+/**
+ * Return the bare metal checker.
+ */
+bool
+RiscvSystem::isBareMetal(ThreadContext* tc)
+{
+ return dynamic_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal();
+}
+
Addr
RiscvSystem::fixFuncEventAddr(Addr addr)
{
@@ -84,4 +95,3 @@
{
return new RiscvSystem(this);
}
-
diff --git a/src/arch/riscv/system.hh b/src/arch/riscv/system.hh
index 4971a10..46276b3 100644
--- a/src/arch/riscv/system.hh
+++ b/src/arch/riscv/system.hh
@@ -29,6 +29,7 @@
* Authors: Ali Saidi
* Nathan Binkert
* Jaidev Patwardhan
+ * Robert Scheffel
*/
#ifndef __ARCH_RISCV_SYSTEM_HH__
@@ -48,6 +49,8 @@
class RiscvSystem : public System
{
protected:
+ // checker for bare metal application
+ bool _isBareMetal;
// entry point for simulation
Addr _resetVect;
@@ -56,12 +59,18 @@
RiscvSystem(Params *p);
~RiscvSystem();
- // return reset address
+ // return reset vector
Addr resetVect() const { return _resetVect; }
+ // return bare metal checker
+ bool isBareMetal() const { return _isBareMetal; }
+
// return reset address of thread context
static Addr resetVect(ThreadContext* tc);
+ // return bare metal checker of thread context
+ static bool isBareMetal(ThreadContext* tc);
+
virtual bool breakpoint();
public:
@@ -101,4 +110,3 @@
};
#endif
-
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index b92327f..96b8bdb 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -1,7 +1,6 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
- * Copyright (c) 2018 TU Dresden
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -32,7 +31,6 @@
* Jaidev Patwardhan
* Zhengxing Li
* Deyuan Guo
- * Robert Scheffel
*/
#include "arch/riscv/tlb.hh"
@@ -43,6 +41,7 @@
#include "arch/riscv/faults.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/pra_constants.hh"
+#include "arch/riscv/system.hh"
#include "arch/riscv/utility.hh"
#include "base/inifile.hh"
#include "base/str.hh"
@@ -289,23 +288,25 @@
{
if (FullSystem) {
/**
- * as we currently support bare metal only, we set the physical
flag
- * that means we treat all addresses as physical addresses
- * no translation needed
+ * check if we simulate a bare metal system
+ * if so, we have no tlb, phys addr == virt addr
*/
- req->setFlags(Request::PHYSICAL);
- }
+ if (RiscvSystem::isBareMetal(tc))
+ req->setFlags(Request::PHYSICAL);
- if (req->getFlags() & Request::PHYSICAL) {
- /**
- * we simply set the virtual address to physical address
- */
- req->setPaddr(req->getVaddr());
- /**
- * check if the request is cacheable
- * seems like this could have an impact on performance
- */
- return checkCacheability(req);
+ if (req->getFlags() & Request::PHYSICAL) {
+ /**
+ * we simply set the virtual address to physical address
+ */
+ req->setPaddr(req->getVaddr());
+ return checkCacheability(req);
+ } else {
+ /**
+ * as we currently support bare metal only, we throw a panic,
+ * if it is not a bare metal system
+ */
+ panic("translateInst not implemented in RISC-V.\n");
+ }
} else {
Process * p = tc->getProcessPtr();
@@ -320,27 +321,49 @@
Fault
TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
{
- if (FullSystem)
- panic("translateData not implemented in RISC-V.\n");
+ if (FullSystem) {
+ /**
+ * check if we simulate a bare metal system
+ * if so, we have no tlb, phys addr == virt addr
+ */
+ if (RiscvSystem::isBareMetal(tc))
+ req->setFlags(Request::PHYSICAL);
- // In the O3 CPU model, sometimes a memory access will be speculatively
- // executed along a branch that will end up not being taken where the
- // address is invalid. In that case, return a fault rather than trying
- // to translate it (which will cause a panic). Since RISC-V allows
- // unaligned memory accesses, this should only happen if the request's
- // length is long enough to wrap around from the end of the memory to
the
- // start.
- assert(req->getSize() > 0);
- if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
- return make_shared<GenericPageTableFault>(req->getVaddr());
+ if (req->getFlags() & Request::PHYSICAL) {
+ /**
+ * we simply set the virtual address to physical address
+ */
+ req->setPaddr(req->getVaddr());
+ return checkCacheability(req);
+ } else {
+ /**
+ * as we currently support bare metal only, we throw a panic,
+ * if it is not a bare metal system
+ */
+ panic("translateData not implemented in RISC-V.\n");
+ }
+ }
+ else
+ {
+ // In the O3 CPU model, sometimes a memory access will be
speculatively
+ // executed along a branch that will end up not being taken where
the
+ // address is invalid. In that case, return a fault rather than
trying
+ // to translate it (which will cause a panic). Since RISC-V allows
+ // unaligned memory accesses, this should only happen if the
request's
+ // length is long enough to wrap around from the end of the memory
to
+ // the start.
+ assert(req->getSize() > 0);
+ if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+ return make_shared<GenericPageTableFault>(req->getVaddr());
- Process * p = tc->getProcessPtr();
+ Process * p = tc->getProcessPtr();
- Fault fault = p->pTable->translate(req);
- if (fault != NoFault)
- return fault;
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
- return NoFault;
+ return NoFault;
+ }
}
Fault
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I973793fe723ce0b2d58d3f3cfd920d3c7106fc63
Gerrit-Change-Number: 9282
Gerrit-PatchSet: 1
Gerrit-Owner: Robert Scheffel <[email protected]>
Gerrit-MessageType: newchange
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