[gem5-dev] Change in gem5/gem5[develop]: base, arch-hsail: Fix GPU build

2020-03-26 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27136 )



Change subject: base,arch-hsail: Fix GPU build
..

base,arch-hsail: Fix GPU build

The GPU build is currently broken due to recent changes. This fixes
the build after changes to local access, removal of getSyscallArg,
and creating of AMO header in base.

Change-Id: I43506f6fb0a92a61a50ecb9efa7ee279ecb21d98
---
M src/base/amo.hh
M src/gpu-compute/cl_driver.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
5 files changed, 17 insertions(+), 17 deletions(-)



diff --git a/src/base/amo.hh b/src/base/amo.hh
index 718b346..44dec8b 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 

 struct AtomicOpFunctor
 {
diff --git a/src/gpu-compute/cl_driver.cc b/src/gpu-compute/cl_driver.cc
index d8a4618..ee86017 100644
--- a/src/gpu-compute/cl_driver.cc
+++ b/src/gpu-compute/cl_driver.cc
@@ -105,9 +105,6 @@
 int
 ClDriver::ioctl(ThreadContext *tc, unsigned req, Addr buf_addr)
 {
-int index = 2;
-auto process = tc->getProcessPtr();
-
 switch (req) {
   case HSA_GET_SIZES:
 {
diff --git a/src/gpu-compute/gpu_dyn_inst.hh  
b/src/gpu-compute/gpu_dyn_inst.hh

index a4a6ffb..bee08e3 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -251,31 +251,31 @@
 // when true, call execContinuation when response arrives
 bool useContinuation;

-template AtomicOpFunctor*
+template AtomicOpFunctorPtr
 makeAtomicOpFunctor(c0 *reg0, c0 *reg1)
 {
 if (isAtomicAnd()) {
-return new AtomicOpAnd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicOr()) {
-return new AtomicOpOr(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicXor()) {
-return new AtomicOpXor(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicCAS()) {
-return new AtomicOpCAS(*reg0, *reg1, cu);
+return m5::make_unique>(*reg0, *reg1, cu);
 } else if (isAtomicExch()) {
-return new AtomicOpExch(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicAdd()) {
-return new AtomicOpAdd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicSub()) {
-return new AtomicOpSub(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicInc()) {
-return new AtomicOpInc();
+return m5::make_unique>();
 } else if (isAtomicDec()) {
-return new AtomicOpDec();
+return m5::make_unique>();
 } else if (isAtomicMax()) {
-return new AtomicOpMax(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicMin()) {
-return new AtomicOpMin(*reg0);
+return m5::make_unique>(*reg0);
 } else {
 fatal("Unrecognized atomic operation");
 }
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index 12fb9aa..2ae40da 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -43,6 +43,7 @@
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/regs/misc.hh"
+#include "arch/x86/regs/msr.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"
@@ -426,7 +427,7 @@
 // If this is true, we're dealing with a request
 // to a non-memory address space.
 if (seg == SEGMENT_REG_MS) {
-return translateInt(mode == Read, req, tc);
+return translateInt(mode == Mode::Read, req, tc);
 }

 delayedResponse = false;
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 6ed4ba1..dbd3a16 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -175,7 +175,8 @@
  */
 std::vector entryList;

-Fault translateInt(const RequestPtr , ThreadContext *tc);
+Fault translateInt(bool read, const RequestPtr ,
+   ThreadContext *tc);

 Fault translate(const RequestPtr , ThreadContext *tc,
 Translation *translation, Mode mode, bool ,

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I43506f6fb0a92a61a50ecb9efa7ee279ecb21d98
Gerrit-Change-Number: 27136
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Add Gabe Black as the scons and util maintainer.

2020-03-26 Thread Gabe Black (Gerrit)
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27143 )



Change subject: misc: Add Gabe Black as the scons and util maintainer.
..

misc: Add Gabe Black as the scons and util maintainer.

Change-Id: I222c25ebd7b28ddad4bb903b6fd9e15b429b1039
---
M MAINTAINERS
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/MAINTAINERS b/MAINTAINERS
index 949657d..1a46a70 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -87,6 +87,7 @@
   Andreas Sandberg 

 scons: Build system
+  Gabe Black 

 sim: General simulation components
   Jason Lowe-Power 
@@ -110,3 +111,4 @@
   Bobby Bruce 

 util:
+  Gabe Black 

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Gerrit-Change-Id: I222c25ebd7b28ddad4bb903b6fd9e15b429b1039
Gerrit-Change-Number: 27143
Gerrit-PatchSet: 1
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[gem5-dev] New blog post: X86 Linux Boot Status on gem5-19

2020-03-26 Thread Jason Lowe-Power
Hi all,

Ayaz Akram is our first blog contributor! He has written up some of the
work we've been doing at UC Davis trying to understand gem5's current
status. Ayaz ran 320 different gem5 configurations and, sadly, found that
most of them don't even boot Linux :(. However, we've already fixed some of
the bugs, and hopefully (with your help!) we'll fix more before the gem5-20
release!

See http://www.gem5.org/project/2020/03/09/boot-tests.html for the details.

Cheers,
Jason

PS: Some of you may have seen that ISCA will be virtual this year due to
the COVID-19 pandemic. This means that the Learning gem5 Tutorial and the
gem5 Users Workshop will also be virtual. I'm actually quite excited by
this since this will make it easier for you all to participate in the
Workshop and attend the Tutorial! More information on how this will work is
coming soon. Stay safe and healthy!
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Checkpoint from MOESI_hammer Ruby hangs

2020-03-26 Thread Hussein Elnawawy (Gerrit)
Hussein Elnawawy has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25683 )


Change subject: mem-ruby: Checkpoint from MOESI_hammer Ruby hangs
..

mem-ruby: Checkpoint from MOESI_hammer Ruby hangs

Fix MOESI_hammer checkpoint hanging.
The function markRemoved() should be called before hitCallback(),
not after it. The reason is that hitCallback() checks if draining is
complete based on the value of "m_outstanding_count". And since
markRemoved() is responsible for decrementing "m_outstanding_count",
hitCallback() does not see that there are no outstanding requests.

Reported by: Timothy Hayes
Jira: https://gem5.atlassian.net/browse/GEM5-331
Change-Id: I14c34be79843b172ae994ab1792fe4ce6cf5cf6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25683
Reviewed-by: Timothy Hayes 
Reviewed-by: John Alsop 
Maintainer: Bradford Beckmann 
Tested-by: kokoro 
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 6 insertions(+), 4 deletions(-)

Approvals:
  John Alsop: Looks good to me, but someone else must approve
  Timothy Hayes: Looks good to me, approved
  Bradford Beckmann: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/system/Sequencer.cc  
b/src/mem/ruby/system/Sequencer.cc

index a90523e..f815787 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -360,20 +360,22 @@
 } else {
 aliased_stores++;
 }
+markRemoved();
+ruby_request = false;
 hitCallback(_req, data, success, mach, externalHit,
 initialRequestTime, forwardRequestTime,
 firstResponseTime);
 } else {
 // handle read request
 assert(!ruby_request);
+markRemoved();
+ruby_request = false;
 aliased_loads++;
 hitCallback(_req, data, true, mach, externalHit,
 initialRequestTime, forwardRequestTime,
 firstResponseTime);
 }
 seq_req_list.pop_front();
-markRemoved();
-ruby_request = false;
 }

 // free all outstanding requests corresponding to this address
@@ -421,12 +423,12 @@
   initialRequestTime, forwardRequestTime,
   firstResponseTime);
 }
+markRemoved();
+ruby_request = false;
 hitCallback(_req, data, true, mach, externalHit,
 initialRequestTime, forwardRequestTime,
 firstResponseTime);
 seq_req_list.pop_front();
-markRemoved();
-ruby_request = false;
 }

 // free all outstanding requests corresponding to this address

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I14c34be79843b172ae994ab1792fe4ce6cf5cf6e
Gerrit-Change-Number: 25683
Gerrit-PatchSet: 6
Gerrit-Owner: Hussein Elnawawy 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hussein Elnawawy 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: John Alsop 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-Reviewer: Tuan Ta 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Ciro Santilli 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use the scons environment when marshalling.

2020-03-26 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27123 )


Change subject: scons: Use the scons environment when marshalling.
..

scons: Use the scons environment when marshalling.

scons maintains an environment (in the shell sense) in the ENV
construction variable for use when running external programs. When we
run the "marshal" program which gathers up python objects to embed in
the gem5 binary, it's run by subprocess instead of through scons, and it
uses its own environment inherited from the host system.

Instead, this change makes the subprocess function use the scons
environment when calling "marshal". This ensures the environment is
consistent between this command and other commands scons runs.

This is usually not very important, but some tools like asan take
options set through the environment, and they may need to be adjusted
sometimes.

Change-Id: I671b447657ed8fad45fac7393cc1c09073bf3d3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27123
Reviewed-by: Nikos Nikoleris 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/SConscript
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/SConscript b/src/SConscript
index 2cdf6cb..ed7e1ea 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1166,7 +1166,8 @@

 import subprocess

-marshalled = subprocess.check_output([source[0].abspath,  
str(source[1])])

+marshalled = subprocess.check_output(
+[source[0].abspath, str(source[1])], env=env['ENV'])

 compressed = zlib.compress(marshalled)
 data = compressed

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Gerrit-Branch: develop
Gerrit-Change-Id: I671b447657ed8fad45fac7393cc1c09073bf3d3a
Gerrit-Change-Number: 27123
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
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Gerrit-CC: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: util: Add a file to suppress spurious lsan leaks in the python lib.

2020-03-26 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27124 )


Change subject: util: Add a file to suppress spurious lsan leaks in the  
python lib.

..

util: Add a file to suppress spurious lsan leaks in the python lib.

The python interpreter does some fancy things with memory which trips up
the lsan leak checker which comes along with asan. This file simply
tells lsan to ignore those leaks.

To use it when running a binary, set the LSAN_OPTIONS environment
variable to "suppressions=${PATH TO SUPPRESSIONS FILE}". To disable the
a report on the leaks that were suppressed, you should also set
"print_suppressions=0". Multiple options can be set by seperating them
with ":"s.

LSAN_OPTIONS=suppressions=util/lsan-suppressions:print_suppressions=0

Change-Id: Ie4d712c6b95f429e67361c41a9b545a8536f2511
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27124
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A util/lsan-suppressions
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/lsan-suppressions b/util/lsan-suppressions
new file mode 100644
index 000..221370a
--- /dev/null
+++ b/util/lsan-suppressions
@@ -0,0 +1,2 @@
+# Suppress detection of leaks from within the python 2.7 interpreter.
+leak:libpython2.7.so

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Gerrit-Change-Number: 27124
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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Gerrit-CC: Earl Ou 
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Gerrit-CC: Yu-hsin Wang 
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[gem5-dev] Change in gem5/gem5[develop]: tests, misc: Updated presubmit YAML to use main.py '-t' flag

2020-03-26 Thread Bobby R. Bruce (Gerrit)
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27064 )


Change subject: tests,misc: Updated presubmit YAML to use main.py '-t' flag
..

tests,misc: Updated presubmit YAML to use main.py '-t' flag

This minor change reduces the presubmit build time by about 10 to 15
minutes.

Change-Id: I3a87d1a720b17fd22a9dbdbeebfb32e4be178c56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27064
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
---
M cloudbuild_presubmit.yaml
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/cloudbuild_presubmit.yaml b/cloudbuild_presubmit.yaml
index e20f273..5fd46ad 100644
--- a/cloudbuild_presubmit.yaml
+++ b/cloudbuild_presubmit.yaml
@@ -23,7 +23,7 @@
 - name: 'gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest'
   dir: 'tests'
   entrypoint: 'python'
-  args: ['main.py', 'run', '-j', '4', '--length', 'quick']
+  args: ['main.py', 'run', '-j', '4', '-t', '8', '--length', 'quick']

 images: ['gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest']
 options:

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3a87d1a720b17fd22a9dbdbeebfb32e4be178c56
Gerrit-Change-Number: 27064
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Migrated 10.linux-boot scons-based test to testlib

2020-03-26 Thread Bobby R. Bruce (Gerrit)
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26324 )


Change subject: tests: Migrated 10.linux-boot scons-based test to testlib
..

tests: Migrated 10.linux-boot scons-based test to testlib

This test has purposely been designed to be easily extendible for future
x86 boot tests. Right now, it only runs two basic Ubuntu boot test
setups.

Change-Id: I81385b5dfc0764af2ec02999eb26e523bd09a595
Issue-on: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26324
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A tests/gem5/x86-boot-tests/run_exit.py
A tests/gem5/x86-boot-tests/system/caches.py
A tests/gem5/x86-boot-tests/system/system.py
A tests/gem5/x86-boot-tests/test_linux_boot.py
4 files changed, 616 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/x86-boot-tests/run_exit.py  
b/tests/gem5/x86-boot-tests/run_exit.py

new file mode 100644
index 000..24edcc5
--- /dev/null
+++ b/tests/gem5/x86-boot-tests/run_exit.py
@@ -0,0 +1,79 @@
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import argparse
+import sys
+import os
+
+import m5
+import m5.ticks
+from m5.objects import *
+
+sys.path.append(os.path.dirname(__file__) + '/system')
+sys.path.append(os.path.dirname(__file__) + '/../../../configs/common/')
+from system import *
+
+parser = argparse.ArgumentParser(description="")
+parser.add_argument('--kernel', type=str)
+parser.add_argument('--disk', type=str)
+parser.add_argument('--cpu-type',  
choices=['atomic', 'kvm', 'o3', 'simple',])

+parser.add_argument('--num-cpus', type=int)
+parser.add_argument('--boot-type', choices=['init', 'systemd',])
+
+#(options, args) = parser.parse_args()
+args = parser.parse_args()
+
+# create the system we are going to simulate
+system = MySystem(args.kernel, args.disk, args.cpu_type, args.num_cpus)
+
+if args.boot_type == "init":
+# Simply run "exit.sh"
+system.boot_osflags += ' init=/root/exit.sh'
+else:
+if args.boot_type != "systemd":
+m5.fatal("Bad option for boot_type. init or systemd.")
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = True, system = system)
+
+if system.getHostParallel():
+# Required for running kvm on multiple host cores.
+# Uses gem5's parallel event queue feature
+# Note: The simulator is quite picky about this number!
+root.sim_quantum = int(1e9) # 1 ms
+
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+print("Running the simulation")
+exit_event = m5.simulate()
+
+if exit_event.getCause() != "m5_exit instruction encountered":
+print("Failed to exit correctly")
+exit(1)
+else:
+print("Success!")
+exit(0)
diff --git a/tests/gem5/x86-boot-tests/system/caches.py  
b/tests/gem5/x86-boot-tests/system/caches.py

new file mode 100755
index 000..2c2e520
--- /dev/null
+++ b/tests/gem5/x86-boot-tests/system/caches.py
@@ -0,0 +1,143 @@
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of 

[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: fix store-release issuing

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27135 )



Change subject: cpu-minor: fix store-release issuing
..

cpu-minor: fix store-release issuing

Store with release flag are treated like store conditionals and are not
bufferable. Also they are only sent when the store buffer is empty to
satisfy the release semantics.

Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Signed-off-by: Tiago Mück 
---
M src/cpu/minor/lsq.cc
1 file changed, 12 insertions(+), 2 deletions(-)



diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e50d498..e4a9dc0 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014,2017-2018 ARM Limited
+ * Copyright (c) 2013-2014,2017-2018,2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1029,10 +1029,11 @@

 bool is_load = request->isLoad;
 bool is_llsc = request->request->isLLSC();
+bool is_release = request->request->isRelease();
 bool is_swap = request->request->isSwap();
 bool is_atomic = request->request->isAtomic();
 bool bufferable = !(request->request->isStrictlyOrdered() ||
-is_llsc || is_swap || is_atomic);
+is_llsc || is_swap || is_atomic || is_release);

 if (is_load) {
 if (numStoresInTransfers != 0) {
@@ -1050,6 +1051,15 @@
 }
 }

+// Process store conditionals or store release after all previous
+// stores are completed
+if (((!is_load && is_llsc) || is_release) &&
+!storeBuffer.isDrained()) {
+DPRINTF(MinorMem, "Memory access needs to wait for store buffer"
+  " to drain\n");
+return;
+}
+
 /* Check if this is the head instruction (and so must be executable as
  *  its stream sequence number was checked above) for loads which must
  *  not be speculatively issued and stores which must be issued here */

--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix store-release issuing

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27134 )



Change subject: cpu-o3: fix store-release issuing
..

cpu-o3: fix store-release issuing

Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück 
---
M src/cpu/o3/lsq_unit_impl.hh
1 file changed, 16 insertions(+), 1 deletion(-)



diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f7fb3fe..7383c6f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,6 +1,6 @@

 /*
- * Copyright (c) 2010-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2010-2014, 2017-2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -753,6 +753,21 @@

 DynInstPtr inst = storeWBIt->instruction();
 LSQRequest* req = storeWBIt->request();
+
+// Process store conditionals or store release after all previous
+// stores are completed
+if ((req->mainRequest()->isLLSC() ||
+ req->mainRequest()->isRelease()) &&
+ (storeWBIt.idx() != storeQueue.head())) {
+DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x "
+"[sn:%lli] is %s%s and not head of the queue\n",
+storeWBIt.idx(), inst->pcState(),
+req->request()->getPaddr(), inst->seqNum,
+req->mainRequest()->isLLSC() ? "SC" : "",
+req->mainRequest()->isRelease() ? "/Release" : "");
+break;
+}
+
 storeWBIt->committed() = true;

 assert(!inst->memData);

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Using acquire/release memory flags

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27133 )



Change subject: arch-arm: Using acquire/release memory flags
..

arch-arm: Using acquire/release memory flags

Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück 
---
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str.isa
M src/arch/arm/isa/insts/str64.isa
4 files changed, 12 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index dc1d650..d828fcf 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2019 ARM Limited
+// Copyright (c) 2010-2011,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 # Disambiguate the class name for different flavors of loads
 if self.flavor != "normal":
@@ -256,6 +257,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 def emit(self):
 # Address computation code
diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 4f12509..fc4f34f 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")
+
 if self.flavor in ("acex", "exclusive", "exp", "acexp"):
 self.memFlags.append("Request::LLSC")

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f542478..e99f6ad 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2017,2019 ARM Limited
+// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -190,6 +190,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
@@ -271,6 +272,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str64.isa  
b/src/arch/arm/isa/insts/str64.isa

index 22d1456..7ad1cad 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2013,2017,2019 ARM Limited
+// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -82,6 +82,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")
+
 if self.flavor in ("relex", "exclusive", "exp", "relexp"):
 self.instFlags.append("IsStoreConditional")
 self.memFlags.append("Request::LLSC")

--
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Gerrit-Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Gerrit-Change-Number: 27133
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück 
Gerrit-MessageType: 

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: MemDepUnit tracks load-acquire/store-release

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27132 )



Change subject: cpu-o3: MemDepUnit tracks load-acquire/store-release
..

cpu-o3: MemDepUnit tracks load-acquire/store-release

MemDepUnit tracks loads/stores that are also barriers, which is the case
of load-acquire / store-release instructions. The tracking logic is also
extended to consider multiple outstanding barriers.

Change-Id: I95b0c710d7c7e4a138492177e3eaaf5143e9a0ba
Signed-off-by: Tiago Mück 
---
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
2 files changed, 118 insertions(+), 73 deletions(-)



diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index c4a3310..54d2363 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2014 ARM Limited
+ * Copyright (c) 2012, 2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "base/statistics.hh"
 #include "cpu/inst_seq.hh"
@@ -177,7 +178,7 @@
   public:
 /** Constructs a memory dependence entry. */
 MemDepEntry(const DynInstPtr _inst)
-: inst(new_inst), regsReady(false), memDepReady(false),
+: inst(new_inst), regsReady(false), memDeps(0),
   completed(false), squashed(false)
 {
 #ifdef DEBUG
@@ -216,8 +217,8 @@

 /** If the registers are ready or not. */
 bool regsReady;
-/** If all memory dependencies have been satisfied. */
-bool memDepReady;
+/** Number of memory dependencies that need to be satisfied. */
+int memDeps;
 /** If the instruction is completed. */
 bool completed;
 /** If the instruction is squashed. */
@@ -257,14 +258,22 @@
  */
 MemDepPred depPred;

+/** Sequence numbers of outstanding load barriers. */
+std::unordered_set loadBarrierSNs;
+
+/** Sequence numbers of outstanding store barriers. */
+std::unordered_set storeBarrierSNs;
+
 /** Is there an outstanding load barrier that loads must wait on. */
-bool loadBarrier;
-/** The sequence number of the load barrier. */
-InstSeqNum loadBarrierSN;
+bool loadBarrier() { return loadBarrierSNs.size() != 0; }
+
 /** Is there an outstanding store barrier that loads must wait on. */
-bool storeBarrier;
-/** The sequence number of the store barrier. */
-InstSeqNum storeBarrierSN;
+bool storeBarrier() { return storeBarrierSNs.size() != 0; }
+
+void _insertBarrier(const DynInstPtr _inst);
+
+void _completeBarrier(const DynInstPtr );
+

 /** Pointer to the IQ. */
 InstructionQueue *iqPtr;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh  
b/src/cpu/o3/mem_dep_unit_impl.hh

index c712965..6fa1607 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2014 ARM Limited
+ * Copyright (c) 2012, 2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
 #define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__

 #include 
+#include 

 #include "cpu/o3/inst_queue.hh"
 #include "cpu/o3/mem_dep_unit.hh"
@@ -50,8 +51,7 @@

 template 
 MemDepUnit::MemDepUnit()
-: loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
-  storeBarrierSN(0), iqPtr(NULL)
+: iqPtr(NULL)
 {
 }

@@ -60,8 +60,7 @@
 : _name(params->name + ".memdepunit"),
   depPred(params->store_set_clear_period, params->SSITSize,
   params->LFSTSize),
-  loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
-  storeBarrierSN(0), iqPtr(NULL)
+  iqPtr(NULL)
 {
 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
 }
@@ -155,8 +154,8 @@
 MemDepUnit::takeOverFrom()
 {
 // Be sure to reset all state.
-loadBarrier = storeBarrier = false;
-loadBarrierSN = storeBarrierSN = 0;
+loadBarrierSNs.clear();
+storeBarrierSNs.clear();
 depPred.clear();
 }

@@ -169,6 +168,48 @@

 template 
 void
+MemDepUnit::_insertBarrier(const DynInstPtr _inst)
+{
+InstSeqNum barr_sn = barr_inst->seqNum;
+// Memory barriers block loads and stores, write barriers only stores.
+if (barr_inst->isMemBarrier()) {
+loadBarrierSNs.insert(barr_sn);
+storeBarrierSNs.insert(barr_sn);
+DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
+barr_inst->pcState(),barr_sn);
+} else if (barr_inst->isWriteBarrier()) {
+storeBarrierSNs.insert(barr_sn);
+DPRINTF(MemDepUnit, "Inserted a write barrier %s SN:%lli\n",
+barr_inst->pcState(),barr_sn);
+}
+if (loadBarrierSNs.size() || storeBarrierSNs.size())
+DPRINTF(MemDepUnit, "Outstanding load barriers = 

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Don't use args and kwargs on attachIO

2020-03-26 Thread Giacomo Travaglini (Gerrit)
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27086 )


Change subject: dev-arm: Don't use args and kwargs on attachIO
..

dev-arm: Don't use args and kwargs on attachIO

This is matching the attachOnChipIO style, and fixing the error of the
dma_ports kwarg being forwarded to the _attach_mem

Change-Id: Ib3ecf2fc18c488d938bbbf63eab3d7693cdb7d06
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27086
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Ciro Santilli 
---
M src/dev/arm/RealView.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Ciro Santilli: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index f9b9cb2..43d2b15 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -625,9 +625,9 @@
 if bridge:
 bridge.ranges = self._off_chip_ranges

-def attachIO(self, *args, **kwargs):
-self._attach_mem(self._off_chip_memory(), *args, **kwargs)
-self._attach_io(self._off_chip_devices(), *args, **kwargs)
+def attachIO(self, bus, dma_ports=None, mem_ports=None):
+self._attach_mem(self._off_chip_memory(), bus, mem_ports)
+self._attach_io(self._off_chip_devices(), bus, dma_ports)

 def setupBootLoader(self, cur_sys, boot_loader, atags_addr,  
load_offset):

 cur_sys.workload.boot_loader = boot_loader

--
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Gerrit-Change-Id: Ib3ecf2fc18c488d938bbbf63eab3d7693cdb7d06
Gerrit-Change-Number: 27086
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
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Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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Re: [gem5-dev] maintainership of scons and util

2020-03-26 Thread Jason Lowe-Power
Sounds good to me.

Cheers,
Jason

On Thu, Mar 26, 2020 at 4:31 AM Gabe Black  wrote:

> Hi folks. I've been doing enough work particularly on scons and to a lesser
> extent in some areas of util, two areas that are currently unclaimed in
> MAINTAINERS, so I thought it might make sense for me to volunteer for those
> slots.
>
> Is that ok with everyone?
>
> Gabe
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[gem5-dev] Change in gem5/gem5[develop]: scons: Get rid of a redundant "Warning:" in the SConstruct.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27127

to review the following change.


Change subject: scons: Get rid of a redundant "Warning:" in the SConstruct.
..

scons: Get rid of a redundant "Warning:" in the SConstruct.

The "warning()" method already prints "Warning:", so putting it in the
message itself means it gets printed twice.

Change-Id: Ic157355958fdf56739f865a926ecba071bb25c5e
---
M SConstruct
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/SConstruct b/SConstruct
index f5eb0ca..8d5ac57 100755
--- a/SConstruct
+++ b/SConstruct
@@ -425,9 +425,9 @@
 disable_lto = GetOption('no_lto')
 if not disable_lto and main.get('BROKEN_INCREMENTAL_LTO', False) and \
 not GetOption('force_lto'):
-warning('Warning: Your compiler doesn\'t support incremental  
linking '
-'and lto at the same time, so lto is being disabled. To  
force '
-'lto on anyway, use the --force-lto option. That will  
disable '
+warning('Your compiler doesn\'t support incremental linking and  
lto '
+'at the same time, so lto is being disabled. To force lto  
on '

+'anyway, use the --force-lto option. That will disable '
 'partial linking.')
 disable_lto = True


--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use the scons environment when marshalling.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27123

to review the following change.


Change subject: scons: Use the scons environment when marshalling.
..

scons: Use the scons environment when marshalling.

scons maintains an environment (in the shell sense) in the ENV
construction variable for use when running external programs. When we
run the "marshal" program which gathers up python objects to embed in
the gem5 binary, it's run by subprocess instead of through scons, and it
uses its own environment inherited from the host system.

Instead, this change makes the subprocess function use the scons
environment when calling "marshal". This ensures the environment is
consistent between this command and other commands scons runs.

This is usually not very important, but some tools like asan take
options set through the environment, and they may need to be adjusted
sometimes.

Change-Id: I671b447657ed8fad45fac7393cc1c09073bf3d3a
---
M src/SConscript
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/SConscript b/src/SConscript
index 2cdf6cb..ed7e1ea 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1166,7 +1166,8 @@

 import subprocess

-marshalled = subprocess.check_output([source[0].abspath,  
str(source[1])])

+marshalled = subprocess.check_output(
+[source[0].abspath, str(source[1])], env=env['ENV'])

 compressed = zlib.compress(marshalled)
 data = compressed

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Call summarize_warnings() when scons finishes building.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27130

to review the following change.


Change subject: scons: Call summarize_warnings() when scons finishes  
building.

..

scons: Call summarize_warnings() when scons finishes building.

This will ensure that warnings are not all shoved off the end of the
scrollback buffer or lost in a sea of compiler lines, and that the user
will actually have a chance to see and read them.

Change-Id: I7129560482ebca903ec597f8b1cf8a9a84d98c9c
---
M SConstruct
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/SConstruct b/SConstruct
index 8d5ac57..0f36eac 100755
--- a/SConstruct
+++ b/SConstruct
@@ -78,6 +78,7 @@
 from __future__ import print_function

 # Global Python includes
+import atexit
 import itertools
 import os
 import re
@@ -1274,3 +1275,5 @@

 %(local_vars)s
 ''' % help_texts)
+
+atexit.register(summarize_warnings)

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Add a mechanism to accumulate warnings to reprint at the end.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27129

to review the following change.


Change subject: scons: Add a mechanism to accumulate warnings to reprint at  
the end.

..

scons: Add a mechanism to accumulate warnings to reprint at the end.

When building gem5, it's possible for warnings printed early in the
build to be quickly wisked away in a see of compile lines, never to be
seen again (or driven off the end of the scrollback buffer).

To avoid those messages getting lost or ignored, this change adds a
mechanism to aggregate them into a list so that they can be summarized
at the end of the build, successful or not.

Change-Id: Ie13320717698fcbcd3a8f8d1c062467e8d6d2914
---
M site_scons/gem5_scons/__init__.py
1 file changed, 16 insertions(+), 3 deletions(-)



diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index e7e7a0a..169e0fe 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -169,12 +169,25 @@
 # Finally add the prefix and padding on extra lines, and glue it all  
back

 # together.
 message = prefix + ('\n' + padding).join(wrapped_lines)
-# Print the message in bold in the requested color.
-print(color + termcap.Bold + message + termcap.Normal, **kwargs)
+# Add in terminal escape sequences.
+message = color + termcap.Bold + message + termcap.Normal
+# Actually print the message.
+print(message, **kwargs)
+return message
+
+all_warnings = []
+def summarize_warnings():
+if not all_warnings:
+return
+print(termcap.Yellow + termcap.Bold +
+'*** Summary of Warnings ***' +
+termcap.Normal)
+list(map(print, all_warnings))

 def warning(*args, **kwargs):
 message = ' '.join(args)
-print_message('Warning: ', termcap.Yellow, message, **kwargs)
+printed = print_message('Warning: ', termcap.Yellow, message, **kwargs)
+all_warnings.append(printed)

 def error(*args, **kwargs):
 message = ' '.join(args)

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Enable LTO and partial linking with gcc >= 8.1.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27131

to review the following change.


Change subject: scons: Enable LTO and partial linking with gcc >= 8.1.
..

scons: Enable LTO and partial linking with gcc >= 8.1.

The bug(s) which prevented LTO and partial linking from working with gcc
have been fixed in my local version (9.3), and according to one of the
original bug reports:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69866

A fix was committed in gcc version 8.1.

The original code left in the SConstruct describing the problem with
versions greated than 6.0 also enabled an -flinker-output option and set
it to "rel". That option doesn't show up in the gcc 8.4 documentation
even though it was added in 6.0, but in the 9.3 documentation it
describes it and says that it defaults to "rel" when the -r (partial
linking) option is used.

This *should* mean that LTO and partial linking can be used together
with no issues after version 8.1, and at most by version 9.3. If someone
finds that that isn't true, then the range of bad versions can be
expanded.

Change-Id: Ie0529d077a0042ef55e2af995d01430d1695c031
---
M SConstruct
1 file changed, 8 insertions(+), 13 deletions(-)



diff --git a/SConstruct b/SConstruct
index 0f36eac..c8d1428 100755
--- a/SConstruct
+++ b/SConstruct
@@ -169,7 +169,7 @@
 AddLocalOption('--with-systemc-tests', dest='with_systemc_tests',
action='store_true', help='Build systemc tests')

-from gem5_scons import Transform, error, warning
+from gem5_scons import Transform, error, warning, summarize_warnings

 if GetOption('no_lto') and GetOption('force_lto'):
 error('--no-lto and --force-lto are mutually exclusive')
@@ -401,27 +401,22 @@

 main['GCC_VERSION'] = gcc_version

-if compareVersions(gcc_version, '4.9') >= 0:
+if compareVersions(gcc_version, '4.9') >= 0 and \
+   compareVersions(gcc_version, '8.1') < 0:
 # Incremental linking with LTO is currently broken in gcc versions
-# 4.9 and above. A version where everything works completely hasn't
-# yet been identified.
+# 4.9 to 8.1.
 #
 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67548
-main['BROKEN_INCREMENTAL_LTO'] = True
-if compareVersions(gcc_version, '6.0') >= 0:
+#
 # gcc versions 6.0 and greater accept an -flinker-output flag which
 # selects what type of output the linker should generate. This is
 # necessary for incremental lto to work, but is also broken in
-# current versions of gcc. It may not be necessary in future
-# versions. We add it here since it might be, and as a reminder  
that

-# it exists. It's excluded if lto is being forced.
+# versions of gcc up to 8.1.
 #
 # https://gcc.gnu.org/gcc-6/changes.html
 # https://gcc.gnu.org/ml/gcc-patches/2015-11/msg03161.html
 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69866
-if not GetOption('force_lto'):
-main.Append(PSHLINKFLAGS='-flinker-output=rel')
-main.Append(PLINKFLAGS='-flinker-output=rel')
+main['BROKEN_INCREMENTAL_LTO'] = True

 disable_lto = GetOption('no_lto')
 if not disable_lto and main.get('BROKEN_INCREMENTAL_LTO', False) and \
@@ -430,7 +425,7 @@
 'at the same time, so lto is being disabled. To force lto  
on '

 'anyway, use the --force-lto option. That will disable '
 'partial linking.')
-disable_lto = True
+#disable_lto = True

 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off. Note that these flags

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use the textwrap module to wrap warnings/errors neatly.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27128

to review the following change.


Change subject: scons: Use the textwrap module to wrap warnings/errors  
neatly.

..

scons: Use the textwrap module to wrap warnings/errors neatly.

Otherwise the error and warning messages get chopped off and wrapped by
the terminal wherever they happened to end. That's ugly and hard to
read.

This mechanism attempts to wrap the text using the console width which
it attempts to determine in two ways, first with shutil which should
work in python 3.3 and above, and then with the curses python module. If
neither of those works, it just falls back to 80 columns which is not
ideal but is reasonable.

Change-Id: I961936295505f93f5f36eb6d9cebc5073b5f793b
---
M site_scons/gem5_scons/__init__.py
1 file changed, 41 insertions(+), 1 deletion(-)



diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index 16bb753..e7e7a0a 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -41,6 +41,7 @@
 from __future__ import print_function

 import os
+import textwrap

 from gem5_scons.util import get_termcap
 import SCons.Script
@@ -127,9 +128,48 @@
 return ', '.join(f)
 return self.format % (com_pfx, fmt(srcs), fmt(tgts))

+# The width warning and error messages should be wrapped at.
+text_width = None
+
+# This should work in python 3.3 and above.
+if text_width is None:
+try:
+import shutil
+text_width = shutil.get_terminal_size().columns
+except:
+pass
+
+# This should work if the curses python module is installed.
+if text_width is None:
+try:
+import curses
+try:
+_, text_width = curses.initscr().getmaxyx()
+finally:
+curses.endwin()
+except:
+pass
+
+# If all else fails, default to 80 columns.
+if text_width is None:
+text_width = 80
+
 def print_message(prefix, color, message, **kwargs):
+# Precompute some useful values.
+prefix_len = len(prefix)
+wrap_width = text_width - prefix_len
+padding = ' ' * prefix_len
+
+# First split on newlines.
 lines = message.split('\n')
-message = prefix + ('\n' + ' ' * len(prefix)).join(lines)
+# Then wrap each line to the required width.
+wrapped_lines = []
+for line in lines:
+wrapped_lines.extend(textwrap.wrap(line, wrap_width))
+# Finally add the prefix and padding on extra lines, and glue it all  
back

+# together.
+message = prefix + ('\n' + padding).join(wrapped_lines)
+# Print the message in bold in the requested color.
 print(color + termcap.Bold + message + termcap.Normal, **kwargs)

 def warning(*args, **kwargs):

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Replace find_first_prog() with the built in Detect().

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27126

to review the following change.


Change subject: scons: Replace find_first_prog() with the built in Detect().
..

scons: Replace find_first_prog() with the built in Detect().

The built in environment method Detect() does the same thing, that is it
finds the first program available from a list of options.

Change-Id: I3763ae5cc9dd22ee322908c0a7a2c037dc91d5a5
---
M SConstruct
1 file changed, 1 insertion(+), 14 deletions(-)



diff --git a/SConstruct b/SConstruct
index 4273d14..f5eb0ca 100755
--- a/SConstruct
+++ b/SConstruct
@@ -214,19 +214,6 @@
 return [abspath(joinpath(root, expanduser(str(p
 for p in path_list]

-def find_first_prog(prog_names):
-"""Find the absolute path to the first existing binary in prog_names"""
-
-if not isinstance(prog_names, (list, tuple)):
-prog_names = [ prog_names ]
-
-for p in prog_names:
-p = main.WhereIs(p)
-if p is not None:
-return p
-
-return None
-
 # Each target must have 'build' in the interior of the path; the
 # directory below this will determine the build parameters.  For
 # example, for target 'foo/bar/build/X86/arch/x86/blah.do' we
@@ -679,7 +666,7 @@
 # version of python, see above for instructions on how to invoke
 # scons with the appropriate PATH set.

-python_config = find_first_prog(main['PYTHON_CONFIG'])
+python_config = main.Detect(main['PYTHON_CONFIG'])
 if python_config is None:
 error("Can't find a suitable python-config, tried %s" % \
   main['PYTHON_CONFIG'])

--
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[gem5-dev] Change in gem5/gem5[develop]: util: Add a file to suppress spurious lsan leaks in the python lib.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27124

to review the following change.


Change subject: util: Add a file to suppress spurious lsan leaks in the  
python lib.

..

util: Add a file to suppress spurious lsan leaks in the python lib.

The python interpreter does some fancy things with memory which trips up
the lsan leak checker which comes along with asan. This file simply
tells lsan to ignore those leaks.

To use it when running a binary, set the LSAN_OPTIONS environment
variable to "suppressions=${PATH TO SUPPRESSIONS FILE}". To disable the
a report on the leaks that were suppressed, you should also set
"print_suppressions=0". Multiple options can be set by seperating them
with ":"s.

LSAN_OPTIONS=suppressions=util/lsan-suppressions:print_suppressions=0

Change-Id: Ie4d712c6b95f429e67361c41a9b545a8536f2511
---
A util/lsan-suppressions
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/util/lsan-suppressions b/util/lsan-suppressions
new file mode 100644
index 000..221370a
--- /dev/null
+++ b/util/lsan-suppressions
@@ -0,0 +1,2 @@
+# Suppress detection of leaks from within the python 2.7 interpreter.
+leak:libpython2.7.so

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use the lsan-suppressions file when running internal commands.

2020-03-26 Thread Gabe Black (Gerrit)

Hello Gabe Black,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27125

to review the following change.


Change subject: scons: Use the lsan-suppressions file when running internal  
commands.

..

scons: Use the lsan-suppressions file when running internal commands.

These commands (like the marshal binary) might otherwise fail with
spurious leaks detected in the python library.

Change-Id: I042c2a811d465ac03f005672f328c0fb0b594494
---
M SConstruct
1 file changed, 10 insertions(+), 0 deletions(-)



diff --git a/SConstruct b/SConstruct
index b93a000..4273d14 100755
--- a/SConstruct
+++ b/SConstruct
@@ -510,6 +510,16 @@
 # Available for gcc >= 4.8 or llvm >= 3.1 both a requirement
 # by the build system
 sanitizers.append('address')
+suppressions_file = Dir('util').File('lsan-suppressions').get_abspath()
+suppressions_opt = 'suppressions=%s' % suppressions_file
+main['ENV']['LSAN_OPTIONS'] = ':'.join([suppressions_opt,
+'print_suppressions=0'])
+print()
+warning('To suppress false positive leaks, set the LSAN_OPTIONS '
+'environment variable to "%s" when running gem5' %
+suppressions_opt)
+warning('LSAN_OPTIONS=suppressions=%s' % suppressions_opt)
+print()
 if sanitizers:
 sanitizers = ','.join(sanitizers)
 if main['GCC'] or main['CLANG']:

--
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[gem5-dev] maintainership of scons and util

2020-03-26 Thread Gabe Black
Hi folks. I've been doing enough work particularly on scons and to a lesser
extent in some areas of util, two areas that are currently unclaimed in
MAINTAINERS, so I thought it might make sense for me to volunteer for those
slots.

Is that ok with everyone?

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix undefined behavior in mask generation

2020-03-26 Thread Daniel Carvalho (Gerrit)
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27104 )



Change subject: base: Fix undefined behavior in mask generation
..

base: Fix undefined behavior in mask generation

When generating a mask, if the number of bits is greater than
the maximum shift distance (63), the shift will have undefined
behavior. Previously the branch was taking care of a single
trespassing case, and it has been fixed to cover the remaining.

Issue-on: https://gem5.atlassian.net/browse/GEM5-205

Change-Id: Ib5a00917c8d2b23ffdb710c2f9673d956cd9f43e
Signed-off-by: Daniel R. Carvalho 
---
M src/base/bitfield.hh
1 file changed, 5 insertions(+), 2 deletions(-)



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 9a252a4..c2ed72b 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -50,12 +50,15 @@
 extern const uint8_t reverseLookUpTable[];

 /**
- * Generate a 64-bit mask of 'nbits' 1s, right justified.
+ * Generate a 64-bit mask of 'nbits' 1s, right justified. If a number of  
bits

+ * greater than 64 is given, it is truncated to 64.
+ *
+ * @param nbits The number of bits set in the mask.
  */
 inline uint64_t
 mask(int nbits)
 {
-return (nbits == 64) ? (uint64_t)-1LL : (1ULL << nbits) - 1;
+return (nbits >= 64) ? (uint64_t)-1LL : (1ULL << nbits) - 1;
 }

 /**

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: LL/SC fixes

2020-03-26 Thread Giacomo Travaglini (Gerrit)

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27103

to review the following change.


Change subject: mem-ruby: LL/SC fixes
..

mem-ruby: LL/SC fixes

The implementation for load-linked/store-conditional did not work
correctly for multi-core simulations. Since load-links were treated as
stores, it was not possible for a line to have multiple readers which
often resulted in livelock when using these instructions to implemented
mutexes. This improved implementation treats load-linked instructions
similarly to loads, but places the associated line's address into a
monitor visible to all devices on a system. Writes to a monitored
address ensure the 'linked' property is blown away and any subsequent
store-conditional will fail.

This patch introduces a new RubyRequestType 'Store_Conditional_Failed'
which is a store conditional that has checked the address monitor
and confirmed that it has already failed. For Gem5/Ruby correctness,
this request still needs to go into and return from the mandatory
queue, i.e. the cache controller. As such, the various protocols will
need to recognise this new type--this patch updates MESI_Three_Level,
MESI_Two_Level and MOESI_hammer. Additionally, the transitions of
MESI_Three_Level-L0cache are updated so that line invalidations also
trigger an update to the address monitor.

Change-Id: I19bd74459e26732c92c8b594901936e6439fb073
---
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/MOESI_hammer-cache.sm
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
9 files changed, 333 insertions(+), 97 deletions(-)



diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm  
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm

index b74a727..f31c0df 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -121,6 +121,8 @@
 Ack,desc="Ack for processor";

 WB_Ack,desc="Ack for replacement";
+
+Failed_SC,desc="Store conditional request that will fail";
   }

   // TYPES
@@ -257,7 +259,8 @@
   return Event:Load;
 } else if (type == RubyRequestType:IFETCH) {
   return Event:Ifetch;
-} else if ((type == RubyRequestType:ST) || (type ==  
RubyRequestType:ATOMIC)) {
+} else if ((type == RubyRequestType:ST) || (type ==  
RubyRequestType:ATOMIC)

+   || (type == RubyRequestType:Store_Conditional)) {
   return Event:Store;
 } else {
   error("Invalid RubyRequestType");
@@ -349,36 +352,48 @@
 }
   }
 } else {
-
   // *** DATA ACCESS ***
   Entry Dcache_entry := getDCacheEntry(in_msg.LineAddress);
+
+  // early out for failed store conditionals
+  if (in_msg.Type == RubyRequestType:Store_Conditional_Failed) {
+  trigger(Event:Failed_SC, in_msg.LineAddress,
+  Dcache_entry, TBEs[in_msg.LineAddress]);
+  }
+
   if (is_valid(Dcache_entry)) {
 // The tag matches for the L0, so the L0 ask the L1 for it
 trigger(mandatory_request_type_to_event(in_msg.Type),  
in_msg.LineAddress,

 Dcache_entry, TBEs[in_msg.LineAddress]);
   } else {
-
-// Check to see if it is in the OTHER L0
-Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
-if (is_valid(Icache_entry)) {
-  // The block is in the wrong L0, put the request on the  
queue to the private L1

-  trigger(Event:L0_Replacement, in_msg.LineAddress,
-  Icache_entry, TBEs[in_msg.LineAddress]);
-}
-
-if (Dcache.cacheAvail(in_msg.LineAddress)) {
-  // L1 does't have the line, but we have space for it
-  // in the L0 let's see if the L1 has it
-  trigger(mandatory_request_type_to_event(in_msg.Type),  
in_msg.LineAddress,

-  Dcache_entry, TBEs[in_msg.LineAddress]);
+// if the request is not valid, the store conditional will fail
+if (in_msg.Type == RubyRequestType:Store_Conditional) {
+// if the line is not valid, it can't be locked
+trigger(Event:Failed_SC, in_msg.LineAddress,
+Dcache_entry, TBEs[in_msg.LineAddress]);
 } else {
-  // No room in the L1, so we need to make room in the L0
-  // Check if the line we want to evict is not locked
-  Addr addr := Dcache.cacheProbe(in_msg.LineAddress);
-  check_on_cache_probe(mandatoryQueue_in, addr);
-  

[gem5-dev] Change in gem5/gem5[develop]: arm: Return whether a semihosting call was recognized/handled.

2020-03-26 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25949 )


Change subject: arm: Return whether a semihosting call was  
recognized/handled.

..

arm: Return whether a semihosting call was recognized/handled.

Otherwise there's no way to determine whether the return value was from
the semihosting mechanism itself, or from one of the calls. There would
also be no way to determine whether a call had actually happened.

Change-Id: Ie2da812172fe2f9c1e2b5be95561863bd12920b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25949
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
4 files changed, 18 insertions(+), 14 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index b6db38a..230ded1 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -153,21 +153,21 @@
tickShift);
 }

-void
+bool
 ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
 {
 RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32));
 if (op > MaxStandardOp && !gem5_ops) {
 unrecognizedCall(
 tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
-return;
+return false;
 }

 auto it = calls.find(op);
 if (it == calls.end()) {
 unrecognizedCall(
 tc, "Unknown aarch64 semihosting call: op = 0x%x", op);
-return;
+return false;
 }
 const SemiCall  = it->second;

@@ -175,23 +175,25 @@
 auto err = call.call64(this, tc);
 semiErrno = err.second;
 DPRINTF(Semihosting, "\t ->: 0x%x, %i\n", err.first, err.second);
+
+return true;
 }

-void
+bool
 ArmSemihosting::call32(ThreadContext *tc, bool gem5_ops)
 {
 RegVal op = tc->readIntReg(ArmISA::INTREG_R0);
 if (op > MaxStandardOp && !gem5_ops) {
 unrecognizedCall(
 tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
-return;
+return false;
 }

 auto it = calls.find(op);
 if (it == calls.end()) {
 unrecognizedCall(
 tc, "Unknown aarch32 semihosting call: op = 0x%x", op);
-return;
+return false;
 }
 const SemiCall  = it->second;

@@ -199,6 +201,8 @@
 auto err = call.call32(this, tc);
 semiErrno = err.second;
 DPRINTF(Semihosting, "\t ->: 0x%x, %i\n", err.first, err.second);
+
+return true;
 }

 void
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 9aa5b41..5884349 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -214,9 +214,9 @@
 ArmSemihosting(const ArmSemihostingParams *p);

 /** Perform an Arm Semihosting call from aarch64 code. */
-void call64(ThreadContext *tc, bool gem5_ops);
+bool call64(ThreadContext *tc, bool gem5_ops);
 /** Perform an Arm Semihosting call from aarch32 code. */
-void call32(ThreadContext *tc, bool gem5_ops);
+bool call32(ThreadContext *tc, bool gem5_ops);

   public: // SimObject and related interfaces
 void serialize(CheckpointOut ) const override;
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index e61402a..5d8808c 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -179,16 +179,16 @@
 return FullSystem && getArmSystem(tc)->haveSemihosting();
 }

-void
+bool
 ArmSystem::callSemihosting64(ThreadContext *tc, bool gem5_ops)
 {
-getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
+return getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
 }

-void
+bool
 ArmSystem::callSemihosting32(ThreadContext *tc, bool gem5_ops)
 {
-getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
+return getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
 }

 void
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index fc32d0f..370a3df 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -314,10 +314,10 @@
 static bool haveSemihosting(ThreadContext *tc);

 /** Make a Semihosting call from aarch64 */
-static void callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
+static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);

 /** Make a Semihosting call from aarch32 */
-static void callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
+static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);

 /** Make a call to notify the power controller of STANDBYWFI assertion  
*/

 static void callSetStandByWfi(ThreadContext *tc);

--
To view, visit 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: print information about faults.

2020-03-26 Thread Nils Asmussen (Gerrit)
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25646 )


Change subject: arch-riscv: print information about faults.
..

arch-riscv: print information about faults.

Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25646
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/faults.cc
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 1d48d85..2296992 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -2,6 +2,7 @@
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
  * Copyright (c) 2018 TU Dresden
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,6 +37,7 @@
 #include "arch/riscv/utility.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Fault.hh"
 #include "sim/debug.hh"
 #include "sim/full_system.hh"

@@ -53,6 +55,9 @@
 {
 PCState pcState = tc->pcState();

+DPRINTFS(Fault, tc->getCpuPtr(), "Fault (%s) at PC: %s\n",
+ name(), pcState);
+
 if (FullSystem) {
 PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
 PrivilegeMode prv = PRV_M;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25646
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
Gerrit-Change-Number: 25646
Gerrit-PatchSet: 7
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.

2020-03-26 Thread Nils Asmussen (Gerrit)
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25645 )


Change subject: arch-riscv: added support for pseudo instructions.
..

arch-riscv: added support for pseudo instructions.

Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25645
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
A src/arch/riscv/insts/pseudo.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/formats.isa
A src/arch/riscv/isa/formats/m5ops.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/operands.isa
M src/arch/riscv/utility.hh
8 files changed, 126 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh
new file mode 100644
index 000..47b11ad
--- /dev/null
+++ b/src/arch/riscv/insts/pseudo.hh
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_INSTS_PSEUDO_HH__
+#define __ARCH_RISCV_INSTS_PSEUDO_HH__
+
+#include 
+
+#include "arch/riscv/insts/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class PseudoOp : public RiscvStaticInst
+{
+  protected:
+using RiscvStaticInst::RiscvStaticInst;
+
+std::string generateDisassembly(
+Addr pc, const SymbolTable *symtab) const override
+{
+return mnemonic;
+}
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/bitfields.isa  
b/src/arch/riscv/isa/bitfields.isa

index dae7fe1..e32c82d 100644
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -119,3 +120,6 @@
 def bitfield CIMM3 <12:10>;
 def bitfield CIMM2 <6:5>;
 def bitfield CIMM1 <12>;
+
+// Pseudo instructions
+def bitfield M5FUNC <31:25>;
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 63cf1e4..4f8fea2 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -1832,5 +1833,7 @@
 }}, IsNonSpeculative, No_OpClass);
 }
 }
+
+0x1e: M5Op::M5Op();
 }
 }
diff --git a/src/arch/riscv/isa/formats/formats.isa  
b/src/arch/riscv/isa/formats/formats.isa

index 0f7dc42..2a6b910 100644
--- a/src/arch/riscv/isa/formats/formats.isa
+++ b/src/arch/riscv/isa/formats/formats.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or 

[gem5-dev] Change in gem5/gem5[develop]: arch, sim: Return whether or not a pseudo inst was recognized.

2020-03-26 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25948 )


Change subject: arch,sim: Return whether or not a pseudo inst was  
recognized.

..

arch,sim: Return whether or not a pseudo inst was recognized.

Otherwise there's no way to distinguish whether return values are from
the calls themselves, including what they mean in the context (success
or failure?) or the pseudo inst dispatch function itself.

Change-Id: I3e71c277f175c69af0d1adeb3299d88d095dfa84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25948
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Alexandru Duțu 
---
M src/arch/arm/tlb.cc
M src/arch/x86/tlb.cc
M src/sim/pseudo_inst.hh
3 files changed, 42 insertions(+), 34 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Alexandru Duțu: Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5a92a0c..84160bb 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -141,7 +141,8 @@
 req->setLocalAccessor(
 [func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
 {
-uint64_t ret = PseudoInst::pseudoInst(tc,  
func);

+uint64_t ret;
+PseudoInst::pseudoInst(tc, func, ret);
 if (mode == Read)
 pkt->setLE(ret);
 return Cycles(1);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 46bab48..53492b0 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -265,8 +265,8 @@
 req->setLocalAccessor(
 [func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
 {
-uint64_t ret =
-PseudoInst::pseudoInst(tc, func);
+uint64_t ret;
+PseudoInst::pseudoInst(tc, func, ret);
 if (mode == Read)
 pkt->setLE(ret);
 return Cycles(1);
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index fbf997a..be9e5bb 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -130,100 +130,109 @@
  * manner using the ISA-specific getArguments functions.
  *
  * @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
+ * @param result A reference to a uint64_t to store a result in.
+ * @return Whether the pseudo instruction was recognized/handled.
  */

 template 
-uint64_t
-pseudoInst(ThreadContext *tc, uint8_t func)
+bool
+pseudoInst(ThreadContext *tc, uint8_t func, uint64_t )
 {
 DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);

+result = 0;
+
 switch (func) {
   case M5OP_ARM:
 invokeSimcall(tc, arm);
-break;
+return true;

   case M5OP_QUIESCE:
 invokeSimcall(tc, quiesce);
-break;
+return true;

   case M5OP_QUIESCE_NS:
 invokeSimcall(tc, quiesceNs);
-break;
+return true;

   case M5OP_QUIESCE_CYCLE:
 invokeSimcall(tc, quiesceCycles);
-break;
+return true;

   case M5OP_QUIESCE_TIME:
-return invokeSimcall(tc, quiesceTime);
+result = invokeSimcall(tc, quiesceTime);
+return true;

   case M5OP_RPNS:
-return invokeSimcall(tc, rpns);
+result = invokeSimcall(tc, rpns);
+return true;

   case M5OP_WAKE_CPU:
 invokeSimcall(tc, wakeCPU);
-break;
+return true;

   case M5OP_EXIT:
 invokeSimcall(tc, m5exit);
-break;
+return true;

   case M5OP_FAIL:
 invokeSimcall(tc, m5fail);
-break;
+return true;

   case M5OP_INIT_PARAM:
-return invokeSimcall(tc, initParam);
+result = invokeSimcall(tc, initParam);
+return true;

   case M5OP_LOAD_SYMBOL:
 invokeSimcall(tc, loadsymbol);
-break;
+return true;

   case M5OP_RESET_STATS:
 invokeSimcall(tc, resetstats);
-break;
+return true;

   case M5OP_DUMP_STATS:
 invokeSimcall(tc, dumpstats);
-break;
+return true;

   case M5OP_DUMP_RESET_STATS:
 invokeSimcall(tc, dumpresetstats);
-break;
+return true;

   case M5OP_CHECKPOINT:
 invokeSimcall(tc, m5checkpoint);
-break;
+return true;

   case M5OP_WRITE_FILE:
-return invokeSimcall(tc, writefile);
+result = invokeSimcall(tc, writefile);
+return true;

   case M5OP_READ_FILE:
-return invokeSimcall(tc, readfile);
+result = invokeSimcall(tc, readfile);
+return true;

   case M5OP_DEBUG_BREAK: