[gem5-dev] Re: Issues when try to mount full-system image files

2023-12-22 Thread Jason Lowe-Power via gem5-dev
Here's the answer from the gem5-GPT bot (
https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt, if you have chatGPT plus):

The error message you're encountering indicates a problem with mounting the
filesystem from the `ubuntu-18.04-arm64-docker.img` image. This can be due
to several reasons such as an incorrect offset value, filesystem
corruption, or a mismatch between the filesystem type and the tools
available on your system. Here's a step-by-step approach to troubleshoot
and resolve this issue:

1. **Verify the Filesystem Type and Integrity:**
   - First, ensure that the image file is not corrupted. You can use
`sha256sum` or a similar tool to verify the integrity of the downloaded
image against the checksum provided on the gem5 guest binaries page.
   - Determine the filesystem type of the image. You can use the `file`
command to check the type of filesystem contained within the image. For
example: `file ubuntu-18.04-arm64-docker.img`.

2. **Check the Offset:**
   - The offset you've specified (`32256`) might be incorrect for the
image. The correct offset depends on how the image was created. You can use
`fdisk -l ubuntu-18.04-arm64-docker.img` to list the partitions within the
image and calculate the correct offset. The offset is typically the start
sector of the partition multiplied by the sector size (usually 512 bytes).

3. **Ensure Necessary Filesystem Support:**
   - Make sure your system supports the filesystem type used in the image.
For instance, if it's an ext4 filesystem, your system should have support
for mounting ext4 partitions.
   - If the filesystem is not natively supported by your Linux
distribution, you may need to install additional packages.

4. **Mounting the Image:**
   - Once you have the correct offset and ensured filesystem support, try
mounting the image again with the updated offset. Ensure that the mount
point (`./mnt`) exists and you have the necessary permissions to mount
there.

5. **Using `losetup`:**
   - Alternatively, you can use `losetup` to associate the image with a
loop device, specifying the correct offset, and then mount the loop device
instead of directly mounting the image file. This can sometimes be more
reliable.

6. **Checking for Additional Errors:**
   - If the issue persists, examine `dmesg` for any kernel messages that
might indicate why the mount operation is failing.

7. **Seeking Further Assistance:**
   - If you continue to face issues, consider reaching out to gem5
communities or forums with detailed information about the steps you've
taken and the specific errors encountered.

Remember to handle filesystem operations with care, especially when
mounting image files, to avoid data corruption. If you're not familiar with
these operations, it's a good idea to create backups of important data
before proceeding.

On Thu, Dec 21, 2023 at 9:45 PM sun2k23 via gem5-dev 
wrote:

> Hello,
>
> I'm trying to moving host files to full-system image files which is
> the ubuntu-18.04-arm64-docker.img, but encountered below error information
> in my linux terminal:  $: mount: /mnt: wrong fs type, bad option, bad
> superblock on /dev/loop1, missing codepage or helper program, or other
> error.
>
>It's pretty appreciated if anyone provide some comments or feedbacks on
> this issue.
>
>My terminal command is as below:  $: sudo mount -o loop,offset=32256
> ./ubuntu-18.04-arm64-docker.img ./mnt
>The ubuntu-18.04-arm64-docker.img is downloaded via gem5 guest binaries
> link.
>
>Best regards,
>
> Sun2K
>
>
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[gem5-dev] [NoOp] Change in gem5/gem5[develop]: configs: Fix SPEC benchmarks example scripts

2023-07-10 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71738?usp=email )


Change subject: configs: Fix SPEC benchmarks example scripts
..

configs: Fix SPEC benchmarks example scripts

This small change fixes the gem5_library example
scripts for SPEC benchmarks to make them compatible
with the latest version of the std library.

Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71738
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
0 files changed, 0 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass





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[gem5-dev] Re: Build failed in Jenkins: nightly #659

2023-07-07 Thread Jason Lowe-Power via gem5-dev
This looks like a random failure to me. This happens on jenkins once every
week or two. It might be better tomorrow. Unfortunately, this failure gives
us no information.

On Fri, Jul 7, 2023 at 8:29 AM Matt Sinclair via gem5-dev 
wrote:

> Hi Bobby,
>
> How do I read this output?  I wanted to check if Square was still passing,
> because of the patch Matt P pushed yesterday, but I don't seem to see it.
> I realize we are replacing this setup shortly, but nonetheless want to make
> sure bugs aren't slipping in.
>
> Thanks,
> Matt
>
> On Fri, Jul 7, 2023 at 9:14 AM jenkins-no-reply--- via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> See <
>> https://jenkins.gem5.org/job/nightly/659/display/redirect?page=changes>
>>
>> Changes:
>>
>> [Bobby R. Bruce] util: Update GitHub Runners Vagrant to overcommit memory
>>
>> [Bobby R. Bruce] util: '-eq' -> '-ge' for if in vm_manager.sh
>>
>> [Bobby R. Bruce] util: Add 'shutdown' argument option to vm_manager.sh
>>
>> [Bobby R. Bruce] util: Add 'swapspace' daemon to runner VM.
>>
>>
>> --
>> [...truncated 2.76 MB...]
>> Starting Test Suite:
>> test-replacement-policy-traces/second_chance_test1_ld-NULL-x86_64-opt-MI_example
>>
>> Starting Test Case:
>> test-replacement-policy-traces/second_chance_test1_ld-NULL-x86_64-opt-MI_example
>> Test:
>> test-replacement-policy-traces/second_chance_test1_ld-NULL-x86_64-opt-MI_example
>> Passed
>> Starting Test Case:
>> test-replacement-policy-traces/second_chance_test1_ld-NULL-x86_64-opt-MI_example-MatchStdoutNoPerf
>> Logging call to command: diff /tmp/gem5outfhfhbv7i/simout
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/ref/second_chance_test1_ld
>> Test:
>> test-replacement-policy-traces/second_chance_test1_ld-NULL-x86_64-opt-MI_example-MatchStdoutNoPerf
>> Passed
>> Logging call to command:
>> /nobackup/jenkins/workspace/nightly/build/NULL_MI_example/gem5.opt -d
>> /tmp/gem5outtvvim2dh -re --silent-redirect
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/run_replacement_policy.py
>> traces/second_chance_test2_ld
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/traces/second_chance_test2_ld.py
>> Starting Test Suite:
>> test-replacement-policy-traces/second_chance_test2_ld-NULL-x86_64-opt-MI_example
>>
>> Starting Test Case:
>> test-replacement-policy-traces/second_chance_test2_ld-NULL-x86_64-opt-MI_example
>> Test:
>> test-replacement-policy-traces/second_chance_test2_ld-NULL-x86_64-opt-MI_example
>> Passed
>> Starting Test Case:
>> test-replacement-policy-traces/second_chance_test2_ld-NULL-x86_64-opt-MI_example-MatchStdoutNoPerf
>> Logging call to command: diff /tmp/gem5outtvvim2dh/simout
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/ref/second_chance_test2_ld
>> Test:
>> test-replacement-policy-traces/second_chance_test2_ld-NULL-x86_64-opt-MI_example-MatchStdoutNoPerf
>> Passed
>> Logging call to command:
>> /nobackup/jenkins/workspace/nightly/build/NULL_MI_example/gem5.opt -d
>> /tmp/gem5outqn5wz59b -re --silent-redirect
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/run_replacement_policy.py
>> traces/second_chance_test3_ld
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/traces/second_chance_test3_ld.py
>> Starting Test Suite:
>> test-replacement-policy-traces/second_chance_test3_ld-NULL-x86_64-opt-MI_example
>>
>> Starting Test Case:
>> test-replacement-policy-traces/second_chance_test3_ld-NULL-x86_64-opt-MI_example
>> Test:
>> test-replacement-policy-traces/second_chance_test3_ld-NULL-x86_64-opt-MI_example
>> Passed
>> Starting Test Case:
>> test-replacement-policy-traces/second_chance_test3_ld-NULL-x86_64-opt-MI_example-MatchStdoutNoPerf
>> Logging call to command: diff /tmp/gem5outqn5wz59b/simout
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/ref/second_chance_test3_ld
>> Test:
>> test-replacement-policy-traces/second_chance_test3_ld-NULL-x86_64-opt-MI_example-MatchStdoutNoPerf
>> Passed
>> Logging call to command:
>> /nobackup/jenkins/workspace/nightly/build/NULL_MI_example/gem5.opt -d
>> /tmp/gem5out6it56ldp -re --silent-redirect
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/run_replacement_policy.py
>> traces/tree_plru_test1_ld
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/traces/tree_plru_test1_ld.py
>> Starting Test Suite:
>> test-replacement-policy-traces/tree_plru_test1_ld-NULL-x86_64-opt-MI_example
>>
>> Starting Test Case:
>> test-replacement-policy-traces/tree_plru_test1_ld-NULL-x86_64-opt-MI_example
>> Test:
>> test-replacement-policy-traces/tree_plru_test1_ld-NULL-x86_64-opt-MI_example
>> Passed
>> Starting Test Case:
>> test-replacement-policy-traces/tree_plru_test1_ld-NULL-x86_64-opt-MI_example-MatchStdoutNoPerf
>> Logging call to command: diff /tmp/gem5out6it56ldp/simout
>> /nobackup/jenkins/workspace/nightly/tests/gem5/replacement-policies/ref/tree_plru_test1

[gem5-dev] [M] Change in gem5/gem5[release-staging-v23-0]: misc: Add release notes for v23.0

2023-06-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71758?usp=email )



Change subject: misc: Add release notes for v23.0
..

misc: Add release notes for v23.0

Change-Id: I003f170339e69a445586fe0486a1db595a10683f
Signed-off-by: Jason Lowe-Power 
---
M RELEASE-NOTES.md
1 file changed, 96 insertions(+), 0 deletions(-)



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 931be69..5d55976 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -1,3 +1,99 @@
+# Version 23.0
+
+This release has approximately 500 contributions from 50 unique  
contributors.

+This release incorporates ...
+
+The big news in this release is gem5's migration from Gerrit (at  
gem5.googlesource.com) to GitHub (at github.com/gem5/).
+From now on, please issue *pull requests* to GitHub instead of change  
requests on Gerrit.

+Gerrit will be available in read-only mode to access prior conversations.
+
+## Significant API and user-facing changes
+
+### Major renaming of CPU stats
+
+The CPU stats have been renamed.
+See <https://gem5.atlassian.net/browse/GEM5-1304> for details.
+
+Now, each stage (fetch, execute, commit) have their own stat group.
+Stats that are shared between the different CPU model (O3, Minor, Simple)  
now have the exact same names.

+
+**Important:** Some stat names were misleading before this change.
+With this change, stats with the same names between different CPU models  
have the same meaning.

+
+### `fs.py` and `se.py` deprecated
+
+These scripts have not been well supported for many gem5 releases.
+With gem5 23.0, we have officially deprecated these scripts.
+They have been moved into the `deprecated` directory, **but they will be  
removed in a future release.**

+As a replacement, we strongly suggest using the gem5 standard library.
+
+### Other API changes
+
+- Removed deprecated namespaces. Namespace names were updated a couple of  
releases ago. This release removes the old names.
+- *Use `MemberEventWrapper` in favor of `EventWrapper` for instance member  
functions

+- Add an extension mechanism to `Packet` and `Request`
+- Set x86 CPU vendor string to "HygoneGenuine" to better support GLIBC
+
+## New features and improvements
+
+### Large improvements to gem5 resources and gem5 vision website
+
+We now have a new web portal for the gem5 resources:  
<https://resources.gem5.org>

+
+This web portal will allow users to browse the resources available (e.g.,  
disk images, kernels, workloads, binaries, simpoints, etc.) to use  
out-of-the-box with the gem5 standard library.
+You can filter based on architecture, resource type, and compatible gem5  
versions.

+
+For each resource, there are examples of how to use the resource and  
pointers to examples using the resource in the gem5 codebase.

+
+More information can be found on gem5's website:  
<https://www.gem5.org/documentation/general_docs/gem5_resources/>

+
+For instance, you can now add the following code to your config script to  
run the "ubuntu-boot" workload.

+
+```python
+board.set_workload(Workload("x86-ubuntu-18.04-boot"))
+```
+
+We will be expanding gem5 resources with more workloads over the course of  
the next release.
+If you would like to contribute to gem5 resources by uploading your own  
workloads, disk images, etc., please create and issue on GitHub.

+
+In addition to the new gem5 Resources web portal, the gem5 Resources API  
has been significantly updated and improved.
+There are now much simpler functions for getting resources such as  
`obtain_resource()` that will download the resource by name and  
return a reference that can be used (e.g., as a binary in `set_se_workload`  
function on the board).
+We also added the `set_workload` function that is a function of the  
`Board` that allows you to use a `Workload` from gem5 Resources with a  
board.
+This function will set up the workload including the disk image, kernel,  
and command line for full system workloads.
+Additionally, we have added support for SimPoints and checkpoints as  
workloads.

+
+### Arm v9 improvements
+
+Many improvements to Arm so that gem5 is mostly compatible with Armv9.2.
+
+Support for some Arm SME (matrix extensions) has been added and more  
support for Arm SVE is included this release.

+
+### Add support for DRAMSys
+
+gem5 can now use DRAMSys <https://github.com/tukl-msd/DRAMSys> as a DRAM  
backend.

+
+### Standard library improvements and new components
+
+- Add MESI_Three_Level component.
+- The gem5 standard library now supports both SimPoint and LoopPoint  
resources.

+- gem5 also now supports ELFies and LoopPoint analysis output from Sniper.
+- DRAMSys is supported in the stdlib.
+
+## Bugfixes and other small improvements
+
+- Lots of RISC-V bugfixes and improvements. Applications should be more  
stable now.

+- Fully implem

[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Fix SPEC benchmarks example scripts

2023-06-14 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71738?usp=email )



Change subject: configs: Fix SPEC benchmarks example scripts
..

configs: Fix SPEC benchmarks example scripts

This small change fixes the gem5_library example
scripts for SPEC benchmarks to make them compatible
with the latest version of the std library.

Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
---
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
M configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

index 60d93eb..10d5da0 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -262,7 +262,7 @@
 kernel=Resource("x86-linux-kernel-4.19.83"),
 # The location of the x86 SPEC CPU 2017 image
 disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
 ),
 readfile_contents=command,
 )
diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

index c491c9b..cb5f5d1 100644
--- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
@@ -278,7 +278,7 @@
 kernel=Resource("x86-linux-kernel-4.19.83"),
 # The location of the x86 SPEC CPU 2017 image
 disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
 ),
 readfile_contents=command,
 )

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[gem5-dev] [XS] Change in gem5/gem5[develop]: python: Ignore -s as gem5 option

2023-06-13 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71502?usp=email )


Change subject: python: Ignore -s as gem5 option
..

python: Ignore -s as gem5 option

This enables more compatibility with the normal python binary. This is
needed to get multiprocessing to work on some systems.

Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71502
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M src/python/m5/main.py
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index a68279b..4701dfa 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -193,6 +193,13 @@
 callback=collect_args,
 )

+option(
+"-s",
+action="store_true",
+help="IGNORED, only for compatibility with python. don't"
+"add user site directory to sys.path; also PYTHONNOUSERSITE",
+)
+
 # Statistics options
 group("Statistics Options")
 option(

--
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Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: python: Ignore -s as gem5 option

2023-06-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71502?usp=email )



Change subject: python: Ignore -s as gem5 option
..

python: Ignore -s as gem5 option

This enables more compatibility with the normal python binary. This is
needed to get multiprocessing to work on some systems.

Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Signed-off-by: Jason Lowe-Power 
---
M src/python/m5/main.py
1 file changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index a68279b..4701dfa 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -193,6 +193,13 @@
 callback=collect_args,
 )

+option(
+"-s",
+action="store_true",
+help="IGNORED, only for compatibility with python. don't"
+"add user site directory to sys.path; also PYTHONNOUSERSITE",
+)
+
 # Statistics options
 group("Statistics Options")
 option(

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[gem5-dev] State of Arm SVE2 in gem5

2023-06-02 Thread Jason Lowe-Power via gem5-dev
Hi Giacomo,

I've noticed that you've been pushing a number of updates to the Arm ISA,
some of which are implementing Arm SVE2 instructions (I believe). Could you
let us know what the current status is of these instructions? Have all of
them been integrated into gem5 or just a subset?

Thanks!
Jason
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add os import to marshall

2023-05-23 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70918?usp=email )


Change subject: scons: Add os import to marshall
..

scons: Add os import to marshall

This file was missing the `import os` after
I3ad28b6ee52fd347d2fe71f279baab629e88d12c

Change-Id: I7fde59e92f03fd240f48a304488d77628bfdb852
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70918
Maintainer: Jason Lowe-Power 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M build_tools/marshal.py
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/build_tools/marshal.py b/build_tools/marshal.py
index 4a1522f..58c78e1 100644
--- a/build_tools/marshal.py
+++ b/build_tools/marshal.py
@@ -50,6 +50,7 @@

 import locale
 import marshal
+import os
 import sys
 import zlib


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Gerrit-Change-Number: 70918
Gerrit-PatchSet: 2
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Gerrit-Reviewer: Gabe Black 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add os import to marshall

2023-05-23 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70918?usp=email )



Change subject: scons: Add os import to marshall
..

scons: Add os import to marshall

This file was missing the `import os` after
I3ad28b6ee52fd347d2fe71f279baab629e88d12c

Change-Id: I7fde59e92f03fd240f48a304488d77628bfdb852
Signed-off-by: Jason Lowe-Power 
---
M build_tools/marshal.py
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/build_tools/marshal.py b/build_tools/marshal.py
index 4a1522f..58c78e1 100644
--- a/build_tools/marshal.py
+++ b/build_tools/marshal.py
@@ -50,6 +50,7 @@

 import locale
 import marshal
+import os
 import sys
 import zlib


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[gem5-users] Re: [gem5-dev] Problem running gem5 gui

2023-04-19 Thread Jason Lowe-Power via gem5-users
Hi Nick,

Unfortunately, we haven't been able to keep the gem5 gui up to date with
either gem5 or python. I'm afraid that the code has undergone a lot of
bitrot over the past couple of years.

If it's any help, I can point you to what I use in my grad classes:
https://jlpteaching.github.io/comparch/modules/gem5/index/

Cheers,
Jason

On Wed, Apr 19, 2023 at 11:52 AM Beser, Nicholas D. via gem5-dev <
gem5-dev@gem5.org> wrote:

> I am creating a module for a graduate class that I teach at the Johns
> Hopkins University that covers gem5 and gem5 GUI. The gem5 code seems to
> work as expected. When I installed the GUI code, the installation seemed to
> complete without errors.  I can see that I have python 3.7.18 and pyside
> 5.13.2 with shiboken2 (version 5.13.2). However when I try to run the gui
> against the gem5.opt that I built (successfully and ran a script against).
> I get the following:
>
>
>
> ~/gem5/build/X86/gem5.opt gui.py
>
> gem5 Simulator System.  https://www.gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
>
>
> gem5 version 22.1.0.0
>
> gem5 compiled Apr 18 2023 20:48:40
>
> gem5 started Apr 19 2023 12:55:02
>
> gem5 executing on besernd1-vm5, pid 823044
>
> command line: /home/besernd1/gem5/build/X86/gem5.opt gui.py
>
>
>
> TypeError: 'Shiboken.ObjectType' object is not iterable
>
>
>
> I researched the error, and it suggested that the version of python or the
> version of pyside2 was out of sync. (The web reference was not for a gem5
> error). I could use some advice to get around this error.
>
>
>
> Thank-you,
>
> Nick Beser
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Add progress bars for long functions

2023-02-27 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67472?usp=email )


Change subject: stdlib: Add progress bars for long functions
..

stdlib: Add progress bars for long functions

This adds a progress bar for downloading large files and computing
md5sums on large files.

Change-Id: Iddc9faf61e861837cc1e2e3b3dbdbeebd6ccf529
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67472
Tested-by: kokoro 
Reviewed-by: Melissa Jost 
Maintainer: Jason Lowe-Power 
---
A optional-requirements.txt
M src/python/SConscript
M src/python/gem5/resources/downloader.py
M src/python/gem5/resources/md5_utils.py
A src/python/gem5/utils/progress_bar.py
5 files changed, 132 insertions(+), 6 deletions(-)

Approvals:
  kokoro: Regressions pass
  Melissa Jost: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/optional-requirements.txt b/optional-requirements.txt
new file mode 100644
index 000..f88787d
--- /dev/null
+++ b/optional-requirements.txt
@@ -0,0 +1 @@
+tqdm==4.64.1
diff --git a/src/python/SConscript b/src/python/SConscript
index 900723b..b0f11dd 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -267,6 +267,7 @@
 PySource('gem5.utils', 'gem5/utils/__init__.py')
 PySource('gem5.utils', 'gem5/utils/filelock.py')
 PySource('gem5.utils', 'gem5/utils/override.py')
+PySource('gem5.utils', 'gem5/utils/progress_bar.py')
 PySource('gem5.utils', 'gem5/utils/requires.py')
 PySource('gem5.utils.multiprocessing',
 'gem5/utils/multiprocessing/__init__.py')
diff --git a/src/python/gem5/resources/downloader.py  
b/src/python/gem5/resources/downloader.py

index 4a2ed5d..24b8970 100644
--- a/src/python/gem5/resources/downloader.py
+++ b/src/python/gem5/resources/downloader.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 The Regents of the University of California
+# Copyright (c) 2021-2023 The Regents of the University of California
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -42,6 +42,7 @@
 from typing import List, Dict, Set, Optional

 from .md5_utils import md5_file, md5_dir
+from ..utils.progress_bar import tqdm, progress_hook

 from ..utils.filelock import FileLock

@@ -286,10 +287,26 @@
 # get the file as a bytes blob
 request = urllib.request.Request(url)
 with urllib.request.urlopen(request, context=ctx) as fr:
-with open(download_to, "wb") as fw:
-fw.write(fr.read())
+with tqdm.wrapattr(
+open(download_to, "wb"),
+"write",
+miniters=1,
+desc="Downloading {download_to}",
+total=getattr(fr, "length", None),
+) as fw:
+for chunk in fr:
+fw.write(chunk)
 else:
-urllib.request.urlretrieve(url, download_to)
+with tqdm(
+unit="B",
+unit_scale=True,
+unit_divisor=1024,
+miniters=1,
+desc=f"Downloading {download_to}",
+) as t:
+urllib.request.urlretrieve(
+url, download_to, reporthook=progress_hook(t)
+)
 return
 except HTTPError as e:
 # If the error code retrieved is retryable, we retry using a
diff --git a/src/python/gem5/resources/md5_utils.py  
b/src/python/gem5/resources/md5_utils.py

index d7212ab..f4a1a87 100644
--- a/src/python/gem5/resources/md5_utils.py
+++ b/src/python/gem5/resources/md5_utils.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2022 The Regents of the University of California
+# Copyright (c) 2022-2023 The Regents of the University of California
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -31,7 +31,22 @@

 def _md5_update_from_file(filename: Path, hash: Hash) -> Hash:
 assert filename.is_file()
-with open(str(filename), "rb") as f:
+
+if filename.stat().st_size < 1024 * 1024 * 100:
+from ..utils.progress_bar import FakeTQDM
+
+# if the file is less than 100MB, no need to show a progress bar.
+tqdm = FakeTQDM()
+else:
+from ..utils.progress_bar import tqdm
+
+with tqdm.wrapattr(
+open(str(filename), "rb"),
+"read",
+miniters=1,
+desc=f"Computing md5sum on {filename}",
+total=filename.stat().st_size,
+) as f:
 for chunk in iter(lambda: f.read(4096)

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Add fatal in BaseCPU for wrong workloads

2023-02-25 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67937?usp=email )


Change subject: cpu: Add fatal in BaseCPU for wrong workloads
..

cpu: Add fatal in BaseCPU for wrong workloads

The CPU models assume that the number of workloads (Processes) is equal
to the number of threads when using SE mode. This wasn't checked leading
to a segfault if there were no workloads. This change makes the error
more clear.

Change-Id: I9a7b21112b8f819c6eeca944ee0d73ae9ce9a57b
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67937
Reviewed-by: Ayaz Akram 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/base.cc
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Ayaz Akram: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 60d443a..d2c0a78 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -182,6 +182,12 @@
   "of threads (%i).\n", params().isa.size(), numThreads);
 }

+if (!FullSystem && params().workload.size() != numThreads) {
+fatal("Number of processes (cpu.workload) (%i) assigned to the  
CPU "

+  "does not equal number of threads (%i).\n",
+  params().workload.size(), numThreads);
+}
+
 modelResetPort.onChange([this](const bool &new_val) {
 setReset(new_val);
 });

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Gerrit-Change-Id: I9a7b21112b8f819c6eeca944ee0d73ae9ce9a57b
Gerrit-Change-Number: 67937
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Add support for ELFies

2023-02-17 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68038?usp=email )



Change subject: stdlib: Add support for ELFies
..

stdlib: Add support for ELFies

This enables the stdlib to load and run ELFie-based binaries

See https://github.com/intel/pinball2elf for more details on ELFies

Change-Id: Ic1b624df64da1c77afc0907257a9e989488912ec
Signed-off-by: Jason Lowe-Power 
---
M src/python/SConscript
M src/python/gem5/components/boards/se_binary_workload.py
A src/python/gem5/resources/elfie.py
3 files changed, 114 insertions(+), 0 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index f401c03..900723b 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -263,6 +263,7 @@
 PySource('gem5.resources', 'gem5/resources/resource.py')
 PySource('gem5.resources', 'gem5/resources/workload.py')
 PySource('gem5.resources', 'gem5/resources/looppoint.py')
+PySource('gem5.resources', 'gem5/resources/elfie.py')
 PySource('gem5.utils', 'gem5/utils/__init__.py')
 PySource('gem5.utils', 'gem5/utils/filelock.py')
 PySource('gem5.utils', 'gem5/utils/override.py')
diff --git a/src/python/gem5/components/boards/se_binary_workload.py  
b/src/python/gem5/components/boards/se_binary_workload.py

index ebdfa40..e4aa1ba 100644
--- a/src/python/gem5/components/boards/se_binary_workload.py
+++ b/src/python/gem5/components/boards/se_binary_workload.py
@@ -35,6 +35,7 @@
 SimpointDirectoryResource,
 )

+from gem5.resources.elfie import ELFieInfo
 from gem5.resources.looppoint import Looppoint

 from m5.objects import SEWorkload, Process
@@ -209,6 +210,37 @@
 checkpoint=checkpoint,
 )

+def set_se_elfie_workload(
+self,
+elfie: AbstractResource,
+elfie_info: ELFieInfo,
+arguments: List[str] = [],
+checkpoint: Optional[Union[Path, AbstractResource]] = None,
+) -> None:
+"""Set up the system to run a ELFie workload.
+
+**Limitations**
+* Dynamically linked executables are partially supported when the  
host

+  ISA and the simulated ISA are the same.
+
+:param elfie: The resource encapsulating the binary elfie to be  
run.

+:param arguments: The input arguments for the binary
+:param elfie_info: The ELFieInfo object that contain all the  
information

+for the ELFie
+"""
+
+assert isinstance(elfie_info, ELFieInfo)
+self._elfie_info_object = elfie_info
+
+self._elfie_info_object.setup_processor(self.get_processor())
+
+# Call set_se_binary_workload after LoopPoint setup is complete
+self.set_se_binary_workload(
+binary=elfie,
+arguments=arguments,
+checkpoint=checkpoint,
+)
+
 def get_looppoint(self) -> Looppoint:
 """
 Returns the LoopPoint object set. If no LoopPoint object has been  
set
diff --git a/src/python/gem5/resources/elfie.py  
b/src/python/gem5/resources/elfie.py

new file mode 100644
index 000..ae51388
--- /dev/null
+++ b/src/python/gem5/resources/elfie.py
@@ -0,0 +1,67 @@
+# Copyright (c) 2023 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+fro

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-x86,sim-se: Ignore the some mem syscalls

2023-02-17 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68037?usp=email )



Change subject: arch-x86,sim-se: Ignore the some mem syscalls
..

arch-x86,sim-se: Ignore the some mem syscalls

This makes the Linux SE mode ignore mlockall and modify_ldt. It is
needed to get ELFies working.

Change-Id: I9fce3c6a5531e5f1bb094c2d0587fa330d2892a9
Signed-off-by: Jason Lowe-Power 
---
M src/arch/x86/linux/syscall_tbl64.cc
1 file changed, 15 insertions(+), 2 deletions(-)



diff --git a/src/arch/x86/linux/syscall_tbl64.cc  
b/src/arch/x86/linux/syscall_tbl64.cc

index 1e7274c..26299d8 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -194,10 +194,10 @@
 { 148, "sched_rr_get_interval" },
 { 149, "mlock" },
 { 150, "munlock" },
-{ 151, "mlockall" },
+{ 151, "mlockall", ignoreFunc },
 { 152, "munlockall" },
 { 153, "vhangup" },
-{ 154, "modify_ldt" },
+{ 154, "modify_ldt", ignoreFunc },
 { 155, "pivot_root" },
 { 156, "_sysctl" },
 { 157, "prctl", ignoreFunc },

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[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Add fatal in BaseCPU for wrong workloads

2023-02-14 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67937?usp=email )



Change subject: cpu: Add fatal in BaseCPU for wrong workloads
..

cpu: Add fatal in BaseCPU for wrong workloads

The CPU models assume that the number of workloads (Processes) is equal
to the number of threads when using SE mode. This wasn't checked leading
to a segfault if there were no workloads. This change makes the error
more clear.

Change-Id: I9a7b21112b8f819c6eeca944ee0d73ae9ce9a57b
Signed-off-by: Jason Lowe-Power 
---
M src/cpu/base.cc
1 file changed, 23 insertions(+), 0 deletions(-)



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 60d443a..9095072 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -181,10 +181,18 @@
 fatal("Number of ISAs (%i) assigned to the CPU does not equal  
number "

   "of threads (%i).\n", params().isa.size(), numThreads);
 }
+<<<<<<< Updated upstream

 modelResetPort.onChange([this](const bool &new_val) {
 setReset(new_val);
 });
+===
+if (!FullSystem && params().workload.size() != numThreads) {
+fatal("Number of processes (cpu.workload) (%i) assigned to the  
CPU "

+  "does not equal number of threads (%i).\n",
+  params().workload.size(), numThreads);
+}
+>>>>>>> Stashed changes
 }

 void

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[gem5-dev] Re: Build failed in Jenkins: weekly #99

2023-01-07 Thread Jason Lowe-Power via gem5-dev
Thanks for quickly digging into this, Matt!

On Sat, Jan 7, 2023 at 1:41 PM Matt Sinclair via gem5-dev 
wrote:

> I have confirmed that the Pannotia benchmarks (to my surprise) are using
> AMD's cache bypassing flags for some memory accesses, which Vishnu added
> support for this week.  Good thing the support is added now!  But that is
> why they are failing here -- they hit a corner case Vishnu and I had
> considered, but implemented incorrectly.  I have a fix I am testing now and
> will push later tonight assuming it solves the problem.
>
> Matt
>
> On Fri, Jan 6, 2023 at 10:07 PM Matt Sinclair <
> mattdsinclair.w...@gmail.com> wrote:
>
>> Hi Matt P & Vishnu,
>>
>> It appears something with the GPU support must have broken between your
>> changes this week -- as far as I can tell all of the nightly tests passed
>> when you checked in your commits, but something in the more complex
>> benchmarks (BC in this case) is breaking:
>>
>> gem5.opt: build/GCN3_X86/mem/ruby/system/VIPERCoalescer.cc:265: void 
>> gem5::ruby::VIPERCoalescer::invTCPCallback(gem5::Addr): Assertion 
>> `m_cache_inv_pkt && m_num_pending_invs > 0' failed.
>>
>> Vishnu, did you test your changes with the weekly tests at all?
>>
>> Matt P did you test your changes with the weekly tests at all?  And have
>> you started bisecting yet to find the offending commit?
>>
>> If not, Vishnu I can show you how to do this.  I will be away next week
>> (although with intermittent email access) so a fix relying on me may be
>> delayed ... but hopefully between the three of us we can isolate and figure
>> out which commit is causing/fixing.  My intuition says that it's probably
>> one of Vishnu's commits, since Matt P's aren't changing the coherence
>> protocol at all, but it's not obvious why Vishnu's commits would be
>> affecting the invalidation calls at all ...
>>
>> Thanks,
>> Matt S.
>>
>> On Fri, Jan 6, 2023 at 9:54 PM jenkins-no-reply--- via gem5-dev <
>> gem5-dev@gem5.org> wrote:
>>
>>> See <
>>> https://jenkins.gem5.org/job/weekly/99/display/redirect?page=changes>
>>>
>>> Changes:
>>>
>>> [Bobby R. Bruce] ext: Fix SST Documentation links
>>>
>>> [Bobby R. Bruce] tests: Fix the download test
>>>
>>> [Bobby R. Bruce] stdlib: Removing incorrect requires.
>>>
>>> [Bobby R. Bruce] stdlib: se_binary_workload exits on work items by
>>> default
>>>
>>> [Bobby R. Bruce] configs: Fix unconnected PCI port in SST gem5 config
>>>
>>> [Bobby R. Bruce] mem: Add getAddrRanges in HBMCtrl
>>>
>>> [Bobby R. Bruce] system-arm: Fix FEAT_PAuth trapping in AArch64
>>> bootloader
>>>
>>> [Bobby R. Bruce] misc: Update version info to v22.0.0.2
>>>
>>> [Bobby R. Bruce] misc: Update RELEASE-NOTES.md for v22.0.0.2
>>>
>>> [Bobby R. Bruce] stdlib: Fix get_isa_from_str() exception behavior in
>>> isas.py
>>>
>>> [Bobby R. Bruce] dev-amdgpu: Handle ring buffer wrap for PM4 queue
>>>
>>> [Bobby R. Bruce] arch-vega: Fix SOPK instruction sign extends
>>>
>>> [Bobby R. Bruce] dev-amdgpu: Fix SDMA ring buffer wrap around
>>>
>>> [Bobby R. Bruce] arch-x86: X86ISA default vector_string to HygonGenuine
>>>
>>> [Bobby R. Bruce] arch-arm: Revert 'Setup TC/ISA at construction time..'
>>>
>>> [Bobby R. Bruce] stdlib,configs: Update riscvmatched-fs example docstring
>>>
>>> [Bobby R. Bruce] configs,stdlib: Fix import in riscvmatched-fs.py
>>>
>>> [Bobby R. Bruce] configs,stdlib,tests: Update riscvmatched-fs.py to-init
>>>
>>> [Bobby R. Bruce] tests: Update riscvmatched tests to use ALL/gem5.opt
>>>
>>> [Bobby R. Bruce] configs: Add missing `_pre_instantiate` call in
>>> "run_lupv.py"
>>>
>>> [Bobby R. Bruce] tests: Delete build directory before running KVM in
>>> nightly
>>>
>>> [Bobby R. Bruce] configs: Set CPU vendor to M5 Simulator in apu_se.py
>>>
>>> [Bobby R. Bruce] stdlib,python: Allow setting of to tick exits via m5
>>>
>>> [Bobby R. Bruce] stdlib, configs: Updating configs/example/gem5_library
>>>
>>> [Bobby R. Bruce] arch-arm: Setup TC/ISA at construction time 2nd attempt
>>>
>>> [Bobby R. Bruce] scons: Remove -Werror for the gem5 v22.1 release
>>>
>>> [Bobby R. Bruce] base: Update the version to v22.1.0.0
>>>
>>> [Bobby R. Bruce] python,tests: Update Resource URL path to v22-1
>>>
>>> [Bobby R. Bruce] stdlib: Update the gem5 resources' version to "v22.1"
>>>
>>> [Bobby R. Bruce] util-docker: Update gcn-gpu Docker to use v22-1 ROCM
>>> patch
>>>
>>> [Bobby R. Bruce] util-docker: Add v22-1 tag to docker-compose.yaml
>>>
>>> [Bobby R. Bruce] tests: Update the compiler-tests.sh to use the v22-1
>>> images
>>>
>>> [Bobby R. Bruce] tests: Abstract the docker image tag for Nightly tests
>>>
>>> [Bobby R. Bruce] tests: Update nightly test docker image tags to v22-1
>>>
>>> [Bobby R. Bruce] tests: Abstract the docker image tag for Weekly tests
>>>
>>> [Bobby R. Bruce] tests: Update weekly test docker image tags to v22-1
>>>
>>> [Bobby R. Bruce] util-gem5art: Fix incorrect type of size in
>>> `createArtifact`
>>>
>>> [Bobby R. Bruce] tests: Update presubmit.sh to use v22-1 docker image

[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix compiler-tests.sh build args passing

2022-12-17 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66772?usp=email )


Change subject: tests: Fix compiler-tests.sh build args passing
..

tests: Fix compiler-tests.sh build args passing

Reverts this fix:
https://gem5-review.googlesource.com/c/public/gem5/+/66631

While this did fix the case where no build args were passed, it broke
the case where build args were passed.

This fix ensures the script works in both cases.

Change-Id: I6cc8cc0c2a10c801d4a59e54b070383ac8ee93ae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66772
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/compiler-tests.sh
1 file changed, 31 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index f16e8e5..f5d4bb1 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -76,7 +76,13 @@
 base_url="gcr.io/gem5-test"

 # Arguments passed into scons on every build target test.
-build_args="$@"
+if [ $# -eq 0 ];then
+# If none is sepcified by the user we pass "-j1" (compile on one  
thread).

+# If `build_args` is left as an empty string, this script will fail.
+build_args="-j1"
+else
+build_args="$@"
+fi

 # Testing directory variables
 mkdir -p "${build_dir}" # Create the build directory if it doesn't exist.
@@ -135,7 +141,7 @@
 docker run --rm -v "${gem5_root}":"/gem5" -u $UID:$GID \
 -w /gem5 --memory="${docker_mem_limit}" $repo_name \
 /usr/bin/env python3 /usr/bin/scons --ignore-style \
-"${build_out} ${build_args}"
+"${build_out}" "${build_args}"
 }>"${build_stdout}" 2>"${build_stderr}"
 result=$?


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6cc8cc0c2a10c801d4a59e54b070383ac8ee93ae
Gerrit-Change-Number: 66772
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix compiler-tests.sh for no build args passed case

2022-12-13 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66631?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Fix compiler-tests.sh for no build args passed case
..

tests: Fix compiler-tests.sh for no build args passed case

When a user ran "tests/compiler-tests.sh" without passing any arguments,
the compiler tests would fail with:

```
scons: Reading SConscript files ...
Error: No existing build directory and no variant for /gem5
```

However, when passed with arguments, such as:

```
./tests/compiler-tests.sh -j6
```

the tests passed.

The fix for this is to merge the "$build_out" and "$build_args" into a
single string when executing the docker. I do not know exactly why this
works, but it does fix the error.

Change-Id: Ibcd316668b60fb7706f0ee05ab6dadf56228319d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66631
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/compiler-tests.sh
1 file changed, 34 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index e01d9de..f16e8e5 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -135,7 +135,7 @@
 docker run --rm -v "${gem5_root}":"/gem5" -u $UID:$GID \
 -w /gem5 --memory="${docker_mem_limit}" $repo_name \
 /usr/bin/env python3 /usr/bin/scons --ignore-style \
-"${build_out}" "${build_args}"
+"${build_out} ${build_args}"
 }>"${build_stdout}" 2>"${build_stderr}"
 result=$?


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibcd316668b60fb7706f0ee05ab6dadf56228319d
Gerrit-Change-Number: 66631
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: nightly #413

2022-11-15 Thread Jason Lowe-Power via gem5-dev
Hi Matt,

That might work for KVM, but it doesn't work for the timing CPUs as far as
I know. The problem we ran into was not with KVM but with the timing CPUs.

The underlying problem is that we are not modeling the system correctly.
Either there's something wrong with our cpuid instruction (it's definitely
not a "valid" result! but I'm not sure if it's the main problem here), or
there's something wrong with our APIC implementation. Almost certainly both
are true, but I don't know which one is the main culprit here.

Cheers,
Jason

On Mon, Nov 14, 2022 at 5:05 PM Poremba, Matthew via gem5-dev <
gem5-dev@gem5.org> wrote:

> [AMD Official Use Only - General]
>
> Hi Bobby,
>
>
>
>
>
> I have seen this issue with do_boot_cpu as well. The short story is I had
> to use multiple event queues and set the “sim_quantum” of the Root object
> to 1e8:  https://gem5-review.googlesource.com/c/public/gem5/+/65131.
> Note that 1e8 is different from the 1e9 value used elsewhere in gem5. Based
> on a test of doing 100 boots with 4 CPUs, 1e8 booted all four CPUs every
> time and 1e9 booted all four CPUs only twice.
>
>
>
>
>
> -Matt
>
>
>
> *From:* Bobby Bruce via gem5-dev 
> *Sent:* Monday, November 14, 2022 10:37 AM
> *To:* gem5-dev@gem5.org
> *Cc:* Bobby Bruce 
> *Subject:* [gem5-dev] Re: Build failed in Jenkins: nightly #413
>
>
>
> *Caution:* This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
>
> Hey all,
>
>
>
> I've submitted the following patch to Gerrit which should fix the timeout
> issues we're seeing with the Jenkin's nightly build:
> https://gem5-review.googlesource.com/c/public/gem5/+/65492
> 
> .
>
>
>
> The high level summary of the problem is as follows:
>
>
>
> - Up until recently we were using "m5 Simulator" as the "vendor_string"
> for each CPU in a gem5 simulation by default.
>
> - The latest versions of GLIB are now much stricter in checking system
> capabilities. It does not recognize "m5 Simulator" as a legitimate vendor
> and this causes problems. We became aware of this when trying to run SE
> workloads in Ubuntu 22.04 or running FS Ubuntu 22.04 workloads.
>
> - Jason changed the default vendor string to "AuthenticAMD" via this
> commit: https://gem5-review.googlesource.com/c/public/gem5/+/64831
> .
> This fixed the above problems but due to a bug, highlighted here:
> https://gem5.atlassian.net/browse/GEM5-1300
> ,
> Linux boots were taking an extremely long time. This caused our Nightly
> tests to reach timeout.
>
> - Our solution is to change the default vector string "HygonGenuine".
> This fixes all of the problems (GLIB problems and long boot times).
> However, we'd prefer to use "AuthenticAMD" over "HygonGenuine" so would
> appreciate it someone could find the time to look into the bug in GEM5-1300.
>
>
>
> Thanks to everyone for your patience here. I know you've all been spammed
> with failing Nightly errors for some time now. Hopefully after this patch
> is submitted we'll be back to everything passing.
>
>
>
> Kind regards,
>
> Bobby
>
>
>
> --
>
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
>
>
> web: https://www.bobbybruce.net
> 
>
>
>
>
>
> On Wed, Nov 9, 2022 at 2:33 PM Bobby Bruce  wrote:
>
> It turns out 

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib,mem-ruby: Add DVM TBEs to CHI in stdlib

2022-10-19 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64691?usp=email )


Change subject: stdlib,mem-ruby: Add DVM TBEs to CHI in stdlib
..

stdlib,mem-ruby: Add DVM TBEs to CHI in stdlib

Change-Id: I12c7cf3aff5450c73c626c5272ae34d84dc612c3
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64691
Reviewed-by: Tiago Muck 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
M src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
M  
src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

3 files changed, 20 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  Tiago Muck: Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py

index f07631e..3488435 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
@@ -81,4 +81,6 @@
 self.number_of_TBEs = 32
 self.number_of_repl_TBEs = 32
 self.number_of_snoop_TBEs = 1
+self.number_of_DVM_TBEs = 1  # should not receive any dvm
+self.number_of_DVM_snoop_TBEs = 1  # should not receive any dvm
 self.unify_repl_TBEs = False
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py

index 9ae4fec..ccac6ca 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
@@ -67,4 +67,6 @@
 self.number_of_TBEs = 16
 self.number_of_repl_TBEs = 1
 self.number_of_snoop_TBEs = 1  # Should never receive snoops
+self.number_of_DVM_TBEs = 1  # should not receive any dvm
+self.number_of_DVM_snoop_TBEs = 1  # should not receive any dvm
 self.unify_repl_TBEs = False
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

index 71bc60f..3e38c90 100644
---  
a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

@@ -74,4 +74,6 @@
 self.number_of_TBEs = 16
 self.number_of_repl_TBEs = 16
 self.number_of_snoop_TBEs = 4
+self.number_of_DVM_TBEs = 16
+self.number_of_DVM_snoop_TBEs = 4
 self.unify_repl_TBEs = False

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I12c7cf3aff5450c73c626c5272ae34d84dc612c3
Gerrit-Change-Number: 64691
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Tiago Muck 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-x86: Fix CPUID for most recent GLIBC

2022-10-19 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64831?usp=email )



Change subject: arch-x86: Fix CPUID for most recent GLIBC
..

arch-x86: Fix CPUID for most recent GLIBC

This change makes the default vendor string AuthenticAMD.

GLIBC now is much more strict about checking for the current system's
supported features. In Ubuntu 22.04, when trying to load a dynamically
linked file, the CPUID is checked for the required features. If they are
not there, an error saying ISA level too low is returned and the program
crashes.

The underlying issue is that GLIBC does not check and populate the
cpu_feature data structure if it does not detect a *known* CPU model.
The options are hardcoded. See the following file for the glibc code.

glibc/sysdeps/x86/cpu-features.c

Note that the cpu_features is not populated with the
COMMON_CPUID_INDEX_1 unless there is a known family, which is only set
if the vendor string matches a known vendor.

This change uses AuthenticAMD instead of the alternatives because the
checks in glibc are most simple (no special cases) for AuthenticAMD in
the init_cpu_features functions.

GLIBC has been unable to populate the cpu_features datastructure
correctly with gem5 for a long time. However, this has just now become a
problem for us because the library now is more strict on not allowing
code to execute unless the processor meets certain minimum requirements.

I believe the commit for GLIBC which caused this breakage is
ecce11aa0752735c4fd730da6e7c9e0b98e12fb8
See https://sourceware.org/pipermail/binutils/2020-October/113593.html
for more details on that commit.

Change-Id: I8eedb46f577361e749ad8d0adda4fd0753e99960
Signed-off-by: Jason Lowe-Power 
---
M src/arch/x86/X86ISA.py
1 file changed, 43 insertions(+), 1 deletion(-)



diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py
index 53a3cfc..2760b76 100644
--- a/src/arch/x86/X86ISA.py
+++ b/src/arch/x86/X86ISA.py
@@ -43,5 +43,5 @@
 cxx_header = "arch/x86/isa.hh"

 vendor_string = Param.String(
-"M5 Simulator", "Vendor string for CPUID instruction"
+"AuthenticAMD", "Vendor string for CPUID instruction"
 )

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8eedb46f577361e749ad8d0adda4fd0753e99960
Gerrit-Change-Number: 64831
Gerrit-PatchSet: 1
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[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add example memory traffic runscript

2022-10-18 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64018?usp=email )


Change subject: configs: Add example memory traffic runscript
..

configs: Add example memory traffic runscript

This simple example shows how to use the test board to test the
bandwidth for an HBM2 pair of pseudo channels

Change-Id: I6235d0cb11909f5b4cc6442e419496c77425ba37
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64018
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Bobby Bruce 
---
A configs/example/gem5_library/memory_traffic.py
1 file changed, 131 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/memory_traffic.py  
b/configs/example/gem5_library/memory_traffic.py

new file mode 100644
index 000..d6772d1
--- /dev/null
+++ b/configs/example/gem5_library/memory_traffic.py
@@ -0,0 +1,114 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script is used for running a traffic generator connected to a memory
+device. It supports linear and random accesses with a configurable amount
+of write traffic.
+
+By default, this scripts runs with one channel (two pseudo channels) of  
HBM2

+and this channel is driven with 32GiB/s of traffic for 1ms.
+"""
+
+import argparse
+
+from m5.objects import MemorySize
+from gem5.components.boards.test_board import TestBoard
+
+from gem5.components.processors.linear_generator import LinearGenerator
+from gem5.components.processors.random_generator import RandomGenerator
+
+from gem5.components.memory.hbm import HighBandwidthMemory
+from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
+
+from gem5.simulate.simulator import Simulator
+
+
+def generator_factory(
+generator_class: str, rd_perc: int, mem_size: MemorySize
+):
+rd_perc = int(rd_perc)
+if rd_perc > 100 or rd_perc < 0:
+raise ValueError(
+"Read percentage has to be an integer number between 0 and  
100."

+)
+if generator_class == "LinearGenerator":
+return LinearGenerator(
+duration="1ms", rate="32GiB/s", max_addr=mem_size,  
rd_perc=rd_perc

+)
+elif generator_class == "RandomGenerator":
+return RandomGenerator(
+duration="1ms", rate="32GiB/s", max_addr=mem_size,  
rd_perc=rd_perc

+)
+else:
+raise ValueError(f"Unknown generator class {generator_class}")
+
+
+parser = argparse.ArgumentParser(
+description="A traffic generator that can be used to test a gem5 "
+"memory component."
+)
+
+parser.add_argument(
+"generator_class",
+type=str,
+help="The class of generator to use.",
+choices=[
+"LinearGenerator",
+"RandomGenerator",
+],
+)
+
+parser.add_argument(
+"read_percentage",
+type=int,
+help="Percentage of read requests in the generated traffic.",
+)
+
+args = parser.parse_args()
+
+# Single pair of HBM2 pseudo channels. This can be replaced with any
+# single ported memory device
+memory = HighBandwi

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Update TestBoard to work with Simulator

2022-10-18 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64017?usp=email )


Change subject: stdlib: Update TestBoard to work with Simulator
..

stdlib: Update TestBoard to work with Simulator

This change makes minor updates to the TestBoard so that it can work
nicely with the Simulator module.

This change also makes the cache hierarchy optional for the TestBoard.

Change-Id: If46d53779164e87b6fc06176355be6b4ae05aa99
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64017
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Reviewed-by: Mahyar Samani 
---
M src/python/gem5/components/boards/test_board.py
M src/python/gem5/components/processors/abstract_generator.py
M src/python/gem5/simulate/exit_event.py
M tests/gem5/traffic_gen/simple_traffic_run.py
4 files changed, 56 insertions(+), 8 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  Mahyar Samani: Looks good to me, but someone else must approve
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/test_board.py  
b/src/python/gem5/components/boards/test_board.py

index 7267f2a..dea5ada 100644
--- a/src/python/gem5/components/boards/test_board.py
+++ b/src/python/gem5/components/boards/test_board.py
@@ -26,15 +26,15 @@

 from m5.objects import Port, IOXBar, AddrRange

-from .mem_mode import MemMode, mem_mode_to_string
 from ...utils.override import overrides
+from .abstract_board import AbstractBoard
 from .abstract_system_board import AbstractSystemBoard
-from ..processors.abstract_processor import AbstractProcessor
+from ..processors.abstract_generator import AbstractGenerator
 from ..memory.abstract_memory_system import AbstractMemorySystem
 from ..cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy



-from typing import List
+from typing import List, Optional


 class TestBoard(AbstractSystemBoard):
@@ -43,21 +43,27 @@
 architecture.

 To work as a traffic generator board, pass a generator as a processor.
+
+This board does not require a cache hierarchy (it can be none) in which
+case the processor (generator) will be directly connected to the  
memory.

+The clock frequency is only used if there is a cache hierarchy or when
+using the GUPS generators.
 """

 def __init__(
 self,
 clk_freq: str,
-processor: AbstractProcessor,
+generator: AbstractGenerator,
 memory: AbstractMemorySystem,
-cache_hierarchy: AbstractCacheHierarchy,
+cache_hierarchy: Optional[AbstractCacheHierarchy],
 ):
 super().__init__(
-clk_freq=clk_freq,
-processor=processor,
+clk_freq=clk_freq,  # Only used if cache hierarchy or GUPS-gen
+processor=generator,
 memory=memory,
 cache_hierarchy=cache_hierarchy,
 )
+self._set_fullsystem(False)

 @overrides(AbstractSystemBoard)
 def _setup_board(self) -> None:
@@ -108,3 +114,16 @@
 @overrides(AbstractSystemBoard)
 def has_dma_ports(self) -> bool:
 return False
+
+@overrides(AbstractBoard)
+def _connect_things(self) -> None:
+super()._connect_things()
+
+if not self.get_cache_hierarchy():
+# If we have no caches, then there must be a one-to-one
+# connection between the generators and the memories.
+assert len(self.get_processor().get_cores()) == 1
+assert len(self.get_memory().get_mem_ports()) == 1
+self.get_processor().get_cores()[0].connect_dcache(
+self.get_memory().get_mem_ports()[0][1]
+)
diff --git a/src/python/gem5/components/processors/abstract_generator.py  
b/src/python/gem5/components/processors/abstract_generator.py

index 41cbf5c..ff5387d 100644
--- a/src/python/gem5/components/processors/abstract_generator.py
+++ b/src/python/gem5/components/processors/abstract_generator.py
@@ -65,3 +65,6 @@
 this method needs to be implemented in detail or implmeneted as  
pass.

 """
 raise NotImplementedError
+
+def _post_instantiate(self) -> None:
+self.start_traffic()
diff --git a/src/python/gem5/simulate/exit_event.py  
b/src/python/gem5/simulate/exit_event.py

index 691e41a..0890178 100644
--- a/src/python/gem5/simulate/exit_event.py
+++ b/src/python/gem5/simulate/exit_event.py
@@ -87,6 +87,12 @@
 return ExitEvent.SIMPOINT_BEGIN
 elif exit_string == "a thread reached the max instruction count":
 return ExitEvent.MAX_INSTS
+elif exit_string.endswith("will terminate the simulation.\n"):
+# This is for the traffic generator exit event
+return ExitEvent.EXIT
+elif exit_string.endsw

[gem5-dev] [M] Change in gem5/gem5[develop]: python: Update -c to work like normal python

2022-10-18 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63151?usp=email )


Change subject: python: Update -c to work like normal python
..

python: Update -c to work like normal python

In python, when you use -c it consumes all subsequent parameters and
appends them to argv. Now, gem5 and python behave the same with -c.

Python:

python -c "import sys; print(sys.argv)" --hello -j

['-c', '--hello', '-j']

gem5:

gem5.opt -c "import sys; print(sys.argv)" --hello -j

gem5 Simulator System.  https://www.gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version [DEVELOP-FOR-22.1]
gem5 compiled Oct 17 2022 15:47:46
gem5 started Oct 17 2022 15:53:45
gem5 executing on challenger, pid 4021103
command line: build/ALL/gem5.opt -c 'import sys; print(sys.argv)' --hello -j

['-c', '--hello', '-j']

Change-Id: I53e87712be9523e0583149235c9787c92618f884
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63151
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/python/m5/main.py
1 file changed, 53 insertions(+), 9 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 2f11633..205f3f1 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -176,6 +176,23 @@
 "-v", "--verbose", action="count", default=0, help="Increase  
verbosity"

 )

+# To make gem5 mimic python better. After `-c` we should consume all  
other

+# arguments and add those to argv.
+def collect_args(option, opt_str, value, parser):
+extra_args = parser.rargs[:]
+del parser.rargs[:]
+setattr(parser.values, option.dest, (value, extra_args))
+
+option(
+"-c",
+type=str,
+help="program passed in as string (terminates option list)",
+default="",
+metavar="cmd",
+action="callback",
+callback=collect_args,
+)
+
 # Statistics options
 group("Statistics Options")
 option(
@@ -281,14 +298,6 @@
 help="List all built-in SimObjects, their params and default  
values",

 )

-option(
-"-c",
-type=str,
-help="program passed in as string (terminates option list)",
-default="",
-metavar="cmd",
-)
-
 arguments = options.parse_args()
 return options, arguments

@@ -556,8 +565,9 @@
 sys.argv = arguments

 if options.c:
-filedata = options.c
+filedata = options.c[0]
 filecode = compile(filedata, "", "exec")
+sys.argv = ["-c"] + options.c[1]
 scope = {"__name__": "__m5_main__"}
 else:
 sys.path = [os.path.dirname(sys.argv[0])] + sys.path

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I53e87712be9523e0583149235c9787c92618f884
Gerrit-Change-Number: 63151
Gerrit-PatchSet: 4
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib,mem-ruby: Add DVM TBEs to CHI in stdlib

2022-10-17 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64691?usp=email )



Change subject: stdlib,mem-ruby: Add DVM TBEs to CHI in stdlib
..

stdlib,mem-ruby: Add DVM TBEs to CHI in stdlib

Change-Id: I12c7cf3aff5450c73c626c5272ae34d84dc612c3
Signed-off-by: Jason Lowe-Power 
---
M src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
M src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
M  
src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

3 files changed, 16 insertions(+), 0 deletions(-)



diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py

index f07631e..3488435 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
@@ -81,4 +81,6 @@
 self.number_of_TBEs = 32
 self.number_of_repl_TBEs = 32
 self.number_of_snoop_TBEs = 1
+self.number_of_DVM_TBEs = 1  # should not receive any dvm
+self.number_of_DVM_snoop_TBEs = 1  # should not receive any dvm
 self.unify_repl_TBEs = False
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py

index 9ae4fec..ccac6ca 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
@@ -67,4 +67,6 @@
 self.number_of_TBEs = 16
 self.number_of_repl_TBEs = 1
 self.number_of_snoop_TBEs = 1  # Should never receive snoops
+self.number_of_DVM_TBEs = 1  # should not receive any dvm
+self.number_of_DVM_snoop_TBEs = 1  # should not receive any dvm
 self.unify_repl_TBEs = False
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

index 71bc60f..3e38c90 100644
---  
a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

@@ -74,4 +74,6 @@
 self.number_of_TBEs = 16
 self.number_of_repl_TBEs = 16
 self.number_of_snoop_TBEs = 4
+self.number_of_DVM_TBEs = 16
+self.number_of_DVM_snoop_TBEs = 4
 self.unify_repl_TBEs = False

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Gerrit-Branch: develop
Gerrit-Change-Id: I12c7cf3aff5450c73c626c5272ae34d84dc612c3
Gerrit-Change-Number: 64691
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Build failed in Jenkins: weekly #82

2022-10-15 Thread Jason Lowe-Power
I think this failed because we got unlucky. I'll re-run it.

On Fri, Oct 14, 2022 at 4:16 PM  wrote:

> See <https://jenkins.gem5.org/job/weekly/82/display/redirect?page=changes>
>
> Changes:
>
> [Jason Lowe-Power] stdlib: Update the default exit events and warning
>
> [Jason Lowe-Power] stdlib: Allow cache_hierarchy to be optional
>
> [Jason Lowe-Power] stdlib: Add _post_instantiate function
>
> [Bobby R. Bruce] mem: Fix 'unused variable' warnings
>
> [Bobby R. Bruce] mem-ruby: Fix clang-14 compilation warning "use of
> bitwise"
>
> [Bobby R. Bruce] util-docker: Add 'ubuntu-22.04_gcc-version'
>
> [Bobby R. Bruce] util-docker,tests: Add GCC-12 compiler image and test
>
> [Bobby R. Bruce] util-docker,tests: Add Clang-13 compiler image and test
>
> [Bobby R. Bruce] util-docker,tests: Add Clang-14 compiler image and test
>
> [Bobby R. Bruce] util-docker,tests: Update supported/test OS to Ubuntu
> 22.04
>
> [ztqiu] stdlib: added errout and output file option in SE process
>
> [Bobby R. Bruce] tests: Add 'riscvmatched-fs.py' example to long/nightly
> tests
>
> [Giacomo Travaglini] misc: Suggest usage of ALL instead of NULL in
> TESTING.md
>
> [Giacomo Travaglini] tests: Run ALL unit-tests with the nightly script
>
> [yuhsingw] sysetmc: fix the leak in TlmToGem5Bridge
>
> [yuhsingw] sysetmc: add missing NO_ACCESS flags in get_direct_mem_ptr
>
> [matthew.poremba] arch-vega: Implement PDE2 and PDE1 as PTE
>
> [matthew.poremba] dev-amdgpu: Add an SDMA data debug flag
>
>
> --
> [...truncated 630.16 KB...]
> Checking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf...
> (cached) yes
> Checking for C header file linux/if_tun.h... (cached) yes
> Checking whether __i386__ is declared... (cached) no
> Checking whether __x86_64__ is declared... (cached) yes
> Checking for compiler -Wno-self-assign-overloaded support... (cached) yes
> Checking for compiler -Wno-free-nonheap-object support... (cached) yes
> scons: done reading SConscript files.
> scons: Building targets ...
>  [VER TAGS]  -> GCN3_X86/sim/tags.cc
> scons: `build/GCN3_X86/gem5.opt' is up to date.
> scons: done building targets.
> *** Summary of Warnings ***
> Warning: Deprecated namespaces are not supported by this compiler.
>  Please make sure to check the mailing list for deprecation
>  announcements.
> + docker run --rm -u 118: --volume
> /nobackup/jenkins/workspace/weekly/tests/..:/nobackup/jenkins/workspace/weekly/tests/..
> -w /nobackup/jenkins/workspace/weekly/tests/../util/m5 --memory=24g
> hacc-test-weekly bash -c 'export TERM=xterm-256color ; scons
> build/x86/out/m5'
> scons: Reading SConscript files ...
> Mkdir("/nobackup/jenkins/workspace/weekly/util/m5/build")
> Checking for java package org.junit...no
> junit test framework not found, not build java wrapper test
> Checking whether pkg-config program exists.../usr/bin/pkg-config
> Checking for pkg-config package lua51...(cached) no
> lua 5.1 not detected, not building lua wrapper.
> scons: done reading SConscript files.
> scons: Building targets ...
> CXX build/x86/call_type/inst.o
> CXX build/x86/call_type/addr.o
> CXX build/x86/args.o
> CXX build/x86/call_type.o
> CXX build/x86/command.o
> CXX build/x86/command/addsymbol.o
> CXX build/x86/command/checkpoint.o
> CXX build/x86/command/dumpresetstats.o
> CXX build/x86/command/dumpstats.o
> CXX build/x86/command/exit.o
> CXX build/x86/command/fail.o
> CXX build/x86/command/sum.o
> CXX build/x86/command/initparam.o
> CXX build/x86/command/loadsymbol.o
> CXX build/x86/command/readfile.o
> CXX build/x86/command/resetstats.o
> CXX build/x86/command/writefile.o
> CXX build/x86/command/workbegin.o
> CXX build/x86/command/workend.o
> CXX build/x86/m5.o
> CC build/x86/m5_mmap.o
> ASPP build/x86/abi/x86/m5op.o
> ASPP build/x86/abi/x86/m5op_addr.o
> AR build/x86/out/libm5.a
> RANLIB build/x86/out/libm5.a
> CXX build/x86/usage.o
> LINK build/x86/out/m5
> scons: done building targets.
> + docker run --rm --volume
> /nobackup/jenkins/workspace/weekly/tests/..:/nobackup/jenkins/workspace/weekly/tests/..
> -w
> /nobackup/jenkins/workspace/weekly/tests/../gem5-resources/src/gpu/lulesh
> -u 118: --memory=24g hacc-test-weekly bash -c make
> mkdir -p ./bin
> /opt/rocm/hip/bin/hipcc src/lulesh.hip.cc -o ./bin/lulesh
> --amdgpu-target=gfx801,gfx803,gfx900
> + docker run --rm -u 118: --volume
> /nobackup/jenkins/workspace/weekly/tests/..:/nobackup/jenkins/workspace/weekly/tests/..
> -w /nobackup/jenkins/workspace/weekly/tests/.. --memory=24g
> hacc-test-weekly build/GCN3_X86/gem

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Fix linking error in aapcs64 unittests

2022-10-15 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64611?usp=email )


Change subject: arch-arm: Fix linking error in aapcs64 unittests
..

arch-arm: Fix linking error in aapcs64 unittests

This is fixing the undefined reference exposed by our nightly
run [1] by including the arch/arm/regs/int.cc source (needed
for the IntRegClassOps::flatten implementation) plus
sim/cur_tick.cc

[1]: https://www.mail-archive.com/gem5-dev@gem5.org/msg43249.html

Change-Id: I51a616ca2ef513f0068e531ebee17172d68cc738
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64611
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
---
M src/arch/arm/SConscript
1 file changed, 27 insertions(+), 2 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 5d27cee..6c359fb 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -49,8 +49,11 @@
 # Note: This will need reconfigured for multi-isa. E.g., if this is
 # incorporated: https://gem5-review.googlesource.com/c/public/gem5/+/52491
 if env['USE_ARM_ISA']:
-GTest('aapcs64.test', 'aapcs64.test.cc', '../../base/debug.cc',
-'../../cpu/reg_class.cc', '../../sim/bufval.cc')
+GTest('aapcs64.test', 'aapcs64.test.cc',
+  '../../base/debug.cc',
+  '../../cpu/reg_class.cc',
+  '../../sim/bufval.cc', '../../sim/cur_tick.cc',
+  'regs/int.cc')
 Source('decoder.cc', tags='arm isa')
 Source('faults.cc', tags='arm isa')
 Source('htm.cc', tags='arm isa')

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I51a616ca2ef513f0068e531ebee17172d68cc738
Gerrit-Change-Number: 64611
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Give board interface for mem ports

2022-10-14 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64631?usp=email )



Change subject: stdlib: Give board interface for mem ports
..

stdlib: Give board interface for mem ports

It is possible that the board has more than just a "main" memory. For
instance, the ArmBoard has a boot memory which is separate from the
`get_memory` function.

This moves the `get_mem_ports` function to the board so that the board
can optionally override it.

Change-Id: I05e388cc93e691e9a4fa674023f158af447349f9
Signed-off-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/abstract_board.py
M  
src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

4 files changed, 30 insertions(+), 4 deletions(-)



diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index fef1db0..647e6ce 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -31,6 +31,7 @@
 from ...resources.workload import AbstractWorkload

 from m5.objects import (
+AddrRange,
 System,
 Port,
 IOXBar,
@@ -39,7 +40,7 @@
 VoltageDomain,
 )

-from typing import List, Optional
+from typing import List, Optional, Sequence, Tuple


 class AbstractBoard:
@@ -123,6 +124,14 @@
 """
 return self.memory

+def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+"""Get the memory ports exposed on this board
+
+Note: The ports should be returned such that the address ranges are
+in ascending order.
+"""
+return self.get_memory().get_mem_ports()
+
 def get_cache_hierarchy(self) -> Optional["AbstractCacheHierarchy"]:
 """Get the cache hierarchy connected to the board.

diff --git  
a/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

index 2033903..9c91e05 100644
---  
a/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

@@ -202,7 +202,7 @@
 self, board: AbstractBoard
 ) -> List[MemoryController]:
 memory_controllers = []
-for rng, port in board.get_memory().get_mem_ports():
+for rng, port in board.get_mem_ports():
 mc = MemoryController(self.ruby_system.network, rng, port)
 mc.ruby_system = self.ruby_system
 memory_controllers.append(mc)
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

index 96c7b70..82089a5 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -147,7 +147,7 @@

 self._directory_controllers = [
 Directory(self.ruby_system.network, cache_line_size, range,  
port)

-for range, port in board.get_memory().get_mem_ports()
+for range, port in board.get_mem_ports()
 ]
 # TODO: Make this prettier: The problem is not being able to proxy
 # the ruby system correctly
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

index e3cf714..5955ad3 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

@@ -118,7 +118,7 @@

 # Create the directory controllers
 self._directory_controllers = []
-for range, port in board.get_memory().get_mem_ports():
+for range, port in board.get_mem_ports():
 dir = Directory(
 self.ruby_system.network,
 board.get_cache_line_size(),

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Gerrit-Branch: develop
Gerrit-Change-Id: I05e388cc93e691e9a4fa674023f158af447349f9
Gerrit-Change-Number: 64631
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Add _post_instantiate function

2022-10-07 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64016?usp=email )


Change subject: stdlib: Add _post_instantiate function
..

stdlib: Add _post_instantiate function

This function will be called on the board after m5.instantiate is
called. This is useful, for instance, to start traffic generators.
Currently all implementations simply `pass`.

Change-Id: Ie2ab3fdddca5f3978d98191e5c08504561587fbb
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64016
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/abstract_board.py
M src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py
M src/python/gem5/components/memory/abstract_memory_system.py
M src/python/gem5/components/processors/abstract_processor.py
M src/python/gem5/simulate/simulator.py
5 files changed, 41 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index 1fe7902..fef1db0 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -338,3 +338,10 @@

 # Incorporate the processor into the motherboard.
 self.get_processor().incorporate_processor(self)
+
+def _post_instantiate(self):
+"""Called to set up anything needed after m5.instantiate"""
+self.get_processor()._post_instantiate()
+if self.get_cache_hierarchy():
+self.get_cache_hierarchy()._post_instantiate()
+self.get_memory()._post_instantiate()
diff --git  
a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py

index 5f6096e..8d59a38 100644
---  
a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py

@@ -70,3 +70,7 @@
 :returns: True if the cache hierarchy is ruby. Otherwise False.
 """
 raise NotImplementedError
+
+def _post_instantiate(self):
+"""Called to set up anything needed after m5.instantiate"""
+pass
diff --git a/src/python/gem5/components/memory/abstract_memory_system.py  
b/src/python/gem5/components/memory/abstract_memory_system.py

index 27bc152..cfbf6ac 100644
--- a/src/python/gem5/components/memory/abstract_memory_system.py
+++ b/src/python/gem5/components/memory/abstract_memory_system.py
@@ -71,3 +71,7 @@
 will be raised.
 """
 raise NotImplementedError
+
+def _post_instantiate(self) -> None:
+"""Called to set up anything needed after m5.instantiate"""
+pass
diff --git a/src/python/gem5/components/processors/abstract_processor.py  
b/src/python/gem5/components/processors/abstract_processor.py

index 72fa5db..a0f8b5c 100644
--- a/src/python/gem5/components/processors/abstract_processor.py
+++ b/src/python/gem5/components/processors/abstract_processor.py
@@ -74,3 +74,7 @@
 @abstractmethod
 def incorporate_processor(self, board: AbstractBoard) -> None:
 raise NotImplementedError
+
+def _post_instantiate(self) -> None:
+"""Called to set up anything needed after m5.instantiate"""
+pass
diff --git a/src/python/gem5/simulate/simulator.py  
b/src/python/gem5/simulate/simulator.py

index f4edd51..34913b3 100644
--- a/src/python/gem5/simulate/simulator.py
+++ b/src/python/gem5/simulate/simulator.py
@@ -405,6 +405,10 @@
 m5.instantiate(self._checkpoint_path)
 self._instantiated = True

+# Let the board know that instantiate has been called so it  
can do

+# any final things.
+self._board._post_instantiate()
+
 def run(self, max_ticks: int = m5.MaxTick) -> None:
 """
 This function will start or continue the simulator run and handle  
exit


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Gerrit-Branch: develop
Gerrit-Change-Id: Ie2ab3fdddca5f3978d98191e5c08504561587fbb
Gerrit-Change-Number: 64016
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Allow cache_hierarchy to be optional

2022-10-07 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64015?usp=email )


Change subject: stdlib: Allow cache_hierarchy to be optional
..

stdlib: Allow cache_hierarchy to be optional

This changeset makes the cache_hierarchy optional on the board. This
will allow us to enable the TestBoard to have memory directly connected
to the traffic generator.

Change-Id: I62d310e74c43724ea38e3b71a4d91d9e06d6e855
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64015
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/python/gem5/components/boards/abstract_board.py
1 file changed, 30 insertions(+), 7 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index e480190..1fe7902 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -39,7 +39,7 @@
 VoltageDomain,
 )

-from typing import List
+from typing import List, Optional


 class AbstractBoard:
@@ -68,13 +68,15 @@
 clk_freq: str,
 processor: "AbstractProcessor",
 memory: "AbstractMemorySystem",
-cache_hierarchy: "AbstractCacheHierarchy",
+cache_hierarchy: Optional["AbstractCacheHierarchy"],
 ) -> None:
 """
 :param clk_freq: The clock frequency for this board.
 :param processor: The processor for this board.
 :param memory: The memory for this board.
-:param cache_hierarchy: The Cachie Hierarchy for this board.
+:param cache_hierarchy: The Cache Hierarchy for this board.
+In some boards caches can be optional. If  
so,

+that board must override `_connect_things`.
 """

 if not isinstance(self, System):
@@ -88,7 +90,9 @@
 # Set the processor, memory, and cache hierarchy.
 self.processor = processor
 self.memory = memory
-self.cache_hierarchy = cache_hierarchy
+self._cache_hierarchy = cache_hierarchy
+if cache_hierarchy is not None:
+self.cache_hierarchy = cache_hierarchy

 # This variable determines whether the board is to be executed in
 # full-system or syscall-emulation mode. This is set when the  
workload

@@ -119,12 +123,12 @@
 """
 return self.memory

-def get_cache_hierarchy(self) -> "AbstractCacheHierarchy":
+def get_cache_hierarchy(self) -> Optional["AbstractCacheHierarchy"]:
 """Get the cache hierarchy connected to the board.

 :returns: The cache hierarchy.
 """
-return self.cache_hierarchy
+return self._cache_hierarchy

 def get_cache_line_size(self) -> int:
 """Get the size of the cache line.
@@ -329,7 +333,8 @@
 self.get_memory().incorporate_memory(self)

 # Incorporate the cache hierarchy for the motherboard.
-self.get_cache_hierarchy().incorporate_cache(self)
+if self.get_cache_hierarchy():
+self.get_cache_hierarchy().incorporate_cache(self)

 # Incorporate the processor into the motherboard.
 self.get_processor().incorporate_processor(self)

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Gerrit-Change-Number: 64015
Gerrit-PatchSet: 3
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Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Update the default exit events and warning

2022-10-07 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64251?usp=email )


Change subject: stdlib: Update the default exit events and warning
..

stdlib: Update the default exit events and warning

This change updates the default actions taken when the user doesn't
specify generators for the exit events in the simulator. Rather than
defining default generators, this change makes the generators more
generic and gives a new decorator to mark them as default.

This change then updates the default generators in the simulator and
only makes some of them issue a default warning. For exit events such as
EXIT, the default will no longer print a warning.

Change-Id: I5552f52392f3aea577034ed278a9ff9e8b5b0b01
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64251
Reviewed-by: Zhantong Qiu 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/python/gem5/simulate/exit_event_generators.py
M src/python/gem5/simulate/simulator.py
2 files changed, 123 insertions(+), 89 deletions(-)

Approvals:
  Zhantong Qiu: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/simulate/exit_event_generators.py  
b/src/python/gem5/simulate/exit_event_generators.py

index cdd8800..fc99dba 100644
--- a/src/python/gem5/simulate/exit_event_generators.py
+++ b/src/python/gem5/simulate/exit_event_generators.py
@@ -24,6 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+from typing import Generator, Optional
 import m5.stats
 from ..components.processors.abstract_processor import AbstractProcessor
 from ..components.processors.switchable_processor import  
SwitchableProcessor

@@ -35,39 +36,37 @@
 """


-def defaultBehaviorWarning(type, effect):
-warn(
-"As no behavior was set by the user, default behavior is being  
carried"

-f" out.\n Type: {type} \n Detail: {effect} \n"
-)
+def warn_default_decorator(gen: Generator, type: str, effect: str):
+"""A decortator for generators which will print a warning that it is a
+default generator.
+"""
+
+def wrapped_generator(*args, **kw_args):
+warn(
+f"No behavior was set by the user for {type}."
+f" Default behavior is {effect}."
+)
+for value in gen(*args, **kw_args):
+yield value
+
+return wrapped_generator


-def default_exit_generator():
+def exit_generator():
 """
 A default generator for an exit event. It will return True, indicating  
that

 the Simulator run loop should exit.
 """
-defaultBehaviorWarning(
-"default_exit_generator",
-"A default generator for an exit event. It will return True, "
-"indicating that the Simulator run loop should exit.",
-)
 while True:
 yield True


-def default_switch_generator(processor: AbstractProcessor):
+def switch_generator(processor: AbstractProcessor):
 """
 A default generator for a switch exit event. If the processor is a
 SwitchableProcessor, this generator will switch it. Otherwise nothing  
will

 happen.
 """
-defaultBehaviorWarning(
-"default_switch_generator",
-"A default generator for a switch exit event.If the processor is  
a "
-"SwitchableProcessor, this generator will switch it. Otherwise  
nothing"

-" will happen.",
-)
 is_switchable = isinstance(processor, SwitchableProcessor)
 while True:
 if is_switchable:
@@ -76,50 +75,6 @@
 yield False


-def default_workbegin_generator():
-"""
-A default generator for a workbegin exit event. It will reset the
-simulation statistics.
-"""
-defaultBehaviorWarning(
-"default_workbegin_generator",
-"A default generator for a workbegin exit event. It will reset  
the "

-"simulation statistics.",
-)
-while True:
-m5.stats.reset()
-yield False
-
-
-def default_workend_generator():
-"""
-A default generator for a workend exit event. It will dump the  
simulation

-statistics.
-"""
-defaultBehaviorWarning(
-"default_workend_generator",
-"A default generator for a workend exit event. It will dump the "
-"simulation statistics.",
-)
-while True:
-m5.stats.dump()
-yield False
-
-
-def default_simpoint_generator():
-"""
-A default genera

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Update the default exit events and warning

2022-10-07 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64251?usp=email )



Change subject: stdlib: Update the default exit events and warning
..

stdlib: Update the default exit events and warning

This change updates the default actions taken when the user doesn't
specify generators for the exit events in the simulator. Rather than
defining default generators, this change makes the generators more
generic and gives a new decorator to mark them as default.

This change then updates the default generators in the simulator and
only makes some of them issue a default warning. For exit events such as
EXIT, the default will no longer print a warning.

Change-Id: I5552f52392f3aea577034ed278a9ff9e8b5b0b01
Signed-off-by: Jason Lowe-Power 
---
M src/python/gem5/simulate/exit_event_generators.py
M src/python/gem5/simulate/simulator.py
2 files changed, 119 insertions(+), 89 deletions(-)



diff --git a/src/python/gem5/simulate/exit_event_generators.py  
b/src/python/gem5/simulate/exit_event_generators.py

index cdd8800..fc99dba 100644
--- a/src/python/gem5/simulate/exit_event_generators.py
+++ b/src/python/gem5/simulate/exit_event_generators.py
@@ -24,6 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+from typing import Generator, Optional
 import m5.stats
 from ..components.processors.abstract_processor import AbstractProcessor
 from ..components.processors.switchable_processor import  
SwitchableProcessor

@@ -35,39 +36,37 @@
 """


-def defaultBehaviorWarning(type, effect):
-warn(
-"As no behavior was set by the user, default behavior is being  
carried"

-f" out.\n Type: {type} \n Detail: {effect} \n"
-)
+def warn_default_decorator(gen: Generator, type: str, effect: str):
+"""A decortator for generators which will print a warning that it is a
+default generator.
+"""
+
+def wrapped_generator(*args, **kw_args):
+warn(
+f"No behavior was set by the user for {type}."
+f" Default behavior is {effect}."
+)
+for value in gen(*args, **kw_args):
+yield value
+
+return wrapped_generator


-def default_exit_generator():
+def exit_generator():
 """
 A default generator for an exit event. It will return True, indicating  
that

 the Simulator run loop should exit.
 """
-defaultBehaviorWarning(
-"default_exit_generator",
-"A default generator for an exit event. It will return True, "
-"indicating that the Simulator run loop should exit.",
-)
 while True:
 yield True


-def default_switch_generator(processor: AbstractProcessor):
+def switch_generator(processor: AbstractProcessor):
 """
 A default generator for a switch exit event. If the processor is a
 SwitchableProcessor, this generator will switch it. Otherwise nothing  
will

 happen.
 """
-defaultBehaviorWarning(
-"default_switch_generator",
-"A default generator for a switch exit event.If the processor is  
a "
-"SwitchableProcessor, this generator will switch it. Otherwise  
nothing"

-" will happen.",
-)
 is_switchable = isinstance(processor, SwitchableProcessor)
 while True:
 if is_switchable:
@@ -76,50 +75,6 @@
 yield False


-def default_workbegin_generator():
-"""
-A default generator for a workbegin exit event. It will reset the
-simulation statistics.
-"""
-defaultBehaviorWarning(
-"default_workbegin_generator",
-"A default generator for a workbegin exit event. It will reset  
the "

-"simulation statistics.",
-)
-while True:
-m5.stats.reset()
-yield False
-
-
-def default_workend_generator():
-"""
-A default generator for a workend exit event. It will dump the  
simulation

-statistics.
-"""
-defaultBehaviorWarning(
-"default_workend_generator",
-"A default generator for a workend exit event. It will dump the "
-"simulation statistics.",
-)
-while True:
-m5.stats.dump()
-yield False
-
-
-def default_simpoint_generator():
-"""
-A default generator for SimPoints. It will do nothing.
-The Simulation run loop will continue after executing the behavior of  
the

-generator.
-"""
-defaultBehaviorWarning(
-"default_simpoint_generator",
-"A

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix variable not found error

2022-09-30 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64012?usp=email )


Change subject: scons: Fix variable not found error
..

scons: Fix variable not found error

Change-Id: I09708fea777a57a35e55409c8997ed0b25de2b46
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64012
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Melissa Jost 
---
M site_scons/gem5_scons/__init__.py
1 file changed, 15 insertions(+), 1 deletion(-)

Approvals:
  Melissa Jost: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index c958e22..7214876 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -264,7 +264,7 @@
 while path_dirs and path_dirs[-1] != "build":
 variant_dir = path_dirs.pop()
 if not path_dirs:
-error("No non-leaf 'build' dir found on target path.", t)
+error("No non-leaf 'build' dir found on target path.", target)

 return os.path.join("/", *path_dirs), variant_dir


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I09708fea777a57a35e55409c8997ed0b25de2b46
Gerrit-Change-Number: 64012
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Melissa Jost 
Gerrit-Reviewer: Melissa Jost 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add example memory traffic runscript

2022-09-30 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64018?usp=email )



Change subject: configs: Add example memory traffic runscript
..

configs: Add example memory traffic runscript

This simple example shows how to use the test board to test the
bandwidth for an HBM2 pair of pseudo channels

Change-Id: I6235d0cb11909f5b4cc6442e419496c77425ba37
Signed-off-by: Jason Lowe-Power 
---
A configs/example/gem5_library/memory_traffic.py
1 file changed, 123 insertions(+), 0 deletions(-)



diff --git a/configs/example/gem5_library/memory_traffic.py  
b/configs/example/gem5_library/memory_traffic.py

new file mode 100644
index 000..80eaa7d
--- /dev/null
+++ b/configs/example/gem5_library/memory_traffic.py
@@ -0,0 +1,110 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script is used for running a traffic generator connected to a memory
+device. It supports linear and random accesses with a configurable amount
+of write traffic.
+"""
+
+import argparse
+
+from m5.objects import MemorySize
+from gem5.components.boards.test_board import TestBoard
+
+from gem5.components.processors.linear_generator import LinearGenerator
+from gem5.components.processors.random_generator import RandomGenerator
+
+from gem5.components.memory.hbm import HighBandwidthMemory
+from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
+
+from gem5.simulate.simulator import Simulator
+
+
+def generator_factory(
+generator_class: str, rd_perc: int, mem_size: MemorySize
+):
+rd_perc = int(rd_perc)
+if rd_perc > 100 or rd_perc < 0:
+raise ValueError(
+"Read percentage has to be an " "integer number between 0 and  
100."

+)
+if generator_class == "LinearGenerator":
+return LinearGenerator(
+duration="1ms", rate="256GiB/s", max_addr=mem_size,  
rd_perc=rd_perc

+)
+elif generator_class == "RandomGenerator":
+return RandomGenerator(
+duration="1ms", rate="256GiB/s", max_addr=mem_size,  
rd_perc=rd_perc

+)
+else:
+raise ValueError(f"Unknown generator class {generator_class}")
+
+
+parser = argparse.ArgumentParser(
+description="A traffic generator that can be used to test a gem5 "
+"memory component."
+)
+
+parser.add_argument(
+"generator_class",
+type=str,
+help="The class of generator to use.",
+choices=[
+"LinearGenerator",
+"RandomGenerator",
+],
+)
+
+parser.add_argument(
+"read_percentage",
+type=int,
+help="Percentage of read requests in the generated traffic.",
+)
+
+args = parser.parse_args()
+
+# Single pair of HBM2 pseudo channels. This can be replaced with any
+# single ported memory device
+memory = HighBandwidthMemory(HBM_2000_4H_1x64, 1, 128)
+
+generator = generator_factory(
+args.generator_class, args.read_percentage, memory.get_size()
+)
+
+# We use the Test Board. This is a special board to run traffic generation
+# tasks. Can replace the cache_hierarchy with any hierarchy to simulate the
+# cache as well as the memory
+board = TestBoard(
+generator=generator,  # We pass the traffic g

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Add _post_instantiate function

2022-09-30 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64016?usp=email )



Change subject: stdlib: Add _post_instantiate function
..

stdlib: Add _post_instantiate function

This function will be called on the board after m5.instantiate is
called. This is useful, for instance, to start traffic generators.
Currently all implementations simply `pass`.

Change-Id: Ie2ab3fdddca5f3978d98191e5c08504561587fbb
Signed-off-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/abstract_board.py
M src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py
M src/python/gem5/components/memory/abstract_memory_system.py
M src/python/gem5/components/processors/abstract_processor.py
M src/python/gem5/simulate/simulator.py
5 files changed, 37 insertions(+), 0 deletions(-)



diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index 1ac31cb..8e3c3a4 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -338,3 +338,10 @@

 # Incorporate the processor into the motherboard.
 self.get_processor().incorporate_processor(self)
+
+def _post_instantiate(self):
+"""Called to set up anything needed after m5.instantiate"""
+self.get_processor()._post_instantiate()
+if self.get_cache_hierarchy():
+self.get_cache_hierarchy()._post_instantiate()
+self.get_memory()._post_instantiate()
diff --git  
a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py

index 5f6096e..8d59a38 100644
---  
a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py

@@ -70,3 +70,7 @@
 :returns: True if the cache hierarchy is ruby. Otherwise False.
 """
 raise NotImplementedError
+
+def _post_instantiate(self):
+"""Called to set up anything needed after m5.instantiate"""
+pass
diff --git a/src/python/gem5/components/memory/abstract_memory_system.py  
b/src/python/gem5/components/memory/abstract_memory_system.py

index 27bc152..cfbf6ac 100644
--- a/src/python/gem5/components/memory/abstract_memory_system.py
+++ b/src/python/gem5/components/memory/abstract_memory_system.py
@@ -71,3 +71,7 @@
 will be raised.
 """
 raise NotImplementedError
+
+def _post_instantiate(self) -> None:
+"""Called to set up anything needed after m5.instantiate"""
+pass
diff --git a/src/python/gem5/components/processors/abstract_processor.py  
b/src/python/gem5/components/processors/abstract_processor.py

index 72fa5db..a0f8b5c 100644
--- a/src/python/gem5/components/processors/abstract_processor.py
+++ b/src/python/gem5/components/processors/abstract_processor.py
@@ -74,3 +74,7 @@
 @abstractmethod
 def incorporate_processor(self, board: AbstractBoard) -> None:
 raise NotImplementedError
+
+def _post_instantiate(self) -> None:
+"""Called to set up anything needed after m5.instantiate"""
+pass
diff --git a/src/python/gem5/simulate/simulator.py  
b/src/python/gem5/simulate/simulator.py

index efa7c42..ad16220 100644
--- a/src/python/gem5/simulate/simulator.py
+++ b/src/python/gem5/simulate/simulator.py
@@ -381,6 +381,10 @@
 m5.instantiate(self._checkpoint_path)
 self._instantiated = True

+# Let the board know that instantiate has been called so it  
can do

+# any final things.
+self._board._post_instantiate()
+
 def run(self, max_ticks: int = m5.MaxTick) -> None:
 """
 This function will start or continue the simulator run and handle  
exit


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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Update TestBoard to work with Simulator

2022-09-30 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64017?usp=email )



Change subject: stdlib: Update TestBoard to work with Simulator
..

stdlib: Update TestBoard to work with Simulator

This change makes minor updates to the TestBoard so that it can work
nicely with the Simulator module.

This change also makes the cache hierarchy optional for the TestBoard.

Change-Id: If46d53779164e87b6fc06176355be6b4ae05aa99
Signed-off-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/test_board.py
M src/python/gem5/components/processors/abstract_generator.py
M src/python/gem5/simulate/exit_event.py
3 files changed, 45 insertions(+), 8 deletions(-)



diff --git a/src/python/gem5/components/boards/test_board.py  
b/src/python/gem5/components/boards/test_board.py

index 7267f2a..eca8c61 100644
--- a/src/python/gem5/components/boards/test_board.py
+++ b/src/python/gem5/components/boards/test_board.py
@@ -26,15 +26,15 @@

 from m5.objects import Port, IOXBar, AddrRange

-from .mem_mode import MemMode, mem_mode_to_string
 from ...utils.override import overrides
+from .abstract_board import AbstractBoard
 from .abstract_system_board import AbstractSystemBoard
-from ..processors.abstract_processor import AbstractProcessor
+from ..processors.abstract_generator import AbstractGenerator
 from ..memory.abstract_memory_system import AbstractMemorySystem
 from ..cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy



-from typing import List
+from typing import List, Optional


 class TestBoard(AbstractSystemBoard):
@@ -43,21 +43,24 @@
 architecture.

 To work as a traffic generator board, pass a generator as a processor.
+
+This board does not require a cache hierarchy (it can be none) in which
+case the processor (generator) will be directly connected to the  
memory.

 """

 def __init__(
 self,
-clk_freq: str,
-processor: AbstractProcessor,
+generator: AbstractGenerator,
 memory: AbstractMemorySystem,
-cache_hierarchy: AbstractCacheHierarchy,
+cache_hierarchy: Optional[AbstractCacheHierarchy],
 ):
 super().__init__(
-clk_freq=clk_freq,
-processor=processor,
+clk_freq="1GHz",  # Clock frequency is ignored
+processor=generator,
 memory=memory,
 cache_hierarchy=cache_hierarchy,
 )
+self._set_fullsystem(False)

 @overrides(AbstractSystemBoard)
 def _setup_board(self) -> None:
@@ -108,3 +111,16 @@
 @overrides(AbstractSystemBoard)
 def has_dma_ports(self) -> bool:
 return False
+
+@overrides(AbstractBoard)
+def _connect_things(self) -> None:
+super()._connect_things()
+
+if not self.get_cache_hierarchy():
+# If we have no caches, then there must be a one-to-one
+# connection between the generators and the memories.
+assert len(self.get_processor().get_cores()) == 1
+assert len(self.get_memory().get_mem_ports()) == 1
+self.get_processor().get_cores()[
+0
+].generator.port = self.get_memory().get_mem_ports()[0][1]
diff --git a/src/python/gem5/components/processors/abstract_generator.py  
b/src/python/gem5/components/processors/abstract_generator.py

index 41cbf5c..ff5387d 100644
--- a/src/python/gem5/components/processors/abstract_generator.py
+++ b/src/python/gem5/components/processors/abstract_generator.py
@@ -65,3 +65,6 @@
 this method needs to be implemented in detail or implmeneted as  
pass.

 """
 raise NotImplementedError
+
+def _post_instantiate(self) -> None:
+self.start_traffic()
diff --git a/src/python/gem5/simulate/exit_event.py  
b/src/python/gem5/simulate/exit_event.py

index 691e41a..29d434c 100644
--- a/src/python/gem5/simulate/exit_event.py
+++ b/src/python/gem5/simulate/exit_event.py
@@ -87,6 +87,9 @@
 return ExitEvent.SIMPOINT_BEGIN
 elif exit_string == "a thread reached the max instruction count":
 return ExitEvent.MAX_INSTS
+elif exit_string.endswith("will terminate the simulation.\n"):
+# This is for the traffic generator exit event
+return ExitEvent.EXIT
 raise NotImplementedError(
 "Exit event '{}' not implemented".format(exit_string)
 )

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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Allow cache_hierarchy to be optional

2022-09-30 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64015?usp=email )



Change subject: stdlib: Allow cache_hierarchy to be optional
..

stdlib: Allow cache_hierarchy to be optional

This changeset makes the cache_hierarchy optional on the board. This
will allow us to enable the TestBoard to have memory directly connected
to the traffic generator.

Change-Id: I62d310e74c43724ea38e3b71a4d91d9e06d6e855
Signed-off-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/abstract_board.py
1 file changed, 25 insertions(+), 6 deletions(-)



diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index e480190..1ac31cb 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -39,7 +39,7 @@
 VoltageDomain,
 )

-from typing import List
+from typing import List, Optional


 class AbstractBoard:
@@ -68,13 +68,15 @@
 clk_freq: str,
 processor: "AbstractProcessor",
 memory: "AbstractMemorySystem",
-cache_hierarchy: "AbstractCacheHierarchy",
+cache_hierarchy: Optional["AbstractCacheHierarchy"],
 ) -> None:
 """
 :param clk_freq: The clock frequency for this board.
 :param processor: The processor for this board.
 :param memory: The memory for this board.
-:param cache_hierarchy: The Cachie Hierarchy for this board.
+:param cache_hierarchy: The Cache Hierarchy for this board.
+In some boards caches can be optional. If  
so,

+that board must override `_connect_things`.
 """

 if not isinstance(self, System):
@@ -88,7 +90,9 @@
 # Set the processor, memory, and cache hierarchy.
 self.processor = processor
 self.memory = memory
-self.cache_hierarchy = cache_hierarchy
+self._cache_hierarchy = cache_hierarchy
+if cache_hierarchy is not None:
+self.cache_hierarchy = cache_hierarchy

 # This variable determines whether the board is to be executed in
 # full-system or syscall-emulation mode. This is set when the  
workload

@@ -124,7 +128,7 @@

 :returns: The cache hierarchy.
 """
-return self.cache_hierarchy
+return self._cache_hierarchy

 def get_cache_line_size(self) -> int:
 """Get the size of the cache line.
@@ -329,7 +333,8 @@
 self.get_memory().incorporate_memory(self)

 # Incorporate the cache hierarchy for the motherboard.
-self.get_cache_hierarchy().incorporate_cache(self)
+if self.get_cache_hierarchy():
+self.get_cache_hierarchy().incorporate_cache(self)

 # Incorporate the processor into the motherboard.
 self.get_processor().incorporate_processor(self)

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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix variable not found error

2022-09-30 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64012?usp=email )



Change subject: scons: Fix variable not found error
..

scons: Fix variable not found error

Change-Id: I09708fea777a57a35e55409c8997ed0b25de2b46
Signed-off-by: Jason Lowe-Power 
---
M site_scons/gem5_scons/__init__.py
1 file changed, 11 insertions(+), 1 deletion(-)



diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index c958e22..7214876 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -264,7 +264,7 @@
 while path_dirs and path_dirs[-1] != "build":
 variant_dir = path_dirs.pop()
 if not path_dirs:
-error("No non-leaf 'build' dir found on target path.", t)
+error("No non-leaf 'build' dir found on target path.", target)

 return os.path.join("/", *path_dirs), variant_dir


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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix error in Arm test

2022-09-30 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63991?usp=email )


Change subject: tests: Fix error in Arm test
..

tests: Fix error in Arm test

I missed this one in the last changeset.

Change-Id: I71d7fa2ac4ff36d4aef5d950e6ed8973ffc32a4e
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63991
Maintainer: Giacomo Travaglini 
Reviewed-by: Melissa Jost 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M tests/gem5/configs/realview64-switcheroo-full.py
1 file changed, 18 insertions(+), 1 deletion(-)

Approvals:
  Melissa Jost: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/realview64-switcheroo-full.py  
b/tests/gem5/configs/realview64-switcheroo-full.py

index abc96f9..0209578 100644
--- a/tests/gem5/configs/realview64-switcheroo-full.py
+++ b/tests/gem5/configs/realview64-switcheroo-full.py
@@ -43,7 +43,7 @@
 ArmAtomicSimpleCPU,
 ArmTimingSimpleCPU,
 ArmMinorCPU,
-ArmDerivO3CPU,
+ArmO3CPU,
 ),
 ).create_root()


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Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix error in Arm test

2022-09-29 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63991?usp=email )



Change subject: tests: Fix error in Arm test
..

tests: Fix error in Arm test

I missed this one in the last changeset.

Change-Id: I71d7fa2ac4ff36d4aef5d950e6ed8973ffc32a4e
Signed-off-by: Jason Lowe-Power 
---
M tests/gem5/configs/realview64-switcheroo-full.py
1 file changed, 13 insertions(+), 1 deletion(-)



diff --git a/tests/gem5/configs/realview64-switcheroo-full.py  
b/tests/gem5/configs/realview64-switcheroo-full.py

index abc96f9..0209578 100644
--- a/tests/gem5/configs/realview64-switcheroo-full.py
+++ b/tests/gem5/configs/realview64-switcheroo-full.py
@@ -43,7 +43,7 @@
 ArmAtomicSimpleCPU,
 ArmTimingSimpleCPU,
 ArmMinorCPU,
-ArmDerivO3CPU,
+ArmO3CPU,
 ),
 ).create_root()


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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Move the arm+ruby tests to not use ALL

2022-09-27 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63852?usp=email )


Change subject: tests: Move the arm+ruby tests to not use ALL
..

tests: Move the arm+ruby tests to not use ALL

The main Ruby.py script does not support the ALL target (it still
depends on get_runtime_isa). So, instead of testing these with the all
target, move them to be tested with just Arm built.

Change-Id: I7942177fffd2bbfb0696b67c1e94e2ec30d8178b
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63852
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Bobby Bruce 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 43 insertions(+), 4 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index dff2e74..8700247 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -73,10 +73,6 @@
 "realview64-minor-dual",
 "realview64-switcheroo-o3",
 "realview64-switcheroo-full",
-"realview-simple-timing-ruby",
-"realview64-simple-timing-ruby",
-"realview64-simple-timing-dual-ruby",
-"realview64-o3-dual-ruby",
 # The following tests fail. These are recorded in the GEM5-640
 # Jira issue.
 #
@@ -88,6 +84,14 @@
 #'realview-simple-timing-dual-ruby',
 ]

+# These tests are Ruby-based and Ruby does not support multiple ISAs
+arm_fs_long_tests_arm_target = [
+"realview-simple-timing-ruby",
+"realview64-simple-timing-ruby",
+"realview64-simple-timing-dual-ruby",
+"realview64-o3-dual-ruby",
+]
+
 tarball = "aarch-system-20220707.tar.bz2"
 url = config.resource_url + "/arm/" + tarball
 filepath = os.path.dirname(os.path.abspath(__file__))
@@ -157,3 +161,20 @@
 fixtures=(arm_fs_binaries,),
 uses_kvm=name in arm_fs_kvm_tests,
 )
+
+for name in arm_fs_long_tests_arm_target:
+args = [
+joinpath(config.base_dir, "tests", "gem5", "configs", name  
+ ".py"),

+path,
+config.base_dir,
+]
+gem5_verify_config(
+name=name,
+verifiers=verifier_list(name),  # TODO: Add basic stat verifiers
+config=joinpath(filepath, "run.py"),
+config_args=args,
+valid_isas=(constants.arm_tag,),
+length=constants.long_tag,
+fixtures=(arm_fs_binaries,),
+uses_kvm=name in arm_fs_kvm_tests,
+)

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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix errors in arm switcheroo

2022-09-26 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63851?usp=email )


Change subject: tests: Fix errors in arm switcheroo
..

tests: Fix errors in arm switcheroo

When switching to the all target, there is no longer a "DerivO3CPU" we
now need to drop the "Deriv"

Note that there are still some cases where it is valid to use "DerivO3"
where it is converted to drop the "Deriv" via a map.

Cleaning this up further is for future work.

Change-Id: Ide59eb3a5c7daf15c13afe395409f588562c1b54
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63851
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Giacomo Travaglini 
Reviewed-by: Giacomo Travaglini 
---
M tests/gem5/configs/realview-switcheroo-o3.py
M tests/gem5/configs/realview64-switcheroo-o3.py
2 files changed, 25 insertions(+), 2 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/tests/gem5/configs/realview-switcheroo-o3.py  
b/tests/gem5/configs/realview-switcheroo-o3.py

index fe3298f..4fca57e 100644
--- a/tests/gem5/configs/realview-switcheroo-o3.py
+++ b/tests/gem5/configs/realview-switcheroo-o3.py
@@ -41,7 +41,7 @@
 aarch64_kernel=False,
 machine_type="VExpress_GEM5_V1",
 mem_class=DDR3_1600_8x8,
-cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU),
+cpu_classes=(ArmO3CPU, ArmO3CPU),
 ).create_root()

 # Setup a custom test method that uses the switcheroo tester that
diff --git a/tests/gem5/configs/realview64-switcheroo-o3.py  
b/tests/gem5/configs/realview64-switcheroo-o3.py

index ddfc73a..f899337 100644
--- a/tests/gem5/configs/realview64-switcheroo-o3.py
+++ b/tests/gem5/configs/realview64-switcheroo-o3.py
@@ -38,7 +38,7 @@
 import switcheroo

 root = LinuxArmFSSwitcheroo(
-mem_class=DDR3_1600_8x8, cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU)
+mem_class=DDR3_1600_8x8, cpu_classes=(ArmO3CPU, ArmO3CPU)
 ).create_root()

 # Setup a custom test method that uses the switcheroo tester that

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ide59eb3a5c7daf15c13afe395409f588562c1b54
Gerrit-Change-Number: 63851
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Move the arm+ruby tests to not use ALL

2022-09-26 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63852?usp=email )



Change subject: tests: Move the arm+ruby tests to not use ALL
..

tests: Move the arm+ruby tests to not use ALL

The main Ruby.py script does not support the ALL target (it still
depends on get_runtime_isa). So, instead of testing these with the all
target, move them to be tested with just Arm built.

Change-Id: I7942177fffd2bbfb0696b67c1e94e2ec30d8178b
Signed-off-by: Jason Lowe-Power 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 39 insertions(+), 4 deletions(-)



diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index dff2e74..8700247 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -73,10 +73,6 @@
 "realview64-minor-dual",
 "realview64-switcheroo-o3",
 "realview64-switcheroo-full",
-"realview-simple-timing-ruby",
-"realview64-simple-timing-ruby",
-"realview64-simple-timing-dual-ruby",
-"realview64-o3-dual-ruby",
 # The following tests fail. These are recorded in the GEM5-640
 # Jira issue.
 #
@@ -88,6 +84,14 @@
 #'realview-simple-timing-dual-ruby',
 ]

+# These tests are Ruby-based and Ruby does not support multiple ISAs
+arm_fs_long_tests_arm_target = [
+"realview-simple-timing-ruby",
+"realview64-simple-timing-ruby",
+"realview64-simple-timing-dual-ruby",
+"realview64-o3-dual-ruby",
+]
+
 tarball = "aarch-system-20220707.tar.bz2"
 url = config.resource_url + "/arm/" + tarball
 filepath = os.path.dirname(os.path.abspath(__file__))
@@ -157,3 +161,20 @@
 fixtures=(arm_fs_binaries,),
 uses_kvm=name in arm_fs_kvm_tests,
 )
+
+for name in arm_fs_long_tests_arm_target:
+args = [
+joinpath(config.base_dir, "tests", "gem5", "configs", name  
+ ".py"),

+path,
+config.base_dir,
+]
+gem5_verify_config(
+name=name,
+verifiers=verifier_list(name),  # TODO: Add basic stat verifiers
+config=joinpath(filepath, "run.py"),
+config_args=args,
+valid_isas=(constants.arm_tag,),
+length=constants.long_tag,
+fixtures=(arm_fs_binaries,),
+uses_kvm=name in arm_fs_kvm_tests,
+)

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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix errors in arm switcheroo

2022-09-26 Thread Jason Lowe-Power (Gerrit)
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63851?usp=email )



Change subject: tests: Fix errors in arm switcheroo
..

tests: Fix errors in arm switcheroo

When switching to the all target, there is no longer a "DerivO3CPU" we
now need to drop the "Deriv"

Note that there are still some cases where it is valid to use "DerivO3"
where it is converted to drop the "Deriv" via a map.

Cleaning this up further is for future work.

Change-Id: Ide59eb3a5c7daf15c13afe395409f588562c1b54
Signed-off-by: Jason Lowe-Power 
---
M tests/gem5/configs/realview-switcheroo-o3.py
M tests/gem5/configs/realview64-switcheroo-o3.py
2 files changed, 20 insertions(+), 2 deletions(-)



diff --git a/tests/gem5/configs/realview-switcheroo-o3.py  
b/tests/gem5/configs/realview-switcheroo-o3.py

index fe3298f..4fca57e 100644
--- a/tests/gem5/configs/realview-switcheroo-o3.py
+++ b/tests/gem5/configs/realview-switcheroo-o3.py
@@ -41,7 +41,7 @@
 aarch64_kernel=False,
 machine_type="VExpress_GEM5_V1",
 mem_class=DDR3_1600_8x8,
-cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU),
+cpu_classes=(ArmO3CPU, ArmO3CPU),
 ).create_root()

 # Setup a custom test method that uses the switcheroo tester that
diff --git a/tests/gem5/configs/realview64-switcheroo-o3.py  
b/tests/gem5/configs/realview64-switcheroo-o3.py

index ddfc73a..f899337 100644
--- a/tests/gem5/configs/realview64-switcheroo-o3.py
+++ b/tests/gem5/configs/realview64-switcheroo-o3.py
@@ -38,7 +38,7 @@
 import switcheroo

 root = LinuxArmFSSwitcheroo(
-mem_class=DDR3_1600_8x8, cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU)
+mem_class=DDR3_1600_8x8, cpu_classes=(ArmO3CPU, ArmO3CPU)
 ).create_root()

 # Setup a custom test method that uses the switcheroo tester that

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Gerrit-Project: public/gem5
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Gerrit-Change-Number: 63851
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Build failed in Jenkins: nightly #348

2022-09-09 Thread Jason Lowe-Power
Hi all,

I'm not sure what the underlying cause is here. We keep getting errors that
look something like the one causing this failure (shown below). They are
all "ModuleNotFound" errors on modules that are definitely there! I've also
seen this happen where I get an error when trying to access a variable
within a module (e.g., `system = System()` produces an error something like
"System is a module...")

> ModuleNotFoundError: No module named 'gem5.resource'

We have been able to "fix" it by deleting the build directory. However, I'm
pretty sure we did that with the nightlies a few days ago.

This started happening after this relation chain from Gabe was merged:
https://gem5-review.googlesource.com/c/public/gem5/+/62201

At least, that relation chain was the biggest change around the time we
started seeing the error. It's hard to tell because when that was merged we
were having other nightly test failures.

Ideas on what could be going on would be appreciated. We'll delete the
build directory and try again in the meantime.

Cheers,
Jason

On Fri, Sep 9, 2022 at 4:40 AM  wrote:

> See <
> https://jenkins.gem5.org/job/nightly/348/display/redirect?page=changes>
>
> Changes:
>
> [Bobby R. Bruce] tests,configs: Update x86 boot tests/examples with
> Workload
>
> [Bobby R. Bruce] configs,tests: Update tests/configs for RISCV boot
> workload
>
> [Bobby R. Bruce] configs: Use "arm64-ubuntu-20.04-boot" workload for
> example
>
> [Bobby R. Bruce] scons: Ensure style_hooks check exits if hook cannot
> install
>
> [matthew.poremba] dev-amdgpu: Remove default callback in mem manager API
>
> [matthew.poremba] configs: Stop disabling SDMA in GPUFS config
>
> [matthew.poremba] dev-amdgpu: Add SDMA device translation helper
>
> [matthew.poremba] dev-amdgpu: Place all user-mode translations in MMHUB
>
> [matthew.poremba] dev-amdgpu: Add user-mode TranslationGen to SDMA
>
> [matthew.poremba] dev-amdgpu: Forward RLC queue doorbells
>
> [matthew.poremba] arch-vega: Allow unaligned large host pages
>
> [matthew.poremba] dev-amdgpu: Rework framebuffer reads
>
> [matthew.poremba] dev-amdgpu: Rework SDMA RLC queue data structure
>
> [matthew.poremba] dev-amdgpu: Implement SDMA RLC queue unmapping
>
> [matthew.poremba] dev-amdgpu: Implement SDMA atomic packet
>
> [matthew.poremba] arch-vega: Improve disasm for GLOBAL insts with scalar
> offset
>
> [matthew.poremba] gpu-compute: dprint instruction requesting translation
>
> [matthew.poremba] dev-amdgpu: Fix interrupt call for release mem
>
>
> --
> [...truncated 1.67 MB...]
> Test:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outfadf52u6 -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGenerator 1 MESITwoLevel gem5.components.memory SingleChannelDDR3_2133
> 512MiB
> Starting Test Suite:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outpf3rir7c -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGenerator 1 MESITwoLevel gem5.components.memory SingleChannelDDR4_2400
> 512MiB
> Starting Test Suite:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outq36vpo96 -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGenerator 1 MESITwoLevel gem5.components.memory
> SingleChannelLPDDR3_1600 512MiB
> Starting Test Suite:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI

[gem5-dev] Re: Build failed in Jenkins: nightly #331

2022-08-25 Thread Jason Lowe-Power
Hey Bobby,

I think this has to do with with new "workload" type in the resources. The
error that we're getting in a bunch of runs is

Exception: Error: Unknown type 'workload'.

At:
  build/X86/python/gem5/resources/downloader.py(223): _get_resources
  build/X86/python/gem5/resources/downloader.py(335): get_resources_json_obj
  build/X86/python/gem5/resources/resource.py(168): __init__

/nobackup/jenkins/workspace/nightly/configs/example/gem5_library/x86-ubuntu-run.py(60):

  build/X86/python/m5/main.py(574): main

On Thu, Aug 25, 2022 at 3:13 AM  wrote:

> See <
> https://jenkins.gem5.org/job/nightly/331/display/redirect?page=changes>
>
> Changes:
>
> [mattdsinclair] configs: Add default to max_cu_tokens CLA
>
> [Bobby R. Bruce] misc: Add the legacy gem5 .git/hooks to the pre-commit
>
> [Bobby R. Bruce] misc: Exclude test ref directories from pre-commit
>
> [Bobby R. Bruce] misc: Run pre-commit run on all files in repo
>
> [Bobby R. Bruce] python: Add 'requirements.txt'
>
> [Bobby R. Bruce] scons: Update automatic hook install for pre-commit
>
> [Bobby R. Bruce] misc: Update CONTRIBUTING.md for `pre-commit`
>
> [Bobby R. Bruce] misc: Add gerrit commit message hook to pre-commit
>
> [yiwkd2] stdlib: Minor typo fixed
>
>
> --
> [...truncated 3.51 MB...]
> Starting Test Case:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5out1tlh9bhh -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGeneratorPAR 2 MESITwoLevel gem5.components.memory
> SingleChannelDDR4_2400 512MiB
> Starting Test Suite:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5out5ein48af -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGeneratorPAR 2 MESITwoLevel gem5.components.memory
> SingleChannelLPDDR3_1600 512MiB
> Starting Test Suite:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outbs6suukc -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGeneratorPAR 2 MESITwoLevel gem5.components.memory SingleChannelHBM
> 512MiB
> Starting Test Suite:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelHBM-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelHBM-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-SingleChannelHBM-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outv0k5k81e -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGeneratorPAR 2 MESITwoLevel gem5.components.memory DualChannelDDR3_1600
> 512MiB
> Starting Test Suite:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-DualChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGeneratorPAR-2-MESITwoLevel-gem5.components.memory-DualChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test: realview-switcheroo-timing-ARM-x86_64-opt Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/ARM/gem5.opt -d
> /tmp/gem5outag5a01zb -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/fs/linux/arm/run.py
> /nobackup/jenkins/workspace/nightly/tests/gem5/configs/realview-o3.py
> /nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm
> /nobackup/jenkins/workspace/nightly
> Starting Test Suite: realv

[gem5-dev] Re: Build failed in Jenkins: nightly #329

2022-08-23 Thread Jason Lowe-Power
I believe the culprit is this change:
https://gem5-review.googlesource.com/c/public/gem5/+/62551

Matt, if you could take a look, I'd appreciate it!

Cheers,
Jason

On Tue, Aug 23, 2022 at 4:53 PM  wrote:

> See <
> https://jenkins.gem5.org/job/nightly/329/display/redirect?page=changes>
>
> Changes:
>
> [c] arch-arm: Switch from getVec* to getReg* accessor.
>
> [c] misc: Fix dynamic decision of TranslatingPortProxy.
>
> [mattdsinclair] configs: Add CLA for max_cu_tokens to apu_se.py
>
>
> --
> [...truncated 1.84 MB...]
>  [ CXX] GCN3_X86/dev/net/etherlink.cc -> .o
>  [ CXX] GCN3_X86/dev/net/etherpkt.cc -> .o
>  [ CXX] GCN3_X86/dev/net/ethertap.cc -> .o
>  [ CXX] GCN3_X86/dev/net/pktfifo.cc -> .o
>  [ CXX] GCN3_X86/debug/Ethernet.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetCksum.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetDMA.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetData.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetDesc.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetEEPROM.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetIntr.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetPIO.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetSM.cc -> .o
>  [ CXX] GCN3_X86/dev/net/dist_iface.cc -> .o
>  [ CXX] GCN3_X86/dev/net/dist_etherlink.cc -> .o
>  [ CXX] GCN3_X86/dev/net/tcp_iface.cc -> .o
>  [ CXX] GCN3_X86/debug/DistEthernet.cc -> .o
>  [ CXX] GCN3_X86/debug/DistEthernetPkt.cc -> .o
>  [ CXX] GCN3_X86/debug/DistEthernetCmd.cc -> .o
>  [ CXX] GCN3_X86/dev/net/i8254xGBe.cc -> .o
>  [ CXX] GCN3_X86/dev/net/ns_gige.cc -> .o
>  [ CXX] GCN3_X86/dev/net/sinic.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetAll.cc -> .o
>  [ CXX] GCN3_X86/debug/EthernetNoData.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/AMDGPU.py.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_AMDGPUDevice.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_AMDGPUInterruptHandler.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_AMDGPUMemoryManager.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_AMDGPUSystemHub.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_SDMAEngine.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_PM4PacketProcessor.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/amdgpu_device.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/amdgpu_vm.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/interrupt_handler.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/memory_manager.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/mmio_reader.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/pm4_packet_processor.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/sdma_engine.cc -> .o
>  [ CXX] GCN3_X86/dev/amdgpu/system_hub.cc -> .o
>  [ CXX] GCN3_X86/debug/AMDGPUDevice.cc -> .o
>  [ CXX] GCN3_X86/debug/AMDGPUMem.cc -> .o
>  [ CXX] GCN3_X86/debug/PM4PacketProcessor.cc -> .o
>  [ CXX] GCN3_X86/debug/SDMAEngine.cc -> .o
>  [ CXX] GCN3_X86/dev/ps2/PS2.py.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_PS2Device.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_PS2Keyboard.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_PS2Mouse.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_PS2TouchKit.cc -> .o
>  [ CXX] GCN3_X86/dev/ps2/device.cc -> .o
>  [ CXX] GCN3_X86/dev/ps2/keyboard.cc -> .o
>  [ CXX] GCN3_X86/dev/ps2/mouse.cc -> .o
>  [ CXX] GCN3_X86/dev/ps2/touchkit.cc -> .o
>  [ CXX] GCN3_X86/dev/ps2/types.cc -> .o
>  [ CXX] GCN3_X86/debug/PS2.cc -> .o
>  [ CXX] GCN3_X86/dev/qemu/QemuFwCfg.py.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_QemuFwCfgItem.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_QemuFwCfgItemBytes.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_QemuFwCfgItemFile.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_QemuFwCfgItemString.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_QemuFwCfg.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_QemuFwCfgIo.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_QemuFwCfgMmio.cc -> .o
>  [ CXX] GCN3_X86/dev/qemu/fw_cfg.cc -> .o
>  [ CXX] GCN3_X86/debug/QemuFwCfg.cc -> .o
>  [ CXX] GCN3_X86/debug/QemuFwCfgVerbose.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/Serial.py.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_SerialDevice.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_SerialNullDevice.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/Terminal.py.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_Terminal.cc -> .o
>  [ CXX] GCN3_X86/enums/TerminalDump.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/Uart.py.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_Uart.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_SimpleUart.cc -> .o
>  [ CXX] GCN3_X86/python/_m5/param_Uart8250.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/serial.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/simple.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/terminal.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/uart.cc -> .o
>  [ CXX] GCN3_X86/dev/serial/uart8250.cc -> .o
>  [ CXX] GCN3_X86/debug/Terminal.cc -> .o
>  [ CXX] GCN3_X86/d

[gem5-dev] Re: Build failed in Jenkins: nightly #324

2022-08-19 Thread Jason Lowe-Power
Hey Bobby,

I think that one of the stdlib changes requires updating the boot-exit
test. The Arm boot exit test failed with the following output.

AttributeError: 'NoneType' object has no attribute 'name'

At:
  build/ARM/python/gem5/components/processors/simple_core.py(90):
cpu_simobject_factory
  build/ARM/python/gem5/components/processors/simple_core.py(47): __init__
  build/ARM/python/gem5/components/processors/simple_processor.py(58):

  build/ARM/python/gem5/components/processors/simple_processor.py(57):
__init__

/nobackup/jenkins/workspace/nightly/configs/example/gem5_library/arm-ubuntu-boot-exit.py(79):

  build/ARM/python/m5/main.py(574): main

On Thu, Aug 18, 2022 at 4:21 PM  wrote:

> See <
> https://jenkins.gem5.org/job/nightly/324/display/redirect?page=changes>
>
> Changes:
>
> [Giacomo Travaglini] mem-ruby: Replace deprecated Stats namespace with
> statistics
>
> [Giacomo Travaglini] arch-arm: XPACD, XPACI, XPACLRI do not trap
>
> [Jason Lowe-Power] tests: Remove functional tests from Garnet
>
> [Bobby R. Bruce] stdlib: Remove "CPUType" from AbstractCore
>
> [Bobby R. Bruce] stdlib: Create BaseCPUCore type
>
> [Bobby R. Bruce] stdlib: Add "is_kvm_core" function to AbstractCore
>
> [Bobby R. Bruce] stdlib: Add "requires_send_evicts" function to
> AbstractCore
>
> [Bobby R. Bruce] stdlib,tests: Add BaseCPUProcessor to stdlib
>
>
> --
> [...truncated 2.37 MB...]
> Starting Test Suite:
> test-memory-RandomGenerator-1-MESITwoLevel-gem5.components.memory-HBM2Stack-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-RandomGenerator-1-MESITwoLevel-gem5.components.memory-HBM2Stack-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-RandomGenerator-1-MESITwoLevel-gem5.components.memory-HBM2Stack-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outuao40yaj -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGenerator 1 MESITwoLevel gem5.components.memory SingleChannelDDR3_1600
> 512MiB
> Starting Test Suite:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outx66a5xzq -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGenerator 1 MESITwoLevel gem5.components.memory SingleChannelDDR3_2133
> 512MiB
> Starting Test Suite:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5out718ioxg1 -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGenerator 1 MESITwoLevel gem5.components.memory SingleChannelDDR4_2400
> 512MiB
> Starting Test Suite:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5out8yh5ll4e -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> GUPSGenerator 1 MESITwoLevel gem5.components.memory
> SingleChannelLPDDR3_1600 512MiB
> Starting Test Suite:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-GUPSGenerator-1-MESITwoLevel-gem5.

[gem5-dev] Re: Build failed in Jenkins: weekly #64

2022-07-25 Thread Jason Lowe-Power
The failure is in the " Test: test-resource-downloading-NULL-x86_64-opt "
with  "Exception: Failure to download resource 'riscv-hello'."

Did we move that resource?

Cheers,
Jason

On Fri, Jul 22, 2022 at 1:50 PM  wrote:

> See 
>
> Changes:
>
> [matthew.poremba] arch-vega: Implement new VOP2 using VOP3 insts
>
> [Bobby R. Bruce] stdlib: se_binary_workload exits on work items by default
>
> [mattdsinclair.wisc] mem-ruby, gpu-compute: update TCP_latency comment
>
> [matthew.poremba] arch-vega,arch-gcn3: Add support for VCC_HI as scalar
> source
>
> [alexandru.dutu] gpu-compute: Fix for HSA queue remapping
>
> [fcrh] arch-riscv: Make WFI halt the hart
>
> [yazakram] mem: Add getAddrRanges in HBMCtrl
>
> [yazakram] mem: Update the default HBMCtrl config
>
> [mattdsinclair] mem-ruby, gpu-compute: Add mandatory_queue_latency input
> option
>
> [jporquet] dev: Fix cpu/reg decoding logic in multi-instance LupIO devices
>
> [jporquet] dev: update LupIO-IPI device to latest specs
>
> [jporquet] python: swap memory addresses of lupio-rng and lupio-sys
>
> [jporquet] python: update IRQ mapping in LupV board
>
> [jporquet] python: improve FDT generation in LupV board
>
> [jporquet] python: remove "earlycon" linux option from LupV board
>
> [yuhsingw] scons: Update GRPC dependency flag
>
>
> --
> [...truncated 725.12 KB...]
>  [SHCC] X86/ext/softfloat/s_remStepMBy32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundMToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundMToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackMToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackMToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF128.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF16.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToUI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToUI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam128Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam256M.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam32.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam64.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam64Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftLeft128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftLeft64To96M.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRight128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightExtendM.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam128Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam64.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam64Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightM.c -> .os
>  [SHCC] X86/ext/softfloat/s_sub128.c -> .os
>  [SHCC] X86/ext/softfloat/s_sub1XM.c -> .os
>  [SHCC] X86/ext/softfloat/s_sub256M.c -> .os
>  [SHCC] X86/ext/softfloat/s_subMagsF128.c -> .os
>  [SHCC] X86/ext/softfloat/s_subMagsF16.c -> .os
>  [SHCC] X86/ext/softfloat/s_subMagsF32.c -> .os
>  [SHCC] X86/ext/softfloat/s_subMagsF64.c -> .os
>  [SHCC] X86/ext/softfloat/s_subM.c -> .os
>  [SHCC] X86/ext/softfloat/ui32_to_f128.c -> .os
>  [SHCC] X86/ext/softfloat/ui32_to_f16.c -> .os
>  [SHCC] X86/ext/softfloat/ui32_to_f32.c -> .os
>  [SHCC] X86/ext/softfloat/ui32_to_f64.c -> .os
>  [SHCC] X86/ext/softfloat/ui64_to_f128.c -> .os
>  [SHCC] X86/ext/softfloat/ui64_to_f16.c -> .os
>  [SHCC] X86/ext/softfloat/ui64_to_f32.c -> .os
>  [SHCC] X86/ext/softfloat/ui64_to_f64.c -> .os
> build/X86/ext/libelf/native-elf-format >
> build/X86/ext/libelf/native-elf-format.h
>  [  M4] X86/ext/libelf/elf_types.m4, libelf_convert.m4 ->
> libelf_convert.c
>  [SHCC] X86/ext/libelf/libelf_allocate.c -> .os
>  [SHCC] X86/ext/libelf/elf_data.c -> .os
>  [SHCC] X86/ext/libelf/libelf.c -> .os
>  [SHCC] X86/ext/libelf/gelf_phdr.c -> .os
>  [SHCC] X86/ext/libelf/libelf_convert.c -> .os
>  [SHCC] X86/ext/libelf/elf_rand.c -> .os
>  [SHCC] X86/ext/libelf/gelf_getclass.c -> .os
>  [SHCC] X86/ext/libelf/elf_shnum.c -> .os
>  [SHCC] X86/ext/libelf/gelf_shdr.c -> .os
>  [SHCC] X86/ext/libelf/elf_fill.c -> .os
>  [SHCC] X86/ext/libelf/libelf_shdr.c -> .os
>  [SHCC] X86/ext/libelf/elf_kind.c -> .os
>  [SHCC] X86/ext/libelf/elf_cntl.

[gem5-dev] Re: Discussing unifying RVV development efforts

2022-05-25 Thread Jason Lowe-Power
Hi Yang,

On Sun, May 22, 2022 at 11:59 PM ksco  wrote:

> Hi Jason and others,
>
> We (the PLCT Lab) are delighted to receive the rapid feedback from the
> community! And we are glad to see that there are so many contributors in
> the open source community participating in the RVV support on gem5. We want
> to give thanks and respectation to other contributors. We also hope to work
> together with the community to advance the development of RVV support
> faster and better.
>
> I think Zoom meetings are helpful for collaborative development, but our
> English (especially speaking) is not so good, so there may be some
> communication difficulties in the voice meeting. Maybe we can maintain
> long-term communication over some IM? I think Slack is a good option, but
> if you guys have any other preferred chat software, we'd love to use it too.
>

Great idea. We've been talking about using a platform like this. I'll try
to set something up this weekend.


>
> We are honored that Jason believes collaboration should be based on our
> implementation posted on Gerrit. We are currently developing on GitHub (
> github.com/plctlab/plct-gem5), PRs are very welcome!
>
> As for the instruction support, it is true that the implementation of
> RIVOS is more complete than our current implementation. We are very willing
> to cooperate with RIVOS to complete the follow-up instruction
> implementation.
>
> And as for the configuration support of VLEN, We hope to have some
> discussion. We believe that it is necessary to make VLEN configurable. We
> found that RIVOS has added support for it in the compilation phase. But we
> think it might be better to support this configuration at runtime (via
> python) as in Spike/QEMU. But we haven't yet found a way to do it. Is this
> possible in gem5?
>

See
https://github.com/darchr/gem5/commit/8e5ff326d9c6dca4320fb231e335c5f8dbcf1e93.
It's not *quite* right, but the idea is there.


>
> And passing vtype/vl via PCState is indeed a better solution if it can
> implement support for the Timing model without hacking the CPU code. We are
> looking forward to further progress with this solution!
>

Great :). Please let me know if you run into any major hurdles. We're still
working on a proof of concept to ensure the PCState solution works as well.


>
> We're honored that the test repo (
> https://github.com/huxuan0307/riscv-vector-tests) has your praise. More
> peer approval is required before integrating it in gem5-resources, we
> think. At present, this repository is experimental and unsteady. And there
> are still bugs to fix.  We're glad if this repo is helpful for your
> development.
>
> In the next steps, we intend to focus on the development and improvement
> of the unit tests repository (
> https://github.com/huxuan0307/riscv-vector-tests) and continue to explore
> the implementation of some new instruction formats under microinstructions
> (such as Widening and Narrowing instructions). In the future, we could have
> more discussions on division of cooperation. We hope we don't have
> duplicate work in cooperative development.
>

A couple of quick and easy things to do here:
- Create a dockerfile to compile the workloads (Hoa at UC Davis may have
already done this, but I'm not sure).
- Write up enough documentation in the README so that anyone can easily
build these binaries (I think this is very close already).
- Document which binaries work and which don't in gem5

After those small things, I think we should go ahead and integrate these
tests here:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable. We
can iterate on improving the tests and adding more there as well. We (here
at UC Davis) can also help by creating the gem5 scripts necessary to run
the tests.

Cheers,
Jason


>
> Thanks again to all the contributors!
>
> Regards,
>
> Yang Liu
>
> Jason Lowe-Power  于2022年5月21日周六 02:32写道:
>
>> Hi everyone,
>>
>> I'm super excited to see all of the activity around RISC-V vector
>> instructions right now. However, it looks like there are a few different
>> implementations being worked on, and it's a good idea to try to unify
>> around a single implementation and work together to get to a point where
>> everyone in the gem5 community can benefit from this support.
>>
>> Before going any further, I want to give a huge thanks to everyone that
>> has been working on this and has made contributions to varying different
>> implementations. I'm not going to try to name people (I'm certain I missed
>> some in the cc line!), but I hope everyone knows that we appreciate their
>> contributions to the project!
>>
>> Before di

[gem5-dev] Discussing unifying RVV development efforts

2022-05-20 Thread Jason Lowe-Power
Hi everyone,

I'm super excited to see all of the activity around RISC-V vector
instructions right now. However, it looks like there are a few different
implementations being worked on, and it's a good idea to try to unify
around a single implementation and work together to get to a point where
everyone in the gem5 community can benefit from this support.

Before going any further, I want to give a huge thanks to everyone that has
been working on this and has made contributions to varying different
implementations. I'm not going to try to name people (I'm certain I missed
some in the cc line!), but I hope everyone knows that we appreciate their
contributions to the project!

Before diving into details of the code, if there's interest from the
community I can set up a meeting time for us all to get together on zoom to
chat about details and the best way to work together.

Looking at the code (
https://gem5-review.googlesource.com/c/public/gem5/+/59789) and the
documentation (
https://docs.google.com/document/d/1yUDPU9NvpKo1WM1WYfdx20_aXLnlHssUUsDYR4lu95Q/edit)
recently submitted, I think there are many great things about this
approach, and a couple of places that we should discuss potential ways to
improve it.

First, I think that using microcode is definitely the right way to enable
configurable VLEN and to get timing memory accesses to work. Because of
this, I believe that the code posted to gerrit is probably the best
starting point for collaboration. Happy to hear other opinions, though.

Note that the Rivos implementation on github (
https://github.com/rivosinc/gem5/tree/rivos/dev/joy/initial_RVV_support)
does not use microcoded instructions, so it only works in atomic mode.
However, I believe this implementation may have more instructions
implemented than the one on gerrit. Also, in this implementation the VLEN
is a parameter of the ISA which allows users to configure the system
dynamically (which is great!). We should try to find a way to merge these
two implementations.

Second, we should integrate the tests (
https://github.com/huxuan0307/riscv-vector-tests) into gem5-resources ASAP.
This is a fabulous contribution! Having tests for vector insts will enable
much faster development.

I would like to discuss one design decision in the gerrit code:
Specifically how the vtype/vl is set in the decoder. Stalling the decoder
to get the correct vtype/vl when vset*vl* is executed doesn't fit well with
gem5's execution model, and it feels like a bit of a hack.

I have an alternative proposal that I would like to hear your thoughts on.
Instead of storing vtype/vl in the decoder, we could store it in the
PCState. Then, the vset*vl* instruction would look a lot like a control
instruction. At decode time, the next PC state could be set with some
values (maybe wrong values, just like the next pc after a branch may be
wrong) or if it is a vsetivli, then the next PC state would have the
correct values. Then, the subsequent instructions could access the PC state
to get the current vtype/vl.

In the execute stage of the vset*vl*, it would set the next pc state
correctly. The CPU models already check to see if the next PC is the same
in execute as it was "predicted" in the decode stage (i.e., was the branch
predicted correctly). We can leverage this to check to see if vtype/vl are
correct. If not, the CPU models will simply squash and re-execute starting
at the correct next pc (i.e., the next vector instruction will execute the
correct vtype/vl after vset*vl* is executed). If we extend the branch
predictor to predict the vtype/vl and use the "last" values, this should be
correct a huge percentage of the time. Smarter methods could also be
employed.

While this may not be a particularly realistic way to implement a hardware
version of RVV and vset*vl*, I think that it's probably the best way to
model it in gem5 without creating a separate vector engine object which is
decoupled from the CPU model.

We have been working on a proof-of-concept for this here at UC Davis (see
https://github.com/darchr/gem5/tree/hn/rvv-uop, though this is untested in
timing mode right now). Do you all think this is a good way forward? Or, is
there something that I'm missing about the decoder stalling?

Cheers,
Jason
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[gem5-dev] Re: Build failed in Jenkins: compiler-checks #224

2022-05-05 Thread Jason Lowe-Power
Yeah, it was https://gem5-review.googlesource.com/c/public/gem5/+/59151 and
https://gem5-review.googlesource.com/c/public/gem5/+/59149

See the comments on
https://gem5-review.googlesource.com/c/public/gem5/+/59151 for the current
status/discussion.

The question is: should we drop support for clang 6 & 7 or should we remove
the compile-time validation.

Thanks for following up on this!

Cheers,
Jason

On Thu, May 5, 2022 at 9:08 AM Matt Sinclair 
wrote:

> If I'm reading the output correctly, it looks like Giacomo's commit caused
> the problem and the Ruby tester didn't?  Since only ARM tests are failing
> (I think).
>
> Matt
>
> On Thu, May 5, 2022 at 7:27 AM  wrote:
>
>> See <
>> https://jenkins.gem5.org/job/compiler-checks/224/display/redirect?page=changes
>> >
>>
>> Changes:
>>
>> [Giacomo Travaglini] arch-arm: Memoize computeAddrTop in the MMU code
>>
>> [mattdsinclair] tests, gpu-compute, mem-ruby: add GPU Ruby random test to
>> nightly
>>
>>
>> --
>> Started by timer
>> Running as SYSTEM
>> Building in workspace 
>> The recommended git tool is: NONE
>> No credentials specified
>>  > git rev-parse --resolve-git-dir <
>> https://jenkins.gem5.org/job/compiler-checks/ws/.git> # timeout=10
>> Fetching changes from the remote Git repository
>>  > git config remote.origin.url https://gem5.googlesource.com/public/gem5
>> # timeout=10
>> Fetching upstream changes from https://gem5.googlesource.com/public/gem5
>>  > git --version # timeout=10
>>  > git --version # 'git version 2.25.1'
>>  > git fetch --tags --force --progress --
>> https://gem5.googlesource.com/public/gem5
>> +refs/heads/*:refs/remotes/origin/* # timeout=10
>>  > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
>> Checking out Revision 11ccc87c91301e4e86e0f375cd8d9b46b1833491
>> (refs/remotes/origin/develop)
>>  > git config core.sparsecheckout # timeout=10
>>  > git checkout -f 11ccc87c91301e4e86e0f375cd8d9b46b1833491 # timeout=10
>> Commit message: "tests, gpu-compute, mem-ruby: add GPU Ruby random test
>> to nightly"
>>  > git rev-list --no-walk cc6aa4c1739cbbb0ba2c8371f05e5af2a25f93dd #
>> timeout=10
>> [Checks API] No suitable checks publisher found.
>> [compiler-checks] $ /bin/sh -xe /tmp/jenkins3908728248261215737.sh
>> + ./tests/compiler-tests.sh -j 16
>> Starting build tests with 'gcc-version-11'...
>> 'gcc-version-11' was found in the comprehensive tests. All ISAs will be
>> built.
>>   * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'RISCV.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'RISCV.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'POWER.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'POWER.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'MIPS.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'MIPS.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'X86_MI_example.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'X86_MI_example.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'ARM_MESI_Three_Level_HTM.opt' with
>> 'gcc-version-11'...
>> Done.
>>   * Building target 'ARM_MESI_Three_Level_HTM.fast' with
>> 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'X86.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'X86.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'ARM.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'ARM.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'SPARC.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'SPARC.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-11'...
>> Done.
>>   * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-11'...
>> Done.
>>   * Building target 'GCN3_X86.opt' with 'gcc-version-11'...
>> Done.
>>  

[gem5-dev] Re: Request for comments/reviews: Multiple Ruby protocols in a single binary

2022-04-26 Thread Jason Lowe-Power
Hi all,

I (finally) finished rebasing and updating the changes based on the
feedback. Thank you all for your help on this!

On the to do list before merging:
- Some more comments that may need a bit of back and forth (especially from
Andreas as of 5/26)
- Run the nightly and weekly tests on the tip
- Update the website and release notes

Here's the changes again if anyone else wants to provide feedback :)
https://gem5-review.googlesource.com/q/topic:all-ruby-protocols

Cheers,
Jason

On Tue, Apr 12, 2022 at 1:44 PM Jason Lowe-Power 
wrote:

> Hi all,
>
> I would really appreciate some reviews on these changes. This is something
> that I know many in the development community (Andreas, Gabe, others) have
> been asking for. Please take a look!
>
> I think most changes are pretty straightforward. There is one change where
> I would like some specific feedback on a good way to incorporate multiple
> Ruby protocols into the SConscript (
> https://gem5-review.googlesource.com/c/public/gem5/+/58443/2)
>
> Hi Giacomo,
>
> I dug into the idea you proposed a bit more today, and I'm pretty
> convinced that it would be significant work.
>
> It's possible to make a SimObject be part of a submodule of m5.objects.
> However, the problem comes in the params. I don't think there's an easy way
> to create two params/.hh files for SimObjects which have the
> same name.
>
> Basically, we have a strong assumption in the SimObject generation code
> that no two SimObjects will have exactly the same name. Extending this to
> allow SimObjects with the same name would be quite a bit of effort. Right
> now, I don't believe this effort is worth the benefit for this set of
> changes.
>
> Let me know what you think.
>
> Cheers,
> Jason
>
> On Fri, Apr 1, 2022 at 7:48 AM Jason Lowe-Power 
> wrote:
>
>> Sounds like a good idea. But I don't know how to do this easily. All
>> SimObjects are part of the m5.object module, and this is deeply embedded in
>> many different parts of gem5.
>>
>> My best guess at how to do this would be to add a new type of SimObject
>> which is not in m5.objects, but in a submodule. Then, we would also have to
>> extend the Scons concept of "SimObject" and how scons creates the SimObject
>> params files and the python m5.objects files. My initial thought is that
>> this would be a lot more work. I could be wrong, though.
>>
>> If you have a specific idea on how to implement this, or if you can
>> provide an implementation, I can try to integrate it with what I have done.
>>
>> Either way, it will require non-backwards compatible changes to configs
>> to import the correct module or use the new names. I'm not sure the benefit
>> is worth the investment, though.
>>
>> Let me know what you think :)
>>
>> Cheers,
>> Jason
>>
>>
>>
>> On Fri, Apr 1, 2022 at 7:31 AM Giacomo Travaglini <
>> giacomo.travagl...@arm.com> wrote:
>>
>>> Congrats to Jason and to everyone who’s making this possible!
>>>
>>>
>>>
>>> About the naming, I wonder if we could provide a different python module
>>> per ruby protocol.
>>>
>>> That would allow us to avoid prefixing in favour of something like:
>>>
>>>
>>> $from m5.objects.mi_example import L1Cache_Controller
>>>
>>>
>>>
>>> or
>>>
>>>
>>> $from m5.objects.msi import L1Cache_Controller
>>>
>>>
>>>
>>> Kind Regards
>>>
>>>
>>>
>>> Giacomo
>>>
>>>
>>>
>>>
>>>
>>> *From: *Jason Lowe-Power via gem5-dev 
>>> *Date: *Thursday, 31 March 2022 at 18:43
>>> *To: *gem5 Developer List 
>>> *Cc: *Jason Lowe-Power 
>>> *Subject: *[gem5-dev] Request for comments/reviews: Multiple Ruby
>>> protocols in a single binary
>>>
>>> Hi all,
>>>
>>>
>>>
>>> For as long as gem5 has been gem5, you have had to build a different
>>> gem5 binary if you want to use a different Ruby protocol. Making it
>>> possible to build multiple protocols has been on the roadmap for a long
>>> time (at least as long as I've been involved with the project).
>>>
>>>
>>>
>>> I'm excited to say that we've been able to do this (finally), and we
>>> have a set of changesets on gerrit for review/comments feedback.
>>>
>>>
>>>
>>> There are a couple of todo items before it's merged, and a couple of
>&g

[gem5-dev] [S] Change in gem5/gem5[develop]: python: Add error for creating abstact SimObjects

2022-04-22 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/59049 )



Change subject: python: Add error for creating abstact SimObjects
..

python: Add error for creating abstact SimObjects

Currently, if you try to instantiate an abstract SimObject the error is
confusing and unhelpful.

"TypeError: _m5.param_.Params: No constructor defined!"

Now, it will instead say "Cannot instantiate an abstract SimObject"
and include the name of the object that causes the error.

Change-Id: Ia8c51e29dccd999ec90dcd39710cc91d9a5fb86f
Signed-off-by: Jason Lowe-Power 
---
M src/python/m5/SimObject.py
1 file changed, 20 insertions(+), 0 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 26a1227..26147a1 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1175,6 +1175,8 @@

 # Call C++ to create C++ object corresponding to this object
 def createCCObject(self):
+if self.abstract:
+fatal(f"Cannot instantiate an abstract SimObject  
({self.path()})")

 self.getCCParams()
 self.getCCObject() # force creation


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/59049
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia8c51e29dccd999ec90dcd39710cc91d9a5fb86f
Gerrit-Change-Number: 59049
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Adding an extension object to Packet-s

2022-04-18 Thread Jason Lowe-Power via gem5-dev
Hi Yan,

Can you use the Packet::pushSenderState(), popSenderState(), etc functions?
This is a stack instead of a linked-list, but it may work for your use
case. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/packet.hh#440
for more information.

The idea with that interface is that an object can push "sender state" into
the packet, send the packet on to some other receiver, and then when you
get a response you can pop the sender state back off. You can also
use findNextSenderState to get any sender state from the stack.

To use it, you can extend the class SenderState to hold any state that
you'd like.

Let me know if this isn't what you're looking for. It sounds quite similar
to what you're proposing. If we can extend that interface, it would
probably be better than adding something totally new.

Cheers,
Jason

On Thu, Apr 14, 2022 at 1:08 AM Yan Lee via gem5-dev 
wrote:

> Hi Gabe and everyone,
>
> Thanks Gabe for bringing this up. Currently I am making a model in AXI
> protocol and this model will need the AxUser and AxProt fields in the AXI
> protocol. The packet in gem5 cannot carry additional information except the
> actual read/write data. I think we can have the extension mechanism in our
> gem5 packet just like the way in SystemC. Therefore, we can simulate some
> protocol-related behavior with this extension in each gem5 packet.
>
> I think we can have an array-based or linked-list-based extension
> mechanism in gem5 packet. That is, we can have multiple extensions in one
> packet and may be increased during the transaction. But we can discuss the
> way of searching for one extension. In systemc, it uses linear search to
> find if one extension exists or not.
>
> Look forward to any feedback or ideas, and thanks for your sharing.
>
> Yan
>
> On Thu, Apr 14, 2022 at 3:37 PM Gabe Black  wrote:
>
>> Hi folks. Yan Lee, a Google colleague of mine, is interested in adding
>> one or more extension objects to gem5 Packet. Systemc has a mechanism like
>> this already, and it's come up a few times where we've wanted to have
>> something like this on the gem5 side as well.
>>
>> Yan, can you please talk about the problem you're trying to solve, and
>> the mechanism you want to add to handle it?
>>
>> Gabe
>>
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[gem5-dev] Re: Build failed in Jenkins: weekly #44

2022-04-18 Thread Jason Lowe-Power via gem5-dev
Hi all,

Here's a link to the failing test:
https://jenkins.gem5.org/job/weekly/44/artifact/tests/testing-results/SuiteUID%3Atiming-cpu_2-cores_mesi_two_level_DualChannelDDR4_2400_systemd_x86-boot-test-X86-x86_64-opt/TestUID%3Atiming-cpu_2-cores_mesi_two_level_DualChannelDDR4_2400_systemd_x86-boot-test-X86-x86_64-opt/

I *think* the problem is in how we're exiting the simulation after boot. It
looks like the system boots up correctly. However, the simulation is not
exiting cleanly as there are no stats output.

We've had some issues with flakiness in booting through systemd in
the past. I always assumed it's because systemd tries to enable networking,
etc. and something was going wrong in one of those subsystems, but maybe
it's something else. If anyone has ideas on how to track this down, I'd
love to hear them. Frustratingly, it seems to work when we run the test
locally.

Cheers,
Jason

On Sun, Apr 17, 2022 at 12:06 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <https://jenkins.gem5.org/job/weekly/44/display/redirect?page=changes>
>
> Changes:
>
> [hoanguyen] stdlib, configs: Migrate riscv-ubuntu-run example to Simulator
>
> [Jason Lowe-Power] scons: Fix bug in error message
>
> [gabe.black] arch-x86: Override make(Read|Write) instead of
> (read|write)_code.
>
> [gabe.black] arch: Eliminate the now unused read_code and write_code args.
>
> [yuhsingw] scons: Fix script failed when default files not found
>
> [gabe.black] scons: Ensure the fast model license count is always at least
> 1.
>
> [yuhsingw] fastmodel: Export more CortexA76 reset pin
>
> [yuhsingw] fastmodel: Export more CortexR52 reset pin
>
> [joy] arch-riscv: Added the Zba and Zbb bitmanip instructions
>
> [joy] arch-riscv: Added the Zbc bitmanip instructions
>
> [joy] arch-riscv: Added the Zbs bitmanip instructions
>
> [hoanguyen] stdlib, configs: Fix riscv-ubuntu-run error
>
>
> --
> [...truncated 536.09 KB...]
>  [SHCC] X86/ext/softfloat/s_normSubnormalF16Sig.c -> .os
>  [SHCC] X86/ext/softfloat/s_normSubnormalF32Sig.c -> .os
>  [SHCC] X86/ext/softfloat/s_normSubnormalF64Sig.c -> .os
>  [SHCC] X86/ext/softfloat/softfloat_raiseFlags.c -> .os
>  [SHCC] X86/ext/softfloat/softfloat_state.c -> .os
>  [SHCC] X86/ext/softfloat/s_propagateNaNF128UI.c -> .os
>  [SHCC] X86/ext/softfloat/s_propagateNaNF16UI.c -> .os
>  [SHCC] X86/ext/softfloat/s_propagateNaNF32UI.c -> .os
>  [SHCC] X86/ext/softfloat/s_propagateNaNF64UI.c -> .os
>  [SHCC] X86/ext/softfloat/s_remStepMBy32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundMToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundMToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackMToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackMToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF128.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF16.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToF64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToUI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundPackToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToUI32.c -> .os
>  [SHCC] X86/ext/softfloat/s_roundToUI64.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam128Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam256M.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam32.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam64.c -> .os
>  [SHCC] X86/ext/softfloat/s_shiftRightJam64Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftLeft128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftLeft64To96M.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRight128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightExtendM.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam128Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam64.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightJam64Extra.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightM.c -> .os
>  [SHCC] X86/ext/softfloat/s_sub128.c -> .os
>  [SHCC] X86/ext/softfloat/s_sub1XM.c -> .os
>  [SHCC] X86/ext/softfloat/s_sub256M.

[gem5-dev] Re: Build failed in Jenkins: nightly #194

2022-04-15 Thread Jason Lowe-Power via gem5-dev
It looks successful to me. Supposedly
test-gem5-library-example-x86-gapbs-benchmarks-X86-aarch64-opt-MESI_Two_Level
failed, but everything looks fine:
https://jenkins.gem5.org/job/nightly/194/artifact/tests/testing-results/SuiteUID%3Atest-gem5-library-example-x86-gapbs-benchmarks-X86-aarch64-opt-MESI_Two_Level/TestUID%3Atest-gem5-library-example-x86-gapbs-benchmarks-X86-aarch64-opt-MESI_Two_Level/

Let's hope that it's just a bump and things are back to normal tonight.

Cheers,
Jason

On Fri, Apr 15, 2022 at 3:53 PM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/194/display/redirect?page=changes>
>
> Changes:
>
> [hoanguyen] stdlib, configs: Fix riscv-ubuntu-run error
>
>
> --
> [...truncated 1.66 MB...]
> Checking for C header file fenv.h... (cached) yes
> Checking for C header file png.h... (cached) yes
> Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached)
> yes
> Checking for C header file valgrind/valgrind.h... (cached) no
> Warning: Deprecated namespaces are not supported by this compiler.
>  Please make sure to check the mailing list for deprecation
>  announcements.
> Checking for pkg-config package hdf5-serial... (cached) yes
> Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) yes
> Checking for H5::H5File("", 0) in C++ library hdf5_cpp... (cached) yes
> Checking for C header file linux/kvm.h... (cached) yes
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
> None... (cached) no
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt...
> (cached) yes
> Checking size of struct kvm_xsave ... (cached) yes
> Checking for member exclude_host in struct perf_event_attr...(cached) yes
> Checking for shm_open("/test", 0, 0) in C library None... (cached) yes
> Checking for char temp; backtrace_symbols_fd((void *)&temp, 0, 0) in C
> library None... (cached) yes
> Checking for pkg-config package protobuf... (cached) yes
> Checking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf...
> (cached) yes
> Checking for C header file linux/if_tun.h... (cached) yes
> Checking whether __i386__ is declared... (cached) no
> Checking whether __x86_64__ is declared... (cached) yes
> Checking for compiler -Wno-self-assign-overloaded support... (cached) yes
> Checking for compiler -Wno-free-nonheap-object support... (cached) yes
> scons: done reading SConscript files.
> scons: Building targets ...
>  [VER TAGS]  -> GCN3_X86/sim/tags.cc
> scons: `build/GCN3_X86/gem5.opt' is up to date.
> scons: done building targets.
> *** Summary of Warnings ***
> Warning: Deprecated namespaces are not supported by this compiler.
>  Please make sure to check the mailing list for deprecation
>  announcements.
> Building the following targets. This may take a while.
> /nobackup/jenkins/workspace/nightly/build/X86_MI_example/gem5.opt
> You may want to run with only a single ISA(--isa=), use --skip-build, or
> use 'rerun'.
> Logging call to command: scons -C /nobackup/jenkins/workspace/nightly -j
> 16 --ignore-style --no-compress-debug
> /nobackup/jenkins/workspace/nightly/build/X86_MI_example/gem5.opt
> --default=X86 PROTOCOL=MI_example
> scons: Entering directory `/nobackup/jenkins/workspace/nightly'
> scons: Reading SConscript files ...
>
> Mkdir("/nobackup/jenkins/workspace/nightly/build/X86_MI_example/gem5.build")
> Checking for linker -Wl,--as-needed support... (cached) yes
> Checking for compiler -Wno-free-nonheap-object support... (cached) yes
> Info: Using Python config: python3-config
> Checking for C header file Python.h... (cached) yes
> Checking Python version... (cached) 3.8.10
> Checking for accept(0,0,0) in C++ library None... (cached) yes
> Checking for zlibVersion() in C++ library z... (cached) yes
> Checking for C library tcmalloc... (cached) yes
> Building in /nobackup/jenkins/workspace/nightly/build/X86_MI_example
> Using saved variables file(s)
> /nobackup/jenkins/workspace/nightly/build/X86_MI_example/gem5.build/variables
> Checking for C header file fenv.h... (cached) yes
> Checking for C header file png.h... (cached) yes
> Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached)
> yes
> Checking for C header file valgrind/valgrind.h... (cached) no
> Warning: Deprecated namespaces are not supported by this compiler.
>  Please make sure to check the mailing list for deprecation
>  announcements.
> Checking for pkg-config package hdf5-serial... (cached) yes
> Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) yes
> Checking for H5::H5File("", 0) in C++ library hdf5_cpp... (cached) yes
> Checking for C header file linux/kvm.h... (cached) yes
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
> None... (cached) no
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt...
> (cached) yes
> Checking size of struct kvm_xsave ... (ca

[gem5-dev] Re: gem5 v22.0 to be released in early May. Staging branch to be created by the end of April

2022-04-15 Thread Jason Lowe-Power via gem5-dev
Hi all,

I would like to merge in my multi-Ruby protocol changes:
https://gem5-review.googlesource.com/c/public/gem5/+/58469
Outstanding issues:
  - I'm still working on the one WIP change to update scons. This should be
ready to review in a couple of days. The other changesets are ready to
review now.

Cheers,
Jason

On Fri, Apr 15, 2022 at 9:13 AM Jason Lowe-Power 
wrote:

> Hi all,
>
> Please respond to this message with a pointer to the gerrit review links
> for changesets that you would like to prioritize for 22.0. This way the
> community can work together to make this another great release with lots of
> new features!
>
> There's a list of issues open in jira here
> <https://gem5.atlassian.net/issues/?jql=project%20%3D%20GEM5%20AND%20status%20in%20(%22In%20Progress%22%2C%20%22In%20Review%22%2C%20%22To%20do%22)%20AND%20fixVersion%20%3D%20%22gem5%2022.0%22>.
> There's currently 65 issues that are "to do", "in progress", or "in
> review". We almost certainly will not be able to get to all of these in the
> next 2 weeks, but if there's something that's important to you, please let
> the community know, and we can try to work together to prioritize that.
>
> Cheers,
> Jason
>
> On Thu, Apr 14, 2022 at 11:39 AM Bobby Bruce via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> Dear all,
>>
>> We intend to create the staging branch on April 28th, with the intent of
>> releasing gem5 v22.0 in early May. This is a two week warning. Please
>> ensure all your patches you wish to be part of v22.0 are submitted to the
>> develop branch prior to April 28th.
>>
>> Kind regards,
>> Bobby
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Mon, Apr 4, 2022 at 10:28 AM Bobby Bruce  wrote:
>>
>>> Dear all,
>>>
>>> In line with our policy of having three major releases a year, we're
>>> aiming to have v22.0 of gem5 released in early May.  This means we'll be
>>> creating a staging branch from the develop branch by the end of April. The
>>> staging branch will be intensely tested to ensure it is suitable for
>>> general community use before being merged into the stable branch.
>>>
>>> We understand there's a backlog of patches to be reviewed. We'll try to
>>> ensure everyone who puts in the effort to submit for this release, and
>>> responds promptly to feedback, makes it into the v22.0 release. If you feel
>>> your patches have been ignored, please ping us on the relevant Gerrit
>>> submission (if you have not already added reviewers, remember to add them).
>>> Help with reviewing over the next month would also be greatly appreciated.
>>>
>>> Kind regards,
>>> Bobby
>>> --
>>> Dr. Bobby R. Bruce
>>> Room 3050,
>>> Kemper Hall, UC Davis
>>> Davis,
>>> CA, 95616
>>>
>>> web: https://www.bobbybruce.net
>>>
>> ___
>> gem5-dev mailing list -- gem5-dev@gem5.org
>> To unsubscribe send an email to gem5-dev-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
>
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[gem5-dev] Re: gem5 v22.0 to be released in early May. Staging branch to be created by the end of April

2022-04-15 Thread Jason Lowe-Power via gem5-dev
Hi all,

Please respond to this message with a pointer to the gerrit review links
for changesets that you would like to prioritize for 22.0. This way the
community can work together to make this another great release with lots of
new features!

There's a list of issues open in jira here
.
There's currently 65 issues that are "to do", "in progress", or "in
review". We almost certainly will not be able to get to all of these in the
next 2 weeks, but if there's something that's important to you, please let
the community know, and we can try to work together to prioritize that.

Cheers,
Jason

On Thu, Apr 14, 2022 at 11:39 AM Bobby Bruce via gem5-dev 
wrote:

> Dear all,
>
> We intend to create the staging branch on April 28th, with the intent of
> releasing gem5 v22.0 in early May. This is a two week warning. Please
> ensure all your patches you wish to be part of v22.0 are submitted to the
> develop branch prior to April 28th.
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Mon, Apr 4, 2022 at 10:28 AM Bobby Bruce  wrote:
>
>> Dear all,
>>
>> In line with our policy of having three major releases a year, we're
>> aiming to have v22.0 of gem5 released in early May.  This means we'll be
>> creating a staging branch from the develop branch by the end of April. The
>> staging branch will be intensely tested to ensure it is suitable for
>> general community use before being merged into the stable branch.
>>
>> We understand there's a backlog of patches to be reviewed. We'll try to
>> ensure everyone who puts in the effort to submit for this release, and
>> responds promptly to feedback, makes it into the v22.0 release. If you feel
>> your patches have been ignored, please ping us on the relevant Gerrit
>> submission (if you have not already added reviewers, remember to add them).
>> Help with reviewing over the next month would also be greatly appreciated.
>>
>> Kind regards,
>> Bobby
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
> ___
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> To unsubscribe send an email to gem5-dev-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-dev] Re: Request for comments/reviews: Multiple Ruby protocols in a single binary

2022-04-12 Thread Jason Lowe-Power via gem5-dev
Hi all,

I would really appreciate some reviews on these changes. This is something
that I know many in the development community (Andreas, Gabe, others) have
been asking for. Please take a look!

I think most changes are pretty straightforward. There is one change where
I would like some specific feedback on a good way to incorporate multiple
Ruby protocols into the SConscript (
https://gem5-review.googlesource.com/c/public/gem5/+/58443/2)

Hi Giacomo,

I dug into the idea you proposed a bit more today, and I'm pretty convinced
that it would be significant work.

It's possible to make a SimObject be part of a submodule of m5.objects.
However, the problem comes in the params. I don't think there's an easy way
to create two params/.hh files for SimObjects which have the
same name.

Basically, we have a strong assumption in the SimObject generation code
that no two SimObjects will have exactly the same name. Extending this to
allow SimObjects with the same name would be quite a bit of effort. Right
now, I don't believe this effort is worth the benefit for this set of
changes.

Let me know what you think.

Cheers,
Jason

On Fri, Apr 1, 2022 at 7:48 AM Jason Lowe-Power  wrote:

> Sounds like a good idea. But I don't know how to do this easily. All
> SimObjects are part of the m5.object module, and this is deeply embedded in
> many different parts of gem5.
>
> My best guess at how to do this would be to add a new type of SimObject
> which is not in m5.objects, but in a submodule. Then, we would also have to
> extend the Scons concept of "SimObject" and how scons creates the SimObject
> params files and the python m5.objects files. My initial thought is that
> this would be a lot more work. I could be wrong, though.
>
> If you have a specific idea on how to implement this, or if you can
> provide an implementation, I can try to integrate it with what I have done.
>
> Either way, it will require non-backwards compatible changes to configs to
> import the correct module or use the new names. I'm not sure the benefit is
> worth the investment, though.
>
> Let me know what you think :)
>
> Cheers,
> Jason
>
>
>
> On Fri, Apr 1, 2022 at 7:31 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
>> Congrats to Jason and to everyone who’s making this possible!
>>
>>
>>
>> About the naming, I wonder if we could provide a different python module
>> per ruby protocol.
>>
>> That would allow us to avoid prefixing in favour of something like:
>>
>>
>> $from m5.objects.mi_example import L1Cache_Controller
>>
>>
>>
>> or
>>
>>
>> $from m5.objects.msi import L1Cache_Controller
>>
>>
>>
>> Kind Regards
>>
>>
>>
>> Giacomo
>>
>>
>>
>>
>>
>> *From: *Jason Lowe-Power via gem5-dev 
>> *Date: *Thursday, 31 March 2022 at 18:43
>> *To: *gem5 Developer List 
>> *Cc: *Jason Lowe-Power 
>> *Subject: *[gem5-dev] Request for comments/reviews: Multiple Ruby
>> protocols in a single binary
>>
>> Hi all,
>>
>>
>>
>> For as long as gem5 has been gem5, you have had to build a different gem5
>> binary if you want to use a different Ruby protocol. Making it possible to
>> build multiple protocols has been on the roadmap for a long time (at least
>> as long as I've been involved with the project).
>>
>>
>>
>> I'm excited to say that we've been able to do this (finally), and we have
>> a set of changesets on gerrit for review/comments feedback.
>>
>>
>>
>> There are a couple of todo items before it's merged, and a couple of
>> user-facing changes that we could not find a way to make fully backwards
>> compatible. More on this below.
>>
>>
>>
>> Let me know what you think, and let me know if there are any questions!
>> I'm excited to see this get in for gem5-22.0.
>>
>>
>>
>> Changes: https://gem5-review.googlesource.com/q/topic:all-ruby-protocols
>>
>>
>>
>> *Non-backwards compatible changes:*
>>
>> Previously each SLICC protocol used the same names for the same machine
>> time. E.g., MI_example has an `L1Cache_Controller` and MSI has an
>> `L1Cache_Controller`. These names were automatically generated from the
>> MachineType (L1Cache) + "_Controller". Now, since we want to be able to
>> compile these two protocols at the same time, we need to make sure there
>> are no (python) name clashes. So, these have been renamed to have the
>> protocol name prepended onto the machine name (e.g.,
>> `MI_exam

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix bug in error message

2022-04-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58429 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: scons: Fix bug in error message
..

scons: Fix bug in error message

The variable p doesn't exist in the context. Just remove the extra
print. Even without the specific variable printed the error message is
pretty helpful.

Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58429
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M build_tools/sim_object_param_struct_hh.py
1 file changed, 19 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/build_tools/sim_object_param_struct_hh.py  
b/build_tools/sim_object_param_struct_hh.py

index ff525ee..261ac9b 100644
--- a/build_tools/sim_object_param_struct_hh.py
+++ b/build_tools/sim_object_param_struct_hh.py
@@ -73,7 +73,7 @@
 try:
 ptypes = [p.ptype for p in params]
 except:
-print(sim_object, p, p.ptype_str)
+print(sim_object)
 print(params)
 raise


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58429
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793
Gerrit-Change-Number: 58429
Gerrit-PatchSet: 4
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Problem decoding RISC-V vector instructions

2022-04-07 Thread Jason Lowe-Power via gem5-dev
Hi all,

In working to integrate the RISC-V vector instructions (RVV) implementation
from Rivos, I've come across a unique (to me) problem. In RVV, the vector
length and the size of the vector element is specified *at runtime* by the
`setvl` instruction. So, the way you decode a vector instruction changes
depending on the previous instructions that have executed.

The problem is that when constructing a static instruction, you need to
know the number of source and destination registers. You also need to be
able to set the src/dest register ids (though, I have to be honest that I
don't fully understand what `set[Src/Dest]RegIdx` is actually doing).

However, for RISC-V vector instructions, the number of src/dest registers
and register IDs depends on the current state (execution context). The
vector length, masking, and vector element size is dependent on
`MISCREG_VL` and `MISCREG_VTYPE`. Right now, these are MISCREGs, but it may
be more appropriate to use a different register class (e.g., something more
like CC regs?).

I can't find another example of this kind of dependency in the codebase. If
someone could point me to an example of how to use execution context state
to decode, I would appreciate it.

I have a feeling this is a new requirement. So, assuming there's no good
examples today, I'd appreciate some pointers for the "right" way to
implement this.

Right now, I'm not very concerned with being able to rename these
registers. Getting RVV working for the O3CPU isn't a requirement currently.
If we can come up with a solution that works in the simple case first, then
try to generalize to O3, that would be good with me.

I suppose one option would be to use the thread context (not execution
context) in the decoder to "speculate" what the vector length is, then, in
execute, read the correct value and make sure we're correct. This may work
for the Simple CPU. It probably won't work for the other CPU models.

Here's a link to the current (working) implementation that "hacks" around
the issue by passing the MISCREGs into the decoder.
https://github.com/rivosinc/gem5/commit/d6d068c9fabf34e5327107513ec41dea3e5e9acc

We could instead use the thread context pointer in the ISA object, but I
don't believe that will solve the problem generally.

Thanks for the input!

Cheers,
Jason
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[gem5-dev] Re: Build failed in Jenkins: compiler-checks #189

2022-04-05 Thread Jason Lowe-Power via gem5-dev
That sounds like a great middle ground.

We could *probably* drop support for 18.04 in v22.0, but we should have a
broader discussion and make sure that's our intention. It's probably not
great to drop support for an OS to get the nightly tests to pass :).

Cheers,
Jason

On Tue, Apr 5, 2022 at 3:43 PM Gabe Black  wrote:

> Well, in that case, we could detect version 3.0.1 (there is a function to
> get the version I believe) and do the monkey patch they suggest in the
> email. The fix was just adding that little function they show, which did
> not exist at all in version 3.0.1. I would have to look up exactly how you
> monkey patch things in python, but I think that's all that should be
> necessary. When we drop support for 3.0.1, then we can drop our hack fix
> also.
>
> Gabe
>
> On Tue, Apr 5, 2022 at 3:12 PM Bobby Bruce  wrote:
>
>> I think we need to have a little discussion on this. The problem with
>> increasing the scons version is we support Ubuntu 18.04 (Official
>> end-of-support not until April 2023) which if you run `apt install scons`
>> will give you v3.0.1. So, increasing this the scons version requirements
>> will hurt these users.
>>
>> I think our solutions here are either:
>>
>> 1) Drop support for Ubuntu 18.04 in the next release.
>> 2) Have a work-around available for Ubuntu 18.04 users.
>> 3) Maintain v3.01 as the minimum scons dependency and work around that.
>>
>> Unfortunately, none of these are very appealing.
>>
>> In the interests of not having the compiler tests fail for another night,
>> can we revert this commit until we figure out exactly what we want to do?
>>
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Tue, Apr 5, 2022 at 1:34 PM Gabe Black  wrote:
>>
>>> The bug in SCons was fixed in version 3.0.2. I have a CL which updates
>>> the required version here:
>>>
>>> https://gem5-review.googlesource.com/c/public/gem5/+/58629
>>>
>>> I'm assuming some docker configuration something will need to be updated
>>> to use SCons version 3.0.2 instead of the 3.0.1 it seems to be using.
>>>
>>> Gabe
>>>
>>> On Tue, Apr 5, 2022 at 4:13 PM Gabe Black  wrote:
>>>
>>>> I think this is actually a bug in SCons. This docker image seems to be
>>>> using the minimum version of it we support, which I think is where the
>>>> problem is coming from and not the compiler versions. There is a
>>>> "fix"/workaround in this email thread which I haven't tried yet, and which
>>>> is a bit of a hack.
>>>>
>>>> https://pairlist2.pair.net/pipermail/scons-dev/2018-October/004766.html
>>>>
>>>> I'm not sure when this bug would have been fixed, or what the best way
>>>> to check if we need to monkey patch around it. If we can find the version
>>>> of SCons where it was fixed and it's not that much more recent, bumping up
>>>> past it may be the easiest.
>>>>
>>>> I think the reason this becomes visible with the change above is that
>>>> more SCons code is run unconditionally, and so the fast model code is now
>>>> being run in the test environment where it is disabled and just skipped
>>>> wholesale before.
>>>>
>>>> Gabe
>>>>
>>>> On Tue, Apr 5, 2022 at 3:06 AM Gabe Black  wrote:
>>>>
>>>>> Yes, I'll take a look.
>>>>>
>>>>> Gabe
>>>>>
>>>>> On Mon, Apr 4, 2022 at 3:02 PM Bobby Bruce  wrote:
>>>>>
>>>>>> I don't fully understand the issue, but after doing a bisect, the
>>>>>> commit causing these issues is
>>>>>> https://gem5-review.googlesource.com/c/public/gem5/+/58356.
>>>>>>
>>>>>> To reproduce locally:
>>>>>>
>>>>>> ```
>>>>>> docker run -u $UID:$GID --rm -v $(pwd):$(pwd) -w $(pwd)
>>>>>> gcr.io/gem5-test/clang-version-9 python3 /usr/bin/scons
>>>>>> build/NULL/gem5.opt -j`nproc`
>>>>>> ```
>>>>>>
>>>>>> which will return:
>>>>>>
>>>>>> ```
>>>>>> scons: *** [build/RISCV/gem5.opt] TypeError `unhashable type:
>>>>>> 'Literal'' trying to evaluate `${_concat(RPATHPREFIX, RPATH, RP

[gem5-dev] Re: Build failed in Jenkins: compiler-checks #189

2022-04-01 Thread Jason Lowe-Power via gem5-dev
Interesting errors. See
https://jenkins.gem5.org/job/compiler-checks/189/artifact/compile-test-out/clang-version-9/
for more info. I think this is a scons error, as it looks like python.

scons: *** [build/RISCV/gem5.opt] TypeError `unhashable type:
'Literal'' trying to evaluate `${_concat(RPATHPREFIX, RPATH,
RPATHSUFFIX, __env__)}'




On Fri, Apr 1, 2022 at 5:21 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/compiler-checks/189/display/redirect?page=changes
> >
>
> Changes:
>
> [gabe.black] scons: Remove an error check from the ProtoBuf declare-er.
>
> [yenlinlai] scons: Allow sources and libs called multiple times
>
> [gabe.black] scons: Add a priority field to the SourceLib construct.
>
> [gabe.black] scons: Get rid of an unused fast model variable.
>
> [gabe.black] scons: Tone down a fast model error into a warning.
>
> [gabe.black] scons: Stop the fast model project file parser from writing
> files.
>
> [gabe.black] scons: Rework the fastmodel extract_var helper.
>
> [gabe.black] scons: Only warn about not finding fast model libs if it's
> enabled.
>
> [gabe.black] scons: Add a tag for arm fastmodel and use it.
>
>
> --
> Started by timer
> Running as SYSTEM
> Building in workspace 
> The recommended git tool is: NONE
> No credentials specified
>  > git rev-parse --resolve-git-dir <
> https://jenkins.gem5.org/job/compiler-checks/ws/.git> # timeout=10
> Fetching changes from the remote Git repository
>  > git config remote.origin.url https://gem5.googlesource.com/public/gem5
> # timeout=10
> Fetching upstream changes from https://gem5.googlesource.com/public/gem5
>  > git --version # timeout=10
>  > git --version # 'git version 2.25.1'
>  > git fetch --tags --force --progress --
> https://gem5.googlesource.com/public/gem5
> +refs/heads/*:refs/remotes/origin/* # timeout=10
>  > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
> Checking out Revision 3b6ea3dfa9055fcd7fb83738b11d00ac00f813ce
> (refs/remotes/origin/develop)
>  > git config core.sparsecheckout # timeout=10
>  > git checkout -f 3b6ea3dfa9055fcd7fb83738b11d00ac00f813ce # timeout=10
> Commit message: "scons: Add a tag for arm fastmodel and use it."
>  > git rev-list --no-walk 118b069d5d238c68afbe29d11878137746b3c375 #
> timeout=10
> [Checks API] No suitable checks publisher found.
> [compiler-checks] $ /bin/sh -xe /tmp/jenkins10877671131247552434.sh
> + ./tests/compiler-tests.sh -j 16
> Starting build tests with 'gcc-version-11'...
> 'gcc-version-11' was found in the comprehensive tests. All ISAs will be
> built.
>   * Building target 'X86_MI_example.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'X86_MI_example.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'POWER.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'POWER.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'RISCV.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'RISCV.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'Garnet_standalone.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'Garnet_standalone.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_directory.fast' with
> 'gcc-version-11'...
> Done.
>   * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'SPARC.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'SPARC.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'X86.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'X86.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'MIPS.opt' with 'gcc-version-11'...
> Done.
>   * B

[gem5-dev] Re: Request for comments/reviews: Multiple Ruby protocols in a single binary

2022-04-01 Thread Jason Lowe-Power via gem5-dev
Sounds like a good idea. But I don't know how to do this easily. All
SimObjects are part of the m5.object module, and this is deeply embedded in
many different parts of gem5.

My best guess at how to do this would be to add a new type of SimObject
which is not in m5.objects, but in a submodule. Then, we would also have to
extend the Scons concept of "SimObject" and how scons creates the SimObject
params files and the python m5.objects files. My initial thought is that
this would be a lot more work. I could be wrong, though.

If you have a specific idea on how to implement this, or if you can provide
an implementation, I can try to integrate it with what I have done.

Either way, it will require non-backwards compatible changes to configs to
import the correct module or use the new names. I'm not sure the benefit is
worth the investment, though.

Let me know what you think :)

Cheers,
Jason



On Fri, Apr 1, 2022 at 7:31 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Congrats to Jason and to everyone who’s making this possible!
>
>
>
> About the naming, I wonder if we could provide a different python module
> per ruby protocol.
>
> That would allow us to avoid prefixing in favour of something like:
>
>
> $from m5.objects.mi_example import L1Cache_Controller
>
>
>
> or
>
>
> $from m5.objects.msi import L1Cache_Controller
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
>
>
> *From: *Jason Lowe-Power via gem5-dev 
> *Date: *Thursday, 31 March 2022 at 18:43
> *To: *gem5 Developer List 
> *Cc: *Jason Lowe-Power 
> *Subject: *[gem5-dev] Request for comments/reviews: Multiple Ruby
> protocols in a single binary
>
> Hi all,
>
>
>
> For as long as gem5 has been gem5, you have had to build a different gem5
> binary if you want to use a different Ruby protocol. Making it possible to
> build multiple protocols has been on the roadmap for a long time (at least
> as long as I've been involved with the project).
>
>
>
> I'm excited to say that we've been able to do this (finally), and we have
> a set of changesets on gerrit for review/comments feedback.
>
>
>
> There are a couple of todo items before it's merged, and a couple of
> user-facing changes that we could not find a way to make fully backwards
> compatible. More on this below.
>
>
>
> Let me know what you think, and let me know if there are any questions!
> I'm excited to see this get in for gem5-22.0.
>
>
>
> Changes: https://gem5-review.googlesource.com/q/topic:all-ruby-protocols
>
>
>
> *Non-backwards compatible changes:*
>
> Previously each SLICC protocol used the same names for the same machine
> time. E.g., MI_example has an `L1Cache_Controller` and MSI has an
> `L1Cache_Controller`. These names were automatically generated from the
> MachineType (L1Cache) + "_Controller". Now, since we want to be able to
> compile these two protocols at the same time, we need to make sure there
> are no (python) name clashes. So, these have been renamed to have the
> protocol name prepended onto the machine name (e.g.,
> `MI_example_L1Cache_Controller`).
>
>
>
> For most people using Ruby, we can provide backwards compatibility. If you
> simply instantiate the `L1Cache_Controller` in python, we can provide a new
> factory function that does the "right" thing. However, if you inherit from
> `L1Cache_Controller` to specialize the controller, this won't work.
>
>
>
> *The user-facing change is* if you have any local ruby protocol
> configuration files which use inheritance with the controllers, you will
> have to update the controller classes to use the name of the protocol
> prepended on the controller name.
>
>
>
> We have updated all of the configurations that are in the gem5 repo. You
> will see warnings if you use the old backwards-compatible names (including
> with Ruby.py).
>
>
>
> The only other user-facing change (I think, reviewers, please point out if
> I'm wrong), is that in places that `buildEnv["PROTOCOL"]` was used to check
> the protocol that was built, you will now need to use `getRubyProtocol`
> (also available in `m5.defines`). However, we are currently supporting
> backwards compatibility here, but there will be no warning when we drop
> backwards compatibility (I expect this to be in a couple of releases).
>
>
>
> *To do items*
>
> - Correctly integrate this with scons (and the new kconfig). See
> https://gem5-review.googlesource.com/c/public/gem5/+/58443 for a WIP that
> needs to be updated.
>
> - Update the website. Assuming there are no major flaws in our
> implementation, we will update the 

[gem5-dev] Re: Request for comments/reviews: Multiple Ruby protocols in a single binary

2022-03-31 Thread Jason Lowe-Power via gem5-dev
Thanks, Brad!

I *hope* that the downstream work is minimal. There's only one change that
I couldn't figure out a way to make backwards compatible, and it's a very
minor update. BTW, if you have an idea on how to make it backwards
compatible, I'm open to revising. I tried a few different things, but I
couldn't find a solution.

The motivation was twofold:
1. There are two sets of changes pushed by Gabe Black that move us closer
to having a single gem5 binary: the MultiISA changes and the kconfig
changes. When these are merged, Ruby was the only thing holding us back
from having a single gem5 binary. I think that having a single gem5 binary
will be a huge win for our users. In fact, for many users they will only
have to build gem5 once, or maybe not at all, if we distribute a prebuilt
version!
2. Testing will be much easier/faster. I don't have data on this, yet, as
the final contribution to select the protocol at runtime is missing. I'm
waiting for reviews on the scons changes before I tackle the last part.
That said, well over 50% (probably closer to 75% or more) of our testing is
building gem5. If we can reduce the number of different targets, we're
going to see a huge win, even if each build is 10% slower.

I'll say that if we were to merge the changes as-is (which we shouldn't!
there's still at least one large WIP), the compile time would increase. In
fact, it would increase in the worst possible way. SLICC is pretty slow
right now, and it runs once for every protocol during the scons startup.
So, building after a change even to a single file is going to be worse with
this change. Thus, I am advocating for waiting on this change (at least the
part that enables multiple protocols) until after the kconfig changes have
been merged.

Let me know if you have any other questions!

Here's the change that I couldn't figure out how to make backwards
compatible: https://gem5-review.googlesource.com/c/public/gem5/+/58442 I
can go into more details on that changeset, if you'd like.
Here's the change that should not be merged until we have a way to easily
select which protocols to build:
https://gem5-review.googlesource.com/c/public/gem5/+/58443 Everything up to
that change makes no difference to compile time, etc.

Cheers,
Jason

On Thu, Mar 31, 2022 at 12:36 PM Beckmann, Brad 
wrote:

> [AMD Official Use Only]
>
> Hi Jason,
>
>
>
> This is a huge undertaking.  I’m very impressed that you got this the
> work.  Congratulations!
>
>
>
> Your email covers many important aspects of the change, but one item
> missing is the motivation for the change.  Is it primarily compilation
> simplicity?  Now one can build gem5 once and use that binary to run
> multiple different protocols at different times?  If so, can you speak to
> the compilation speedup of compiling all protocols at once versus compiling
> each one individually.  Also does this change allow us to add more tests to
> check-ins because we don’t have to spend as much time building a bunch of
> individual binaries?  Some quantified data could really help motivate the
> downstream work involved to consume this change.
>
>
>
> Thanks!
>
>
>
> Brad
>
>
>
>
>
>
>
>
>
> *From:* Jason Lowe-Power via gem5-dev 
> *Sent:* Thursday, March 31, 2022 9:42 AM
> *To:* gem5 Developer List 
> *Cc:* Jason Lowe-Power 
> *Subject:* [gem5-dev] Request for comments/reviews: Multiple Ruby
> protocols in a single binary
>
>
>
> [CAUTION: External Email]
>
> Hi all,
>
>
>
> For as long as gem5 has been gem5, you have had to build a different gem5
> binary if you want to use a different Ruby protocol. Making it possible to
> build multiple protocols has been on the roadmap for a long time (at least
> as long as I've been involved with the project).
>
>
>
> I'm excited to say that we've been able to do this (finally), and we have
> a set of changesets on gerrit for review/comments feedback.
>
>
>
> There are a couple of todo items before it's merged, and a couple of
> user-facing changes that we could not find a way to make fully backwards
> compatible. More on this below.
>
>
>
> Let me know what you think, and let me know if there are any questions!
> I'm excited to see this get in for gem5-22.0.
>
>
>
> Changes: https://gem5-review.googlesource.com/q/topic:all-ruby-protocols
> <https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgem5-review.googlesource.com%2Fq%2Ftopic%3Aall-ruby-protocols&data=04%7C01%7Cbrad.beckmann%40amd.com%7C8d109b9ce6e1484f661508da13357d22%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637843417701279262%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=eVLWd

[gem5-dev] Request for comments/reviews: Multiple Ruby protocols in a single binary

2022-03-31 Thread Jason Lowe-Power via gem5-dev
Hi all,

For as long as gem5 has been gem5, you have had to build a different gem5
binary if you want to use a different Ruby protocol. Making it possible to
build multiple protocols has been on the roadmap for a long time (at least
as long as I've been involved with the project).

I'm excited to say that we've been able to do this (finally), and we have a
set of changesets on gerrit for review/comments feedback.

There are a couple of todo items before it's merged, and a couple of
user-facing changes that we could not find a way to make fully backwards
compatible. More on this below.

Let me know what you think, and let me know if there are any questions! I'm
excited to see this get in for gem5-22.0.

Changes: https://gem5-review.googlesource.com/q/topic:all-ruby-protocols

*Non-backwards compatible changes:*
Previously each SLICC protocol used the same names for the same machine
time. E.g., MI_example has an `L1Cache_Controller` and MSI has an
`L1Cache_Controller`. These names were automatically generated from the
MachineType (L1Cache) + "_Controller". Now, since we want to be able to
compile these two protocols at the same time, we need to make sure there
are no (python) name clashes. So, these have been renamed to have the
protocol name prepended onto the machine name (e.g.,
`MI_example_L1Cache_Controller`).

For most people using Ruby, we can provide backwards compatibility. If you
simply instantiate the `L1Cache_Controller` in python, we can provide a new
factory function that does the "right" thing. However, if you inherit from
`L1Cache_Controller` to specialize the controller, this won't work.

*The user-facing change is* if you have any local ruby protocol
configuration files which use inheritance with the controllers, you will
have to update the controller classes to use the name of the protocol
prepended on the controller name.

We have updated all of the configurations that are in the gem5 repo. You
will see warnings if you use the old backwards-compatible names (including
with Ruby.py).

The only other user-facing change (I think, reviewers, please point out if
I'm wrong), is that in places that `buildEnv["PROTOCOL"]` was used to check
the protocol that was built, you will now need to use `getRubyProtocol`
(also available in `m5.defines`). However, we are currently supporting
backwards compatibility here, but there will be no warning when we drop
backwards compatibility (I expect this to be in a couple of releases).

*To do items*
- Correctly integrate this with scons (and the new kconfig). See
https://gem5-review.googlesource.com/c/public/gem5/+/58443 for a WIP that
needs to be updated.
- Update the website. Assuming there are no major flaws in our
implementation, we will update the website soon (before the changes are
committed). The main updates are the two user-facing changes described
above, but I expect some updates to how Ruby/SLICC works as well.
- Add another commit that checks if the protocol is in the list of built
protocols instead of a single protocol. I'm holding off on this one until
item #1 is complete. This will also include a new command-line parameter to
set the "main" protocol for backwards compatibility.

Cheers,
Jason
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add check for single protocol

2022-03-31 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58469 )



Change subject: mem-ruby: Add check for single protocol
..

mem-ruby: Add check for single protocol

Now that multiple protocols are built into a single binary, it's
possible that the user instantiates machines from different protocols.
Right now, Ruby doesn't allow this. This changes informs the user if
this happens with a hopefully helpful error statement.

This was tested by using machine from different protocols and the error
condition was hit.

Change-Id: I1ca4b60c360bf6fa5531291003079b39e407da26
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/slicc/symbols/StateMachine.py
3 files changed, 35 insertions(+), 3 deletions(-)



diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 91c4bc3..9d25ce8 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -104,8 +104,19 @@
 }

 void
-RubySystem::registerAbstractController(AbstractController* cntrl)
+RubySystem::registerAbstractController(AbstractController* cntrl,
+   std::string protocol_str)
 {
+// Check and enforce that controllers can only come from one protocol
+if (m_protocol_str.empty()) {
+m_protocol_str = protocol_str;
+} else {
+fatal_if(protocol_str != m_protocol_str,
+ "Ruby only supports using machines from a single  
protocol. "
+ "The current machine %s is part of the protocol %s.  
Other "

+ "controllers instantiated were part of protocol %s.",
+ cntrl->name(), protocol_str, m_protocol_str);
+}
 m_abs_cntrl_vec.push_back(cntrl);

 MachineID id = cntrl->getMachineID();
diff --git a/src/mem/ruby/system/RubySystem.hh  
b/src/mem/ruby/system/RubySystem.hh

index e16d699..b1e7b4b 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -35,6 +35,7 @@
 #ifndef __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
 #define __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__

+#include 
 #include 

 #include "base/callback.hh"
@@ -104,7 +105,7 @@
 bool functionalWrite(Packet *ptr);

 void registerNetwork(Network*);
-void registerAbstractController(AbstractController*);
+void registerAbstractController(AbstractController*, std::string);
 void registerMachineID(const MachineID& mach_id, Network* network);
 void registerRequestorIDs();

@@ -145,6 +146,8 @@
 memory::SimpleMemory *m_phys_mem;
 const bool m_access_backing_store;

+std::string m_protocol_str;
+
 //std::vector m_networks;
 std::vector> m_networks;
 std::vector m_abs_cntrl_vec;
diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 2faf19a..90f789f 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -619,7 +619,7 @@
 m_machineID.type = MachineType_${ident};
 m_machineID.num = m_version;
 m_num_controllers++;
-p.ruby_system->registerAbstractController(this);
+p.ruby_system->registerAbstractController(this, "${protocol}");

 m_in_ports = $num_in_ports;
 ''')

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58469
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1ca4b60c360bf6fa5531291003079b39e407da26
Gerrit-Change-Number: 58469
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Replace buildEnv with getRubyProtocol

2022-03-31 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58449 )



Change subject: configs: Replace buildEnv with getRubyProtocol
..

configs: Replace buildEnv with getRubyProtocol

Instead of using `buildEnv['PROTOCOL']` use the new function
`getRubyProtocol()`.

*User-facing change!*
We are deprecating the use of buildEnv['PROTOCOL'] when transitioning to
enable multiple Ruby protocols in a single binary. If you have any
configuration scripts that rely on buildEnv['PROTOCOL'] they should be
updated as shown below.

`buildEnv['PROTOCOL']` -> `getRubyProtocol()`

Change-Id: Ic4d010f93a027be03767d5306c2eee6c13ed9511
Signed-off-by: Jason Lowe-Power 
---
M configs/common/FSConfig.py
M configs/example/apu_se.py
M configs/example/gpufs/Disjoint_VIPER.py
M configs/example/ruby_random_test.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/test_caches.py
M configs/ruby/AMD_Base_Constructor.py
M configs/ruby/CHI.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/Garnet_standalone.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Three_Level_HTM.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M configs/ruby/Ruby.py
M configs/topologies/CustomMesh.py
M tests/configs/gpu-randomtest-ruby.py
M tests/configs/gpu-ruby.py
M tests/configs/rubytest-ruby.py
24 files changed, 72 insertions(+), 49 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index a7ba815..61d8958 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -41,6 +41,7 @@
 import m5
 from m5.objects import *
 from m5.util import *
+from m5.defines import *
 from common.Benchmarks import *
 from common import ObjectList

@@ -339,7 +340,7 @@
 self.system_port = self.membus.cpu_side_ports

 if ruby:
-if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
+if getRubyProtocol() == 'MI_example' and num_cpus > 1:
 fatal("The MI_example protocol cannot implement Load/Store "
   "Exclusive operations. Multicore ARM systems configured "
   "with the MI_example protocol will not work properly.")
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index b5fb9ff..6bb4151 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -34,6 +34,7 @@

 import m5
 from m5.objects import *
+from m5.defines import buildEnv, getRubyProtocol
 from m5.util import addToPath

 addToPath('../')
@@ -211,7 +212,7 @@
 ## Sanity Check 

 # Currently the gpu model requires ruby
-if buildEnv['PROTOCOL'] == 'None':
+if getRubyProtocol() == 'None':
 fatal("GPU model requires ruby")

 # Currently the gpu model requires only timing or detailed CPU
@@ -252,7 +253,7 @@
 # means pipeline initiates a acquire/release operation at kernel  
launch/end.

 # VIPER protocol is write-through based, and thus only impl_kern_launch_acq
 # needs to set.
-if (buildEnv['PROTOCOL'] == 'GPU_VIPER'):
+if (getRubyProtocol() == 'GPU_VIPER'):
 shader.impl_kern_launch_acq = True
 shader.impl_kern_end_rel = False
 else:
diff --git a/configs/example/gpufs/Disjoint_VIPER.py  
b/configs/example/gpufs/Disjoint_VIPER.py

index 8ddaeac..65d3d2f 100644
--- a/configs/example/gpufs/Disjoint_VIPER.py
+++ b/configs/example/gpufs/Disjoint_VIPER.py
@@ -27,7 +27,7 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.

-from m5.defines import buildEnv
+from m5.defines import getRubyProtocol
 from m5.objects import *
 from m5.util import fatal

@@ -45,7 +45,7 @@

 class Disjoint_VIPER(RubySystem):
 def __init__(self):
-if buildEnv['PROTOCOL'] != "GPU_VIPER":
+if getRubyProtocol() != "GPU_VIPER":
 fatal("This ruby config only supports the GPU_VIPER protocol")

 super(Disjoint_VIPER, self).__init__()
diff --git a/configs/example/ruby_random_test.py  
b/configs/example/ruby_random_test.py

index edc8ee8..7849cae 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -27,7 +27,7 @@

 import m5
 from m5.objects import *
-from m5.defines import buildEnv
+from m5.defines import getRubyProtocol
 from m5.util import addToPath
 import os, argparse, sys

@@ -79,7 +79,7 @@

 # Check the protocol
 check_flush = False
-if buildEnv['PROTOCOL'] == 'MOESI_hammer':
+if getRubyProtocol() == '

[gem5-dev] Change in gem5/gem5[develop]: stdlib,mem-ruby: Use protocol-spec. names

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58440 )



Change subject: stdlib,mem-ruby: Use protocol-spec. names
..

stdlib,mem-ruby: Use protocol-spec. names

Update the standard library Ruby protocols to use the protocol-specific
class names instead of the deprecated general names.

Unfortunately, some code became duplicated between similar controllers.
I tried multiple inheritance, but it didn't work out for me. I think the
correct solution is to move some of the shared code down into the
generated python. That's out of the scope for these changes.

Change-Id: I3444bee3c2917dcbe92b600b85e60244129aad35
Signed-off-by: Jason Lowe-Power 
---
M src/python/SConscript
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py

12 files changed, 160 insertions(+), 280 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index bb069f5..30c0ec5 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -106,14 +106,6 @@
 'gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies.ruby.caches',
 'gem5/components/cachehierarchies/ruby/caches/__init__.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_directory.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level',
 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/__init__.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level',
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py

deleted file mode 100644
index e39a38c..000
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py

+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF S

[gem5-dev] Change in gem5/gem5[develop]: WIP: mem-ruby: Build gem5 binary with all protocols

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58443 )



Change subject: WIP: mem-ruby: Build gem5 binary with all protocols
..

WIP: mem-ruby: Build gem5 binary with all protocols

This changeset is hacky just to test out the build. It should not be
committed as-is. A better solution to the configuration is required
before committing as this increases the build time significantly.

Change-Id: I3187e0b884c185380bb23558f4b8e37432dd3bfb
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/protocol/SConscript
M src/mem/ruby/protocol/SConsopts
2 files changed, 18 insertions(+), 2 deletions(-)



diff --git a/src/mem/ruby/protocol/SConscript  
b/src/mem/ruby/protocol/SConscript

index 550dd73..bf0658f 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -116,7 +116,10 @@

 env.Append(BUILDERS={'SLICC' : slicc_builder})

-for protocol in [env['CONF']['PROTOCOL']]:
+if env['CONF']['BUILD_GPU']:
+env['ALL_PROTOCOLS'].append('GPU_VIPER')
+
+for protocol in env['ALL_PROTOCOLS']:
 if protocol == "None":
 continue
 protocol_dir = None
diff --git a/src/mem/ruby/protocol/SConsopts  
b/src/mem/ruby/protocol/SConsopts

index 2fcc57a..1009e22 100644
--- a/src/mem/ruby/protocol/SConsopts
+++ b/src/mem/ruby/protocol/SConsopts
@@ -31,7 +31,6 @@
 Import('*')

 main.Append(ALL_PROTOCOLS=[
-'GPU_VIPER',
 'MOESI_AMD_Base',
 'MESI_Two_Level',
 'MESI_Three_Level',

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[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: Procotol-spec. names in CHI

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58439 )



Change subject: configs,mem-ruby: Procotol-spec. names in CHI
..

configs,mem-ruby: Procotol-spec. names in CHI

Use the protocol-specific controller names in CHI.

**Important**: This could change some scripts. As long as people use
CHI_config (likely), this shouldn't be a problem, but if you have a
different version of CHI_config.py locally, you will need to make the
following updates:

`Cache_Controller` -> `CHI_Cache_Controller`
`Memory_Controller` -> `CHI_Memory_Controller`

Website updates coming soon!

Change-Id: I7afdcede884ac5f9a9a76cc3d3dd35941e4e2faa
Signed-off-by: Jason Lowe-Power 
---
M configs/ruby/CHI_config.py
M src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
M src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
3 files changed, 35 insertions(+), 13 deletions(-)



diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py
index b596efa..8eb7aed 100644
--- a/configs/ruby/CHI_config.py
+++ b/configs/ruby/CHI_config.py
@@ -173,7 +173,7 @@
 class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
 ordered = True

-class CHI_Cache_Controller(Cache_Controller):
+class Base_CHI_Cache_Controller(CHI_Cache_Controller):
 '''
 Default parameters for a Cache controller
 The Cache_Controller can also be used as a DMA requester or as
@@ -181,8 +181,8 @@
 '''

 def __init__(self, ruby_system):
-super(CHI_Cache_Controller, self).__init__(
-version = Versions.getVersion(Cache_Controller),
+super(Base_CHI_Cache_Controller, self).__init__(
+version = Versions.getVersion(CHI_Cache_Controller),
 ruby_system = ruby_system,
 mandatoryQueue = MessageBuffer(),
 prefetchQueue = MessageBuffer(),
@@ -200,7 +200,7 @@
 # timeouts on unique lines when a store conditional fails
 self.sc_lock_enabled = False

-class CHI_L1Controller(CHI_Cache_Controller):
+class CHI_L1Controller(Base_CHI_Cache_Controller):
 '''
 Default parameters for a L1 Cache controller
 '''
@@ -232,7 +232,7 @@
 self.number_of_snoop_TBEs = 4
 self.unify_repl_TBEs = False

-class CHI_L2Controller(CHI_Cache_Controller):
+class CHI_L2Controller(Base_CHI_Cache_Controller):
 '''
 Default parameters for a L2 Cache controller
 '''
@@ -264,7 +264,7 @@
 self.number_of_snoop_TBEs = 16
 self.unify_repl_TBEs = False

-class CHI_HNFController(CHI_Cache_Controller):
+class CHI_HNFController(Base_CHI_Cache_Controller):
 '''
 Default parameters for a coherent home node (HNF) cache controller
 '''
@@ -297,7 +297,7 @@
 self.number_of_snoop_TBEs = 1 # should not receive any snoop
 self.unify_repl_TBEs = False

-class CHI_DMAController(CHI_Cache_Controller):
+class CHI_DMAController(Base_CHI_Cache_Controller):
 '''
 Default parameters for a DMA controller
 '''
@@ -545,8 +545,8 @@
 def __init__(self, ruby_system, parent):
 super(CHI_SNF_Base, self).__init__(ruby_system)

-self._cntrl = Memory_Controller(
-  version = Versions.getVersion(Memory_Controller),
+self._cntrl = CHI_Memory_Controller(
+  version =  
Versions.getVersion(CHI_Memory_Controller),

   ruby_system = ruby_system,
   triggerQueue = TriggerMessageBuffer(),
   responseFromMemory = MessageBuffer(),
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py

index e8797b6..285cd68 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
@@ -29,7 +29,7 @@
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.abstract_core import AbstractCore

-from m5.objects import Cache_Controller, MessageBuffer, RubyNetwork
+from m5.objects import CHI_Cache_Controller, MessageBuffer, RubyNetwork

 import math

@@ -45,7 +45,7 @@
 class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
 ordered = True

-class AbstractNode(Cache_Controller):
+class AbstractNode(CHI_Cache_Controller):
 """A node is the abstract unit for caches in the CHI protocol.

 You can extend the AbstractNode to create caches (private or shared)  
and
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Use function for backwards compat. ruby

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58442 )



Change subject: mem-ruby: Use function for backwards compat. ruby
..

mem-ruby: Use function for backwards compat. ruby

Instead of simply renaming the class, add a function which can be
evaluated at runtime to get the new class name. Note that this will
break any code which uses these classes as a base class. This should be
fixed in prior changes.

Change-Id: Id0ff17026d89322f8506ffb0d0fb75eb3725d111
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/StateMachine.py
1 file changed, 28 insertions(+), 7 deletions(-)



diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 2a0d6a4..2faf19a 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -268,20 +268,26 @@

 code.dedent()

-# Needed for backwards compatibility while there is only one  
protocol
-# compiled. When moving to multiple protocols in the gem5 binary,  
this

-# will need to change.
+# Needed for backwards compatibility. This redefines the function  
in
+# the same way for every protocol, but it uses the  
`getRubyProtocol`
+# function to dynamically select the machine to use. Having  
multiple
+# copies of this function is not ideal, but generating a  
separate .py

+# for MachineType was not feasible.
+# This will be removed in a later version of gem5.
 code('''

-from m5.defines import buildEnv
+from m5.defines import getRubyProtocol
+from m5 import objects
 from m5.util import warn

-if getRubyProtocol() == "${protocol}":
+def ${c_ident}(**args):
 warn(
-"${c_indent} is deprecated. Use %s_${c_indent} instead",
+"${c_ident} is deprecated. Use %s_${c_ident} instead",
 getRubyProtocol()
 )
-${c_ident} = ${py_ident}
+full_name = getRubyProtocol() + "_${c_ident}"
+cls = getattr(objects, full_name)
+return cls(**args)
 ''')

 code.write(path, '%s.py' % gen_filename)

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby,configs: Update AMD protos with new names

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58441 )



Change subject: mem-ruby,configs: Update AMD protos with new names
..

mem-ruby,configs: Update AMD protos with new names

Update the MOESI_AMD_Base and GPU_VIPER configuration files with the new
full protocol-specific names for the controllers instead of the
deprecated names.

Note: If you have any files which use the `CntrlBase` base, you will
likely need to update the class names that you are inheriting from.

Change-Id: I623fea7dd4cd151f7b15fe7cb43f8a4c45492d89
Signed-off-by: Jason Lowe-Power 
---
M configs/ruby/GPU_VIPER.py
M configs/ruby/MOESI_AMD_Base.py
2 files changed, 25 insertions(+), 8 deletions(-)



diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index c73995f..9f341c5 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -85,7 +85,7 @@
 self.assoc = assoc
 self.replacement_policy = TreePLRURP()

-class CPCntrl(CorePair_Controller, CntrlBase):
+class CPCntrl(GPU_VIPER_CorePair_Controller, CntrlBase):

 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
@@ -134,7 +134,7 @@
 self.resourceStalls = options.no_tcc_resource_stalls
 self.replacement_policy = TreePLRURP()

-class TCPCntrl(TCP_Controller, CntrlBase):
+class TCPCntrl(GPU_VIPER_TCP_Controller, CntrlBase):

 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
@@ -264,7 +264,7 @@
 self.replacement_policy = TreePLRURP()


-class TCCCntrl(TCC_Controller, CntrlBase):
+class TCCCntrl(GPU_VIPER_TCC_Controller, CntrlBase):
 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
 self.L2cache = TCC()
@@ -293,7 +293,7 @@
 self.resourceStalls = False
 self.replacement_policy = TreePLRURP()

-class L3Cntrl(L3Cache_Controller, CntrlBase):
+class L3Cntrl(GPU_VIPER_L3Cache_Controller, CntrlBase):
 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
 self.L3cache = L3Cache()
@@ -314,7 +314,7 @@
 self.probeToL3 = probe_to_l3
 self.respToL3 = resp_to_l3

-class DirCntrl(Directory_Controller, CntrlBase):
+class DirCntrl(GPU_VIPER_Directory_Controller, CntrlBase):
 def create(self, options, dir_ranges, ruby_system, system):
 self.version = self.versionCount()

diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 12b8771..0833915 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -83,7 +83,7 @@
 self.assoc = options.l2_assoc
 self.replacement_policy = TreePLRURP()

-class CPCntrl(CorePair_Controller, CntrlBase):
+class CPCntrl(MOESI_AMD_Base_CorePair_Controller, CntrlBase):

 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
@@ -139,7 +139,7 @@
 self.resourceStalls = options.no_resource_stalls
 self.replacement_policy = TreePLRURP()

-class L3Cntrl(L3Cache_Controller, CntrlBase):
+class L3Cntrl(MOESI_AMD_Base_L3Cache_Controller, CntrlBase):
 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
 self.L3cache = L3Cache()
@@ -161,7 +161,7 @@
 self.probeToL3 = probe_to_l3
 self.respToL3 = resp_to_l3

-class DirCntrl(Directory_Controller, CntrlBase):
+class DirCntrl(MOESI_AMD_Base_Directory_Controller, CntrlBase):
 def create(self, options, dir_ranges, ruby_system, system):
 self.version = self.versionCount()


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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Use shared and per-protocol SLICC files

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58431 )



Change subject: mem-ruby: Use shared and per-protocol SLICC files
..

mem-ruby: Use shared and per-protocol SLICC files

This changes extends SLICC to understand two different kinds of slicc
files: files that are protocol-specific and files that are shared or
included between different protocols.

Each declaration in SLICC can now be shared or not. If it is shared,
then we can take a different action in the code generation (e.g., wrap
in a namespace).

*Developer facing change*
Removes the RubySlicc_interfaces.slicc file from the SLICC includes of
every protocol.

Changes required: If you have a custom protocol, you will need to remove
the line `include "RubySlicc_interfaces.slicc" from your .slicc file.

Change-Id: Ia6c2dafe2b8fe86749a13d17daa885bddd166855
Signed-off-by: Jason Lowe-Power 
---
M src/learning_gem5/part3/MSI.slicc
M src/mem/ruby/protocol/GPU_VIPER.slicc
M src/mem/ruby/protocol/Garnet_standalone.slicc
M src/mem/ruby/protocol/MESI_Three_Level.slicc
M src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc
M src/mem/ruby/protocol/MESI_Two_Level.slicc
M src/mem/ruby/protocol/MI_example.slicc
M src/mem/ruby/protocol/MOESI_AMD_Base.slicc
M src/mem/ruby/protocol/MOESI_CMP_directory.slicc
M src/mem/ruby/protocol/MOESI_CMP_token.slicc
M src/mem/ruby/protocol/MOESI_hammer.slicc
M src/mem/ruby/protocol/RubySlicc_interfaces.slicc
M src/mem/ruby/protocol/SConscript
M src/mem/ruby/protocol/chi/CHI.slicc
M src/mem/slicc/ast/DeclAST.py
M src/mem/slicc/ast/DeclListAST.py
M src/mem/slicc/ast/EnumDeclAST.py
M src/mem/slicc/ast/StateDeclAST.py
M src/mem/slicc/ast/TypeDeclAST.py
M src/mem/slicc/main.py
M src/mem/slicc/parser.py
M src/mem/slicc/symbols/SymbolTable.py
M src/mem/slicc/symbols/Type.py
23 files changed, 104 insertions(+), 45 deletions(-)



diff --git a/src/learning_gem5/part3/MSI.slicc  
b/src/learning_gem5/part3/MSI.slicc

index c6fdc50..4c02fcb 100644
--- a/src/learning_gem5/part3/MSI.slicc
+++ b/src/learning_gem5/part3/MSI.slicc
@@ -1,5 +1,4 @@
 protocol "MSI";
-include "RubySlicc_interfaces.slicc";
 include "MSI-msg.sm";
 include "MSI-cache.sm";
 include "MSI-dir.sm";
diff --git a/src/mem/ruby/protocol/GPU_VIPER.slicc  
b/src/mem/ruby/protocol/GPU_VIPER.slicc

index 196058b..2a89d02 100644
--- a/src/mem/ruby/protocol/GPU_VIPER.slicc
+++ b/src/mem/ruby/protocol/GPU_VIPER.slicc
@@ -1,5 +1,4 @@
 protocol "GPU_VIPER";
-include "RubySlicc_interfaces.slicc";
 include "MOESI_AMD_Base-msg.sm";
 include "MOESI_AMD_Base-dir.sm";
 include "MOESI_AMD_Base-dma.sm";
diff --git a/src/mem/ruby/protocol/Garnet_standalone.slicc  
b/src/mem/ruby/protocol/Garnet_standalone.slicc

index e467f34..8c856af 100644
--- a/src/mem/ruby/protocol/Garnet_standalone.slicc
+++ b/src/mem/ruby/protocol/Garnet_standalone.slicc
@@ -1,5 +1,4 @@
 protocol "Garnet_standalone";
-include "RubySlicc_interfaces.slicc";
 include "Garnet_standalone-msg.sm";
 include "Garnet_standalone-cache.sm";
 include "Garnet_standalone-dir.sm";
diff --git a/src/mem/ruby/protocol/MESI_Three_Level.slicc  
b/src/mem/ruby/protocol/MESI_Three_Level.slicc

index a24b11c..d37b937 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level.slicc
+++ b/src/mem/ruby/protocol/MESI_Three_Level.slicc
@@ -1,5 +1,4 @@
 protocol "MESI_Three_Level";
-include "RubySlicc_interfaces.slicc";
 include "MESI_Two_Level-msg.sm";
 include "MESI_Three_Level-msg.sm";
 include "MESI_Three_Level-L0cache.sm";
diff --git a/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc  
b/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc

index 4ec31b5..88afc2f 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc
+++ b/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc
@@ -1,5 +1,4 @@
 protocol "MESI_Three_Level_HTM";
-include "RubySlicc_interfaces.slicc";
 include "MESI_Two_Level-msg.sm";
 include "MESI_Three_Level-msg.sm";
 include "MESI_Three_Level_HTM-L0cache.sm";
diff --git a/src/mem/ruby/protocol/MESI_Two_Level.slicc  
b/src/mem/ruby/protocol/MESI_Two_Level.slicc

index b5bf104..e0f6dda 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level.slicc
+++ b/src/mem/ruby/protocol/MESI_Two_Level.slicc
@@ -1,5 +1,4 @@
 protocol "MESI_Two_Level";
-include "RubySlicc_interfaces.slicc";
 include "MESI_Two_Level-msg.sm";
 include "MESI_Two_Level-L1cache.sm";
 include "MESI_Two_Level-L2cache.sm";
diff --git a/src/mem/ruby/protocol/MI_example.slicc  
b/src/mem/ruby/protocol/MI_example.slicc

index 7061478..b3c1585 100644
--- a/src/mem/ruby/protocol/MI_example.slicc
+++ b/src/mem/ruby/protocol/MI_example.slicc
@@ -1,5 +1,4 

[gem5-dev] Change in gem5/gem5[develop]: scons: Fix bug in error message

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58429 )



Change subject: scons: Fix bug in error message
..

scons: Fix bug in error message

The variable p doesn't exist in the context. Just remove the extra
print. Even without the specific variable printed the error message is
pretty helpful.

Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793
Signed-off-by: Jason Lowe-Power 
---
M build_tools/sim_object_param_struct_hh.py
1 file changed, 15 insertions(+), 1 deletion(-)



diff --git a/build_tools/sim_object_param_struct_hh.py  
b/build_tools/sim_object_param_struct_hh.py

index ff525ee..261ac9b 100644
--- a/build_tools/sim_object_param_struct_hh.py
+++ b/build_tools/sim_object_param_struct_hh.py
@@ -73,7 +73,7 @@
 try:
 ptypes = [p.ptype for p in params]
 except:
-print(sim_object, p, p.ptype_str)
+print(sim_object)
 print(params)
 raise


--
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Gerrit-Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793
Gerrit-Change-Number: 58429
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[gem5-dev] Change in gem5/gem5[develop]: python: Add function to get ruby protocol

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58430 )



Change subject: python: Add function to get ruby protocol
..

python: Add function to get ruby protocol

This changeset moves the auto-generated defines.py file to _defines and
replaces it with an explicit defines.py file in the m5 module. This
explicit module also includes a function to expose the ruby protocol.
This will make it easier to provide backwards compatibility and have a
"main" protocol as we add support for multiple protocols in a single
binary.

Change-Id: Id632d4af7d1e60f2c3ea0c492c0cba26c6d9af92
Signed-off-by: Jason Lowe-Power 
---
M src/SConscript
M src/python/SConscript
A src/python/m5/defines.py
3 files changed, 52 insertions(+), 2 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index d55520b..f356f00 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -609,9 +609,9 @@
 code.write(target[0].abspath)

 # Generate a file with all of the compile options in it
-env.Command('python/m5/defines.py', ToValue(dict(build_env)),
+env.Command('python/m5/_defines.py', ToValue(dict(build_env)),
 MakeAction(makeDefinesPyFile, Transform("DEFINES", 0)))
-PySource('m5', 'python/m5/defines.py')
+PySource('m5', 'python/m5/_defines.py')

 # Generate a file that wraps the basic top level files
 gem5py_env.Command('python/m5/info.py',
diff --git a/src/python/SConscript b/src/python/SConscript
index 343a696..bb069f5 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -219,6 +219,7 @@
 PySource('m5', 'm5/SimObject.py')
 PySource('m5', 'm5/core.py')
 PySource('m5', 'm5/debug.py')
+PySource('m5', 'm5/defines.py')
 PySource('m5', 'm5/event.py')
 PySource('m5', 'm5/main.py')
 PySource('m5', 'm5/options.py')
diff --git a/src/python/m5/defines.py b/src/python/m5/defines.py
new file mode 100644
index 000..9c1c98d
--- /dev/null
+++ b/src/python/m5/defines.py
@@ -0,0 +1,32 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from ._defines import buildEnv
+
+def getRubyProtocol() -> str:
+return buildEnv["PROTOCOL"]
+
+__all__ = ["buildEnv", "getRubyProtocol"]

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Update HTML output to include protocol

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58437 )



Change subject: mem-ruby: Update HTML output to include protocol
..

mem-ruby: Update HTML output to include protocol

Move the html output to be in a subdirectory with the protocol name.

Change-Id: I1510d2d5a531cc6db74d10a0478c23bc8a836a26
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/SymbolTable.py
1 file changed, 16 insertions(+), 0 deletions(-)



diff --git a/src/mem/slicc/symbols/SymbolTable.py  
b/src/mem/slicc/symbols/SymbolTable.py

index be3147b..1b29b38 100644
--- a/src/mem/slicc/symbols/SymbolTable.py
+++ b/src/mem/slicc/symbols/SymbolTable.py
@@ -164,6 +164,10 @@
 def writeHTMLFiles(self, path):
 makeDir(path)

+# Append the protocol to the path and make that directory
+path = os.path.join(path, self.slicc.protocol)
+makeDir(path)
+
 machines = list(self.getAllType(StateMachine))
 if len(machines) > 1:
 name = "%s_table.html" % machines[0].ident

--
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Gerrit-Change-Id: I1510d2d5a531cc6db74d10a0478c23bc8a836a26
Gerrit-Change-Number: 58437
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Move getNumControllers out of machines

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58435 )



Change subject: mem-ruby: Move getNumControllers out of machines
..

mem-ruby: Move getNumControllers out of machines

Move the getNumControllers function out of the protocol-specific
machine definitions (which are now in their own namespaces) to a
BaseMachine class that the protocol-specific machines inherit
from. This design was the simplest way to keep backwards compatibility.

The one caveat is that this design means that while you can compile
multiple protocols into one binary, you cannot use the same machine type
from different protocols in one simulation. This is the current
assumption, so it shouldn't change anything for users.

Change-Id: If9eeb78c24eb5076956b9f44fa04c7e6eb0f0dd4
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/Type.py
2 files changed, 44 insertions(+), 23 deletions(-)



diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 3ef6b5b..2a0d6a4 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -342,12 +342,11 @@

 extern std::stringstream ${ident}_transitionComment;

-class $c_ident : public AbstractController
+class $c_ident : public AbstractController, Base${ident}Machine
 {
   public:
 typedef ${py_ident}Params Params;
 $c_ident(const Params &p);
-static int getNumControllers();
 void init();

 MessageBuffer *getMandatoryQueue() const;
@@ -432,7 +431,6 @@

 static std::vector eventVec;
 static std::vector > transVec;
-static int m_num_controllers;

 // Internal functions
 ''')
@@ -596,7 +594,6 @@
 namespace ${protocol}
 {

-int $c_ident::m_num_controllers = 0;
 std::vector  $c_ident::eventVec;
 std::vector >  $c_ident::transVec;

@@ -1030,12 +1027,6 @@
 return m_counters[state][event];
 }

-int
-$c_ident::getNumControllers()
-{
-return m_num_controllers;
-}
-
 MessageBuffer*
 $c_ident::getMandatoryQueue() const
 {
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 282f55a..2973046 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -583,6 +583,20 @@
 MachineID get${{enum.ident}}MachineID(NodeID RubyNode);
 ''')

+# Machine types are expected to be overridden by protocol-
+# specific classes.
+if self.isMachineType:
+code('''
+
+class Base${{enum.ident}}Machine {
+  protected:
+static int m_num_controllers;
+  public:
+static int getNumControllers() { return m_num_controllers; }
+};
+
+''')
+
 if self.isStateDecl:
 code('''

@@ -699,10 +713,6 @@
 ''')

 if self.isMachineType:
-for enum in self.enums.values():
-if enum.primary:
-code('#include "mem/ruby/protocol/${{protocol}}/'
-'${{enum.ident}}_Controller.hh"')
 code('#include "mem/ruby/common/MachineID.hh"')

 code('''
@@ -858,13 +868,9 @@
 code.indent()
 code('  case ${{self.c_ident}}_NUM:')
 for enum in reversed(list(self.enums.values())):
-# Check if there is a defined machine with this type
-if enum.primary:
-code('''
-base += ${{protocol}}::${{enum.ident}}_Controller::getNumControllers();
+code('''
+base += Base${{enum.ident}}Machine::getNumControllers();
 ''')
-else:
-code('base += 0;')
 code('[[fallthrough]];')
 code('  case ${{self.c_ident}}_${{enum.ident}}:')
 code('break;')
@@ -890,9 +896,8 @@
 # For each field
 for enum in self.enums.values():
 code('case ${{self.c_ident}}_${{enum.ident}}:')
-if enum.primary:
-code('''
-return ${{protocol}}::${{enum.ident}}_Controller::getNumControllers();
+code('''
+return Base${{enum.ident}}Machine::getNumControllers();
 ''')

 # total num
@@ -916,6 +921,11 @@
   return mach;
 }
 ''')
+if self.isMachineType:
+code('''
+
+int Base${{enum.ident}}Machine::m_num_controllers = 0;
+''')

 # For protocol-specific types, close the protocol namespace
 if not self.shared:

--
To view, visit https://gem5-review

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Rename SLICC SimObjs with compatibility

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58434 )



Change subject: mem-ruby: Rename SLICC SimObjs with compatibility
..

mem-ruby: Rename SLICC SimObjs with compatibility

Rename all SLICC generated SimObjects to have the protocol in their
name. This will allow for two different protocols to have the same
machine names (e.g., L1Cache). For compatiblity, we check to see if the
current protocol that is built matches the SimObject's protocol and
export the backwards-compatible name.

Change-Id: I2f1b2a541778de5b6316348386927141485c19b6
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/protocol/SConscript
M src/mem/slicc/ast/MachineAST.py
M src/mem/slicc/symbols/StateMachine.py
3 files changed, 50 insertions(+), 8 deletions(-)



diff --git a/src/mem/ruby/protocol/SConscript  
b/src/mem/ruby/protocol/SConscript

index 62e3e10..162c0db 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -124,7 +124,7 @@
 elif s.endswith('.py'):
 filename = os.path.basename(s)
 # We currently only expect ${ident}_Controller.py to be generated,  
and

-# for it to contain a single SimObject with the same name.
+# for it to contain a single SimObject with the same name +  
protocol.

 assert(filename.endswith('_Controller.py'))
-SimObject(f, sim_objects=[os.path.splitext(filename)[0]])
+SimObject(f,  
sim_objects=[protocol+'_'+os.path.splitext(filename)[0]])


diff --git a/src/mem/slicc/ast/MachineAST.py  
b/src/mem/slicc/ast/MachineAST.py

index 4114f01..17116da 100644
--- a/src/mem/slicc/ast/MachineAST.py
+++ b/src/mem/slicc/ast/MachineAST.py
@@ -43,9 +43,15 @@
 def files(self, parent=None):
 import os
 file_prefix = os.path.join(self.slicc.protocol, self.ident)
+# Can't have multiple python simobject files with the same name
+# So, we have to prepend the protocol name to the .py file
+py_prefix = os.path.join(
+self.slicc.protocol,
+self.slicc.protocol + '_' + self.ident
+)
 s = set(('%s_Controller.cc' % file_prefix,
  '%s_Controller.hh' % file_prefix,
- '%s_Controller.py' % file_prefix,
+ '%s_Controller.py' % py_prefix,
  '%s_Transitions.cc' % file_prefix,
  '%s_Wakeup.cc' % file_prefix))

diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 2540b0d..3ef6b5b 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -236,7 +236,7 @@
 ident = self.ident

 protocol = self.symtab.slicc.protocol
-py_ident = "%s_Controller" % ident
+py_ident = f"{protocol}_{ident}_Controller"
 c_ident = "%s_Controller" % self.ident
 gen_filename = f"{protocol}/{py_ident}"

@@ -267,6 +267,23 @@
"in StateMachine.py",  
param.type_ast.type.c_ident)


 code.dedent()
+
+# Needed for backwards compatibility while there is only one  
protocol
+# compiled. When moving to multiple protocols in the gem5 binary,  
this

+# will need to change.
+code('''
+
+from m5.defines import buildEnv
+from m5.util import warn
+
+if getRubyProtocol() == "${protocol}":
+warn(
+"${c_indent} is deprecated. Use %s_${c_indent} instead",
+getRubyProtocol()
+)
+${c_ident} = ${py_ident}
+''')
+
 code.write(path, '%s.py' % gen_filename)


@@ -275,8 +292,11 @@
 code = self.symtab.codeFormatter()
 ident = self.ident
 c_ident = "%s_Controller" % self.ident
-header_string = self.symtab.slicc.protocol + '_' + self.ident
-gen_filename = f"{self.symtab.slicc.protocol}/{c_ident}"
+
+protocol = self.symtab.slicc.protocol
+header_string = protocol + '_' + self.ident
+gen_filename = f"{protocol}/{c_ident}"
+py_ident = f"{protocol}_{ident}_Controller"

 code('''
 // Created by slicc definition of Module "${{self.short}}"
@@ -292,7 +312,7 @@
 #include "mem/ruby/protocol/TransitionResult.hh"
 #include "mem/ruby/protocol/${protocol}/Types.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
-#include "params/$c_ident.hh"
+#include "params/$py_ident.hh"

 ''')

@@ -325,7 +345,7 @@
 class $c_ident : public AbstractController
 {
   public:
-typedef ${c_ident}Params Params;
+ty

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Move protocol files to subdir

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58433 )



Change subject: mem-ruby: Move protocol files to subdir
..

mem-ruby: Move protocol files to subdir

Move all generated protocol-specific files to a subdirectory with the
protocol's name.

This change also updates SLICC to have separate variables for the
filename, c identifier and python identifier instead of just using
variations of the c identifier.

Change-Id: I62f69a4606b030ee23cb2d96493f3257a6923748
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/ast/EnumDeclAST.py
M src/mem/slicc/ast/MachineAST.py
M src/mem/slicc/ast/StateDeclAST.py
M src/mem/slicc/ast/TypeDeclAST.py
M src/mem/slicc/parser.py
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/SymbolTable.py
M src/mem/slicc/symbols/Type.py
8 files changed, 109 insertions(+), 51 deletions(-)



diff --git a/src/mem/slicc/ast/EnumDeclAST.py  
b/src/mem/slicc/ast/EnumDeclAST.py

index 5a3fd7a..3e71dc0 100644
--- a/src/mem/slicc/ast/EnumDeclAST.py
+++ b/src/mem/slicc/ast/EnumDeclAST.py
@@ -46,6 +46,8 @@
 ident = "%s_%s" % (parent, self.type_ast.ident)
 else:
 ident = self.type_ast.ident
+if not self.shared:
+ident = f"{self.slicc.protocol}/{ident}"
 s = set(("%s.hh" % ident, "%s.cc" % ident))
 return s

diff --git a/src/mem/slicc/ast/MachineAST.py  
b/src/mem/slicc/ast/MachineAST.py

index 7434d6b..4114f01 100644
--- a/src/mem/slicc/ast/MachineAST.py
+++ b/src/mem/slicc/ast/MachineAST.py
@@ -41,11 +41,13 @@
 return "[Machine: %r]" % self.ident

 def files(self, parent=None):
-s = set(('%s_Controller.cc' % self.ident,
- '%s_Controller.hh' % self.ident,
- '%s_Controller.py' % self.ident,
- '%s_Transitions.cc' % self.ident,
- '%s_Wakeup.cc' % self.ident))
+import os
+file_prefix = os.path.join(self.slicc.protocol, self.ident)
+s = set(('%s_Controller.cc' % file_prefix,
+ '%s_Controller.hh' % file_prefix,
+ '%s_Controller.py' % file_prefix,
+ '%s_Transitions.cc' % file_prefix,
+ '%s_Wakeup.cc' % file_prefix))

 s |= self.decls.files(self.ident)
 return s
diff --git a/src/mem/slicc/ast/StateDeclAST.py  
b/src/mem/slicc/ast/StateDeclAST.py

index 4100296..1fffaa1 100644
--- a/src/mem/slicc/ast/StateDeclAST.py
+++ b/src/mem/slicc/ast/StateDeclAST.py
@@ -45,6 +45,8 @@
 ident = "%s_%s" % (parent, self.type_ast.ident)
 else:
 ident = self.type_ast.ident
+if not self.shared:
+ident = f"{self.slicc.protocol}/{ident}"
 s = set(("%s.hh" % ident, "%s.cc" % ident))
 return s

diff --git a/src/mem/slicc/ast/TypeDeclAST.py  
b/src/mem/slicc/ast/TypeDeclAST.py

index 9748178..000d66e 100644
--- a/src/mem/slicc/ast/TypeDeclAST.py
+++ b/src/mem/slicc/ast/TypeDeclAST.py
@@ -46,6 +46,8 @@
 ident = "%s_%s" % (parent, self.type_ast.ident)
 else:
 ident = self.type_ast.ident
+if not self.shared:
+ident = f"{self.slicc.protocol}/{ident}"
 return set(("%s.hh" % ident, "%s.cc" % ident))

 def generate(self):
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index e2b0a64..78a16bf 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -97,7 +97,7 @@
 self.symtab.writeHTMLFiles(html_path)

 def files(self):
-f = set(['Types.hh'])
+f = set([os.path.join(self.protocol, 'Types.hh')])

 f |= self.decl_list.files()

diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index e220731..2540b0d 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -235,8 +235,10 @@
 code = self.symtab.codeFormatter()
 ident = self.ident

+protocol = self.symtab.slicc.protocol
 py_ident = "%s_Controller" % ident
 c_ident = "%s_Controller" % self.ident
+gen_filename = f"{protocol}/{py_ident}"

 code('''
 from m5.params import *
@@ -245,8 +247,8 @@

 class $py_ident(RubyController):
 type = '$py_ident'
-cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
-cxx_class = 'gem5::ruby::$protocol::$py_ident'
+cxx_header = 'mem/ruby/protocol/${protocol}/${c_ident}.hh'
+cxx_class = 'gem5::ruby::$protocol::$c_ident'
 ''')
 code.indent()

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby,scons: Split SLICC generic and specific

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58436 )



Change subject: mem-ruby,scons: Split SLICC generic and specific
..

mem-ruby,scons: Split SLICC generic and specific

Update the SLICC generation to be able to generate the shared files and
protocol-specific files separately.

Update the SLICC SConscript to make a separate call to SLICC for the
shared files and the protocol-specific files.

Note: The Scons changes are a bit hacky. Improvements are welcome.

Change-Id: I516a1bbe7f82e57dc4145064170f10b31683b6cd
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/protocol/SConscript
M src/mem/slicc/ast/DeclListAST.py
M src/mem/slicc/main.py
M src/mem/slicc/parser.py
M src/mem/slicc/symbols/SymbolTable.py
5 files changed, 117 insertions(+), 34 deletions(-)



diff --git a/src/mem/ruby/protocol/SConscript  
b/src/mem/ruby/protocol/SConscript

index 162c0db..550dd73 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -66,15 +66,23 @@
 assert len(source) == 1
 filepath = source[0].srcnode().abspath

+if filepath.endswith('RubySlicc_interfaces.slicc'):
+# We're working on the shared files
+filepath = None
+shared_only = True
+else:
+shared_only = False
+
 slicc = SLICC(
 filepath,
  
[os.path.join(protocol_base.abspath, 'RubySlicc_interfaces.slicc')],

 protocol_base.abspath,
+shared_only=shared_only,
 verbose=False
 )
 slicc.process()
 slicc.writeCodeFiles(output_dir.abspath, slicc_includes)
-if env['CONF']['SLICC_HTML']:
+if env['CONF']['SLICC_HTML'] and not shared_only:
 slicc.writeHTMLFiles(html_dir.abspath)

 target.extend([output_dir.File(f) for f in sorted(slicc.files())])
@@ -83,35 +91,63 @@
 def slicc_action(target, source, env):
 assert len(source) == 1
 filepath = source[0].srcnode().abspath
+
+if filepath.endswith('RubySlicc_interfaces.slicc'):
+# We're working on the shared files
+filepath = None
+shared_only = True
+else:
+shared_only = False
+
 slicc = SLICC(
 filepath,
  
[os.path.join(protocol_base.abspath, 'RubySlicc_interfaces.slicc')],

 protocol_base.abspath,
+shared_only=shared_only,
 verbose=True
 )
 slicc.process()
 slicc.writeCodeFiles(output_dir.abspath, slicc_includes)
-if env['CONF']['SLICC_HTML']:
+if env['CONF']['SLICC_HTML'] and not shared_only:
 slicc.writeHTMLFiles(html_dir.abspath)

 slicc_builder = Builder(action=MakeAction(slicc_action,  
Transform("SLICC")),

 emitter=slicc_emitter)

-protocol = env['CONF']['PROTOCOL']
-protocol_dir = None
-for path in env['PROTOCOL_DIRS']:
-if os.path.exists(path.File("%s.slicc" % protocol).abspath):
-protocol_dir = Dir(path)
-break
-
-if not protocol_dir:
-raise ValueError("Could not find {}.slicc in PROTOCOL_DIRS".format(
-protocol))
-
-sources = [ protocol_dir.File("%s.slicc" % protocol) ]
-
 env.Append(BUILDERS={'SLICC' : slicc_builder})
-nodes = env.SLICC([], sources)
+
+for protocol in [env['CONF']['PROTOCOL']]:
+if protocol == "None":
+continue
+protocol_dir = None
+for path in env['PROTOCOL_DIRS']:
+if os.path.exists(path.File("%s.slicc" % protocol).abspath):
+protocol_dir = Dir(path)
+break
+
+if not protocol_dir:
+raise ValueError("Could not find {}.slicc in PROTOCOL_DIRS".format(
+protocol))
+
+nodes = env.SLICC([], [protocol_dir.File("%s.slicc" % protocol)])
+env.Depends(nodes, slicc_depends)
+
+append = {}
+if env['CLANG']:
+append['CCFLAGS'] = '-Wno-parentheses'
+for f in nodes:
+s = str(f)
+if s.endswith('.cc'):
+Source(f, append=append)
+elif s.endswith('.py'):
+filename = os.path.basename(s)
+# We currently only expect ${ident}_Controller.py to be  
generated,

+# and for it to contain a single SimObject with the same name +
+# protocol.
+assert(filename.endswith('_Controller.py'))
+SimObject(f, sim_objects=[os.path.splitext(filename)[0]])
+
+nodes = env.SLICC([], [protocol_base.File('RubySlicc_interfaces.slicc')])
 env.Depends(nodes, slicc_depends)

 append = {}
@@ -121,10 +157,3 @@
 s = str(f)
 if s.endswith('.cc'):
 Source(f, append=append)
-elif s.endswith('.py')

[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: Protocol-spec. in learning gem5

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58438 )



Change subject: configs,mem-ruby: Protocol-spec. in learning gem5
..

configs,mem-ruby: Protocol-spec. in learning gem5

Use protocol-specific names in Learning gem5 configs. Now, we should no
longer use the generic names for the controllers (it's deprecated). This
updates Learning gem5.

Website changes coming soon. (Hopefull before I push this...)

Change-Id: I18fc5b8bb0fef7c3b8b5cea8de4f73fc0f66a1b3
Signed-off-by: Jason Lowe-Power 
---
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
2 files changed, 20 insertions(+), 4 deletions(-)



diff --git a/configs/learning_gem5/part3/msi_caches.py  
b/configs/learning_gem5/part3/msi_caches.py

index 957adf2..5abfff0 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -105,7 +105,7 @@
 self.sequencers[i].connectCpuPorts(cpu)


-class L1Cache(L1Cache_Controller):
+class L1Cache(MSI_L1Cache_Controller):

 _version = 0
 @classmethod
@@ -169,7 +169,7 @@
 self.responseFromDirOrSibling = MessageBuffer(ordered = True)
 self.responseFromDirOrSibling.in_port =  
ruby_system.network.out_port


-class DirController(Directory_Controller):
+class DirController(MSI_Directory_Controller):

 _version = 0
 @classmethod
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py  
b/configs/learning_gem5/part3/ruby_caches_MI_example.py

index b67e6b1..9e5f9cf 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -102,7 +102,7 @@
 for i,cpu in enumerate(cpus):
 self.sequencers[i].connectCpuPorts(cpu)

-class L1Cache(L1Cache_Controller):
+class L1Cache(MI_example_L1Cache_Controller):

 _version = 0
 @classmethod
@@ -157,7 +157,7 @@
 self.responseToCache = MessageBuffer(ordered = True)
 self.responseToCache.in_port = ruby_system.network.out_port

-class DirController(Directory_Controller):
+class DirController(MI_example_Directory_Controller):

 _version = 0
 @classmethod

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58438
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I18fc5b8bb0fef7c3b8b5cea8de4f73fc0f66a1b3
Gerrit-Change-Number: 58438
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Use namespaces for protocol types

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58432 )



Change subject: mem-ruby: Use namespaces for protocol types
..

mem-ruby: Use namespaces for protocol types

Wrap all protocol-specific types in `namespace `. This will
facilitate compiling multiple protocols into one binary.

There is a one-time hack to the generated `MachineType.cc` file to use
the namespace for the protocol until we generalize the machine types.

Change-Id: I5947e8ac69afe6f7ed257d7c5980ad65e9338acf
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/Type.py
2 files changed, 127 insertions(+), 4 deletions(-)



diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index a9f7373..e220731 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -246,7 +246,7 @@
 class $py_ident(RubyController):
 type = '$py_ident'
 cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
-cxx_class = 'gem5::ruby::$py_ident'
+cxx_class = 'gem5::ruby::$protocol::$py_ident'
 ''')
 code.indent()
 for param in self.config_parameters:
@@ -306,6 +306,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 extern std::stringstream ${ident}_transitionComment;

 class $c_ident : public AbstractController
@@ -463,6 +466,7 @@
 code('''
 };

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5

@@ -550,6 +554,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 int $c_ident::m_num_controllers = 0;
 std::vector  $c_ident::eventVec;
 std::vector >  $c_ident::transVec;
@@ -827,7 +834,7 @@
 AbstractController::regStats();

 // For each type of controllers, one controller of that type is picked
-// to aggregate stats of all controllers of that type.
+// to aggregate stats of all controllers of that type.
 if (m_version == 0) {

 Profiler *profiler = params().ruby_system->getProfiler();
@@ -1221,6 +1228,7 @@
 return read;
 }

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5
 ''')
@@ -1282,6 +1290,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 void
 ${ident}_Controller::wakeup()
 {
@@ -1357,6 +1368,7 @@
 }
 }

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5
 ''')
@@ -1395,6 +1407,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 TransitionResult
 ${ident}_Controller::doTransition(${ident}_Event event,
 ''')
@@ -1623,6 +1638,7 @@
 return TransitionResult_Valid;
 }

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5
 ''')
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index a9c5303..bb8ff0c 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -228,6 +228,16 @@

 namespace ruby
 {
+''')
+# For protocol-specific types, wrap in the protocol namespace
+if not self.shared:
+code('''
+
+namespace ${{protocol}}
+{
+''')
+
+code('''

 $klass ${{self.c_ident}}$parent
 {
@@ -394,7 +404,15 @@
 out << ::std::flush;
 return out;
 }
+''')
+# For protocol-specific types, close the protocol namespace
+if not self.shared:
+code('''

+} // namespace ${{protocol}}
+''')
+
+code('''
 } // namespace ruby
 } // namespace gem5

@@ -418,6 +436,16 @@

 namespace ruby
 {
+''')
+# For protocol-specific types, wrap in the protocol namespace
+if not self.shared:
+code('''
+
+namespace ${{protocol}}
+{
+''')
+
+code('''

 /** \\brief Print the state of this object */
 void
@@ -446,6 +474,13 @@
 for item in self.methods:
 code(self.methods[item].generateCode())

+# For protocol-specific types, close the protocol namespace
+if not self.shared:
+code('''
+
+} // namespace ${{protocol}}
+''')
+
 code('''
 } // namespace ruby
 } // namespace gem5
@@ -480,6 +515,13 @@
 {

 ''')
+# For protocol-specific types, wrap in the protocol namespace
+if not self.shared:
+code('''
+
+namespace ${{protocol}}
+{
+''')

 if self.isMachineType:
 code('struct MachineID;')
@@ -545,7 +587,16 @@

 ::std::ostream&
 operator<<(::std::ostream& out, const ${{self.c_ident}}& obj);
+''')

+# For protocol-specific types, close the protocol namespace
+if not self.shared:
+ 

[gem5-dev] Re: Build failed in Jenkins: nightly #177

2022-03-30 Thread Jason Lowe-Power via gem5-dev
I'm not sure why this test failed. The build artifacts look successful.

However, there seems to be a bug in which tests are selected to run. We
seem to be running duplicate tests on the x86_64 host and calling them both
x86_64 and aarch64 tests.

Jason

On Tue, Mar 29, 2022 at 11:01 PM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/177/display/redirect?page=changes>
>
> Changes:
>
> [fcrh] mem: Add SharedMemoryServer
>
> [gabe.black] arch-arm: Override makeRead and makeWrite in the ISA
> description.
>
> [gabe.black] ext: Add a cont_choice keyword to kconfiglib.
>
> [gabe.black] scons: Put all config variables in an env['CONF'] sub-dict.
>
> [gabe.black] scons: Put internal build files in a gem5.build directory.
>
> [Bobby R. Bruce] tests: Remove accidentally included "exit 0" test code
>
> [matthew.poremba] configs,gpu-compute: Support fetch from system pages
>
> [matthew.poremba] dev-hsa: Properly mask HSA packet header bits
>
> [matthew.poremba] dev-hsa: Update QCntxt readIndex in HW scheduler write
>
> [gabe.black] arch: Split up src/dest register ID creation.
>
> [srikant.bharadwaj] configs: Update memory port name in Ruby
>
>
> --
> [...truncated 3.91 MB...]
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_getarsym.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/gelf_move.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_hash.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/libelf_ar_util.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/gelf_shdr.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/gelf_cap.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_rawfile.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_open.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_getident.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/libelf_xlate.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_update.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/gelf_checksum.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/gelf_rela.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/gelf_dyn.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_fill.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_errmsg.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_next.c -> .os
>  [SHCC] X86_MESI_Two_Level/ext/libelf/elf_shnum.c -> .os
>  [  AR]  -> X86_MESI_Two_Level/ext/softfloat/libsoftfloat.a
>  [  AR]  -> X86_MESI_Two_Level/ext/libelf/libelf.a
>  [  RANLIB]  -> X86_MESI_Two_Level/ext/libelf/libelf.a
>  [  RANLIB]  -> X86_MESI_Two_Level/ext/softfloat/libsoftfloat.a
>  [LINK]  -> X86_MESI_Two_Level/gem5.opt
> /usr/bin/ld: skipping incompatible /usr/lib/libgcc_s.so.1 when searching
> for libgcc_s.so.1
> /usr/bin/ld: skipping incompatible /usr/lib/libgcc_s.so.1 when searching
> for libgcc_s.so.1
> scons: done building targets.
> *** Summary of Warnings ***
> Warning: Deprecated namespaces are not supported by this compiler.
>  Please make sure to check the mailing list for deprecation
>  announcements.
> Warning: Deleting old variant variables file
> "/nobackup/jenkins/workspace/nightl
>  y/build/variables/X86_MESI_Two_Level"
> Building the following targets. This may take a while.
> /nobackup/jenkins/workspace/nightly/build/GCN3_X86/gem5.opt
> You may want to run with only a single ISA(--isa=), use --skip-build, or
> use 'rerun'.
> Logging call to command: scons -C /nobackup/jenkins/workspace/nightly -j
> 16 --ignore-style --no-compress-debug
> /nobackup/jenkins/workspace/nightly/build/GCN3_X86/gem5.opt
> scons: Entering directory `/nobackup/jenkins/workspace/nightly'
> scons: Reading SConscript files ...
> Mkdir("/nobackup/jenkins/workspace/nightly/build/GCN3_X86/gem5.build")
> Checking for linker -Wl,--as-needed support... (cached) yes
> Checking for compiler -Wno-free-nonheap-object support... (cached) yes
> Info: Using Python config: python3-config
> Checking for C header file Python.h... (cached) yes
> Checking Python version... (cached) 3.8.10
> Checking for accept(0,0,0) in C++ library None... (cached) yes
> Checking for zlibVersion() in C++ library z... (cached) yes
> Checking for C library tcmalloc... (cached) yes
> Building in /nobackup/jenkins/workspace/nightly/build/GCN3_X86
> Using saved variables file(s)
> /nobackup/jenkins/workspace/nightly/build/GCN3_X86/gem5.build/variables
> Checking for C header file fenv.h... (cached) yes
> Checking for C header file png.h... (cached) yes
> Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached)
> yes
> Checking for C header file valgrind/valgrind.h... (cached) no
> Warning: Deprecated namespaces are not supported by this compiler.
>  Please make sure to check the mailing list for deprecation
>  announcements.
> Checking for pkg-config package hdf5-serial... (cached) ye

[gem5-dev] Re: Build failed in Jenkins: nightly #161

2022-03-16 Thread Jason Lowe-Power via gem5-dev
Thanks, Gabe!

On Tue, Mar 15, 2022 at 9:28 PM Gabe Black via gem5-dev 
wrote:

> https://gem5-review.googlesource.com/c/public/gem5/+/57749
>
> On Tue, Mar 15, 2022 at 12:59 PM Gabe Black  wrote:
>
>> It looks like the problem is that the aapcs test calls ThreadContext
>> which returns a TheISA::VecRegContainer, where since that test is for ARM
>> it *should* really be working with an ARM VecRegContainer. Because this is
>> being built for NULL, that uses the dummy versions which are not complete
>> enough to have "as" template methods like the real classes.
>>
>> I think the solution is either to restrict that test to when building
>> with ARM, or to add as<>() to the dummy classes. In the short term the
>> offending change can be reverted, or we can wait until this evening when
>> I'll have a chance to find a proper fix. This is what is right now probably
>> a unique corner case where we have a unit test which is ISA dependent, and
>> while it will *become* possible to run reasonably under any build once the
>> ThreadContext doesn't build in what data type vector registers should be,
>> in the mean time it either won't work because of this problem, or even when
>> it would work, it would be operating on an inappropriate data type.
>>
>> Gabe
>>
>> On Tue, Mar 15, 2022 at 8:13 AM Jason Lowe-Power 
>> wrote:
>>
>>> Looks like the problem is  [gabe.black] arch: Make the DummyVec... types
>>> the same size as RegVal.
>>>
>>> Can you take a look, Gabe?
>>>
>>> Thanks,
>>> Jason
>>>
>>> On Tue, Mar 15, 2022 at 1:46 AM jenkins-no-reply--- via gem5-dev <
>>> gem5-dev@gem5.org> wrote:
>>>
>>>> See <
>>>> https://jenkins.gem5.org/job/nightly/161/display/redirect?page=changes>
>>>>
>>>> Changes:
>>>>
>>>> [gabe.black] arch-x86: Fix a bug in the protected mode IRET.
>>>>
>>>> [gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.
>>>>
>>>> [gabe.black] arch-x86: Detect when entering virtual 8086 mode.
>>>>
>>>> [gabe.black] arch-x86: Tidy up the page table walker stepWalk method.
>>>>
>>>> [gabe.black] arch-x86: Use the right bits in the page table walker.
>>>>
>>>> [gabe.black] arch-x86: Make the flags microops handle reserved bits
>>>> better.
>>>>
>>>> [matthew.poremba] sim-se: Initialize shared page table base upon clone
>>>>
>>>> [Bobby R. Bruce] util-docker: Adding docker-compose.yaml
>>>>
>>>> [Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests
>>>>
>>>> [Bobby R. Bruce] util: Remove util/cloudbuild
>>>>
>>>> [gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.
>>>>
>>>> [gabe.black] dev,arch-x86: Implement some self test 8042 commands.
>>>>
>>>> [gabe.black] scons: Process the SConsopts files for each variant.
>>>>
>>>> [gabe.black] scons: Turn a lot of compiler flag vars into env vars.
>>>>
>>>> [gabe.black] arch-x86: Fix the SAHF and LAHF instructions.
>>>>
>>>> [gabe.black] arch: Make the DummyVec... types the same size as RegVal.
>>>>
>>>> [gabe.black] ext,scons: Make kconfiglib available for use in SCons.
>>>>
>>>> [gabe.black] scons: Make all sticky variables automatically exported.
>>>>
>>>> [gabe.black] dev: Implement PS/2 keyboard echo and set scan code
>>>> commands.
>>>>
>>>> [gabe.black] arch-x86: Specialize some instructions for virtual 8086
>>>> mode.
>>>>
>>>>
>>>> --
>>>> [...truncated 1.17 MB...]
>>>> [ RUN  ] LoggingFixture.Warn
>>>> [   OK ] LoggingFixture.Warn (0 ms)
>>>> [ RUN  ] LoggingFixture.Inform
>>>> [   OK ] LoggingFixture.Inform (0 ms)
>>>> [ RUN  ] LoggingFixture.Hack
>>>> [   OK ] LoggingFixture.Hack (0 ms)
>>>> [ RUN  ] LoggingFixture.WarnOnce
>>>> [   OK ] LoggingFixture.WarnOnce (0 ms)
>>>> [ RUN  ] LoggingFixture.InformOnce
>>>> [   OK ] LoggingFixture.InformOnce (0 ms)
>>>> [ RUN  ] LoggingFixture.HackOnce
>>>> [   OK ] LoggingFixture.HackOnce (0 ms)
>>>> [ RUN  ] LoggingFixture.WarnIf
>>

[gem5-dev] Re: Build failed in Jenkins: nightly #161

2022-03-15 Thread Jason Lowe-Power via gem5-dev
Looks like the problem is  [gabe.black] arch: Make the DummyVec... types
the same size as RegVal.

Can you take a look, Gabe?

Thanks,
Jason

On Tue, Mar 15, 2022 at 1:46 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/161/display/redirect?page=changes>
>
> Changes:
>
> [gabe.black] arch-x86: Fix a bug in the protected mode IRET.
>
> [gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.
>
> [gabe.black] arch-x86: Detect when entering virtual 8086 mode.
>
> [gabe.black] arch-x86: Tidy up the page table walker stepWalk method.
>
> [gabe.black] arch-x86: Use the right bits in the page table walker.
>
> [gabe.black] arch-x86: Make the flags microops handle reserved bits better.
>
> [matthew.poremba] sim-se: Initialize shared page table base upon clone
>
> [Bobby R. Bruce] util-docker: Adding docker-compose.yaml
>
> [Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests
>
> [Bobby R. Bruce] util: Remove util/cloudbuild
>
> [gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.
>
> [gabe.black] dev,arch-x86: Implement some self test 8042 commands.
>
> [gabe.black] scons: Process the SConsopts files for each variant.
>
> [gabe.black] scons: Turn a lot of compiler flag vars into env vars.
>
> [gabe.black] arch-x86: Fix the SAHF and LAHF instructions.
>
> [gabe.black] arch: Make the DummyVec... types the same size as RegVal.
>
> [gabe.black] ext,scons: Make kconfiglib available for use in SCons.
>
> [gabe.black] scons: Make all sticky variables automatically exported.
>
> [gabe.black] dev: Implement PS/2 keyboard echo and set scan code commands.
>
> [gabe.black] arch-x86: Specialize some instructions for virtual 8086 mode.
>
>
> --
> [...truncated 1.17 MB...]
> [ RUN  ] LoggingFixture.Warn
> [   OK ] LoggingFixture.Warn (0 ms)
> [ RUN  ] LoggingFixture.Inform
> [   OK ] LoggingFixture.Inform (0 ms)
> [ RUN  ] LoggingFixture.Hack
> [   OK ] LoggingFixture.Hack (0 ms)
> [ RUN  ] LoggingFixture.WarnOnce
> [   OK ] LoggingFixture.WarnOnce (0 ms)
> [ RUN  ] LoggingFixture.InformOnce
> [   OK ] LoggingFixture.InformOnce (0 ms)
> [ RUN  ] LoggingFixture.HackOnce
> [   OK ] LoggingFixture.HackOnce (0 ms)
> [ RUN  ] LoggingFixture.WarnIf
> [   OK ] LoggingFixture.WarnIf (0 ms)
> [ RUN  ] LoggingFixture.WarnIfOnce
> [   OK ] LoggingFixture.WarnIfOnce (0 ms)
> [--] 21 tests from LoggingFixture (0 ms total)
>
> [--] Global test environment tear-down
> [==] 34 tests from 2 test suites ran. (1638 ms total)
> [  PASSED  ] 34 tests.
>  [LINK]  -> NULL/arch/generic/vec_pred_reg.test.opt
> build/NULL/arch/generic/vec_reg.test.opt
> --gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_reg.test.xml
> Running main() from build/NULL/ext/googletest/googletest/src/gtest_main.cc
> [==] Running 8 tests from 2 test suites.
> [--] Global test environment set-up.
> [--] 2 tests from VecReg
> [ RUN  ] VecReg.Size
> [   OK ] VecReg.Size (0 ms)
> [ RUN  ] VecReg.Zero
> [   OK ] VecReg.Zero (0 ms)
> [--] 2 tests from VecReg (0 ms total)
>
> [--] 6 tests from TwoDifferentVecRegs
> [ RUN  ] TwoDifferentVecRegs.Assignment
> [   OK ] TwoDifferentVecRegs.Assignment (0 ms)
> [ RUN  ] TwoDifferentVecRegs.Equality
> [   OK ] TwoDifferentVecRegs.Equality (0 ms)
> [ RUN  ] TwoDifferentVecRegs.Inequality
> [   OK ] TwoDifferentVecRegs.Inequality (0 ms)
> [ RUN  ] TwoDifferentVecRegs.Printing
> [   OK ] TwoDifferentVecRegs.Printing (0 ms)
> [ RUN  ] TwoDifferentVecRegs.ParseParam
> [   OK ] TwoDifferentVecRegs.ParseParam (0 ms)
> [ RUN  ] TwoDifferentVecRegs.ShowParam
> [   OK ] TwoDifferentVecRegs.ShowParam (0 ms)
> [--] 6 tests from TwoDifferentVecRegs (0 ms total)
>
> [--] Global test environment tear-down
> [==] 8 tests from 2 test suites ran. (0 ms total)
> [  PASSED  ] 8 tests.
>  [SO Param] m5.objects.SimObject, SimObject -> NULL/params/SimObject.hh
>  [ENUMDECL] m5.objects.StaticInstFlags, StaticInstFlags ->
> NULL/enums/StaticInstFlags.hh
>  [ENUMDECL] m5.objects.FuncUnit, OpClass -> NULL/enums/OpClass.hh
>  [ENUMDECL] m5.objects.SimObject, ByteOrder -> NULL/enums/ByteOrder.hh
> build/NULL/arch/generic/vec_pred_reg.test.opt
> --gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_pred_reg.test.xml
> Running main() from build/NULL/ext/googletest/googletest/src/gtest_main.cc
> [==] Running 14 tests from 3 test suites.
> [--] Global test environment set-up.
> [--] 2 tests from VecPredReg
> [ RUN  ] VecPredReg.reset
> [   OK ] VecPredReg.reset (0 ms)
> [ RUN  ] VecPredReg.set
> [   OK ] VecPredReg.set (0 ms)
> [--] 2 tests from VecPredReg (0 ms total)
>
> [--] 9 tests from TwoDifferentVecPredRegs
> [ RUN  ] TwoDiffere

[gem5-dev] Re: Build failed in Jenkins: nightly #157

2022-03-11 Thread Jason Lowe-Power via gem5-dev
I spent some time looking into this I'm not sure what's going on. I
don't *think* we're running out of memory (at least, dmesg doesn't say we
ran out of memory).

I'm trying to figure out if maybe docker is configured to kill processes
when they use "too much" memory (for some definition of too much), but
having trouble tracking that down.

I'll keep digging...

Jason

On Fri, Mar 11, 2022 at 4:31 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/157/display/redirect?page=changes>
>
> Changes:
>
> [gabe.black] arch-x86: Use the new operand desc classes in the ISA
> description.
>
> [gabe.black] arch: Create a new operand desc type which takes a class as a
> parameter.
>
> [gabe.black] arch-riscv: Use the OperandDesc classes in the ISA
> description.
>
> [gabe.black] arch-arm: Use the new OperandDesc classes in the ISA
> description.
>
>
> --
> [...truncated 1.49 MB...]
> Starting Test Case: build-POWER-opt
> Starting Test Suite:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5out254odcqw -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> LinearGenerator 1 MESITwoLevel gem5.components.memory
> SingleChannelDDR3_2133 512MiB
> Starting Test Suite:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outhken_zl9 -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> LinearGenerator 1 MESITwoLevel gem5.components.memory
> SingleChannelDDR4_2400 512MiB
> Starting Test Suite:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5out5maaqx5u -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> LinearGenerator 1 MESITwoLevel gem5.components.memory
> SingleChannelLPDDR3_1600 512MiB
> Starting Test Suite:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5out09n9ru6k -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> LinearGenerator 1 MESITwoLevel gem5.components.memory SingleChannelHBM
> 512MiB
> Starting Test Suite:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelHBM-512MiB-NULL-x86_64-opt-MESI_Two_Level
>
> Starting Test Case:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelHBM-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Test:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelHBM-512MiB-NULL-x86_64-opt-MESI_Two_Level
> Passed
> Logging call to command:
> /nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d
> /tmp/gem5outkwnarmuf -re --silent-redirect
> /nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
> LinearGenerator 1 MESITwoLevel gem5.components.memory DualChannelDDR3_1600
> 512MiB
> Starting Test Suite:
> test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_T

[gem5-dev] Re: All tests failing: Please don't commit anything!

2022-03-09 Thread Jason Lowe-Power via gem5-dev
Great news everyone! The tests are finally passing again. Thanks for your
patience!

As always see https://jenkins.gem5.org/ for the current testing status.

Cheers,
Jason

On Tue, Mar 8, 2022 at 3:53 PM Jason Lowe-Power  wrote:

> Hi all,
>
> Please, please, please, refrain from committing anything until we are sure
> that the current bugs are squashed! The weekly tests should finish today or
> tonight, so we can open up committing again tomorrow (if they pass).
>
> It is incredibly difficult to track down what's causing failures when new
> changes are introduced while these tests are failing. The maintainers would
> greatly appreciate your patience!
>
> Thanks,
> Jason
>
> On Mon, Mar 7, 2022 at 3:00 PM Bobby Bruce  wrote:
>
>> Pretty sure the compiler tests are fixed, but they are re-running, so
>> let's see.
>>
>> The nighty tests succeeded in the last couple of runs. Either what was
>> pushed before this submission freeze fixed the issue (I don't know exactly
>> how), or the test is flaky in some capacity. I'm letting it run again to
>> see if it triggers anything. It could have also just failed due to some
>> Jenkin's stutter.
>>
>> The weekly tests failed with a docker error, "error waiting for
>> container: EOF". I couldn't reproduce this locally. From some Googling it
>> happens when you overwhelm the docker with too much CPU or memory
>> utilization. I've never seen it happen before with these tests. I'm running
>> again to see if it triggers again (I want to know if this is now something
>> that will consistently fail or some flakiness in our tests).
>>
>> I'll wait until the weekly's finish again to see if we can unfreeze
>> submissions.
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Mon, Mar 7, 2022 at 8:26 AM Jason Lowe-Power via gem5-dev <
>> gem5-dev@gem5.org> wrote:
>> >
>> > Thanks, Giacomo!
>> >
>> > Now we just have to track down the others...
>> >
>> > Jason
>> >
>> > On Mon, Mar 7, 2022 at 2:02 AM Giacomo Travaglini <
>> giacomo.travagl...@arm.com> wrote:
>> >>
>> >> Hi Jason,
>> >>
>> >>
>> >>
>> >> https://gem5-review.googlesource.com/c/public/gem5/+/57349 might fix
>> the compiler-check failure (gcc-version-7)
>> >>
>> >>
>> >>
>> >> Kind Regards
>> >>
>> >>
>> >>
>> >> Giacomo
>> >>
>> >>
>> >>
>> >> From: Jason Lowe-Power via gem5-dev 
>> >> Date: Saturday, 5 March 2022 at 17:27
>> >> To: gem5 Developer List 
>> >> Cc: Jason Lowe-Power 
>> >> Subject: [gem5-dev] All tests failing: Please don't commit anything!
>> >>
>> >> Hi gem5 developers!
>> >>
>> >>
>> >>
>> >> You may or may not have noticed that as of this morning (3/5) all of
>> the tests on our Jenkins server are failing. This includes the nightly
>> tests, weekly tests, and the compiler tests.
>> >>
>> >>
>> >>
>> >> I'd like to ask everyone to refrain from committing anything else to
>> develop until these tests are passing again. It's incredibly difficult to
>> track down the offending commit when the target is moving and new changes
>> may introduce new bugs.
>> >>
>> >>
>> >>
>> >> If you have some time to help track down these issues, we would also
>> greatly appreciate the help! You can find all of the logs from the failing
>> tests on the jenkins server: https://jenkins.gem5.org/. All of the build
>> artifacts are available for download.
>> >>
>> >>
>> >>
>> >> If you find any leads, please let us know! Given that today is a
>> Saturday, it will be Monday at the earliest that we will be able to dive in
>> ourselves.
>> >>
>> >>
>> >>
>> >> Thanks,
>> >>
>> >> Jason
>> >>
>> >> IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
>> contents to any other person, use it for any purpose, or store or copy the
>> information in any medium. Thank you.
>> >
>> > ___
>> > gem5-dev mailing list -- gem5-dev@gem5.org
>> > To unsubscribe send an email to gem5-dev-le...@gem5.org
>> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>
>
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[gem5-dev] Re: All tests failing: Please don't commit anything!

2022-03-08 Thread Jason Lowe-Power via gem5-dev
Hi all,

Please, please, please, refrain from committing anything until we are sure
that the current bugs are squashed! The weekly tests should finish today or
tonight, so we can open up committing again tomorrow (if they pass).

It is incredibly difficult to track down what's causing failures when new
changes are introduced while these tests are failing. The maintainers would
greatly appreciate your patience!

Thanks,
Jason

On Mon, Mar 7, 2022 at 3:00 PM Bobby Bruce  wrote:

> Pretty sure the compiler tests are fixed, but they are re-running, so
> let's see.
>
> The nighty tests succeeded in the last couple of runs. Either what was
> pushed before this submission freeze fixed the issue (I don't know exactly
> how), or the test is flaky in some capacity. I'm letting it run again to
> see if it triggers anything. It could have also just failed due to some
> Jenkin's stutter.
>
> The weekly tests failed with a docker error, "error waiting for container:
> EOF". I couldn't reproduce this locally. From some Googling it happens when
> you overwhelm the docker with too much CPU or memory utilization. I've
> never seen it happen before with these tests. I'm running again to see if
> it triggers again (I want to know if this is now something that will
> consistently fail or some flakiness in our tests).
>
> I'll wait until the weekly's finish again to see if we can unfreeze
> submissions.
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Mon, Mar 7, 2022 at 8:26 AM Jason Lowe-Power via gem5-dev <
> gem5-dev@gem5.org> wrote:
> >
> > Thanks, Giacomo!
> >
> > Now we just have to track down the others...
> >
> > Jason
> >
> > On Mon, Mar 7, 2022 at 2:02 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
> >>
> >> Hi Jason,
> >>
> >>
> >>
> >> https://gem5-review.googlesource.com/c/public/gem5/+/57349 might fix
> the compiler-check failure (gcc-version-7)
> >>
> >>
> >>
> >> Kind Regards
> >>
> >>
> >>
> >> Giacomo
> >>
> >>
> >>
> >> From: Jason Lowe-Power via gem5-dev 
> >> Date: Saturday, 5 March 2022 at 17:27
> >> To: gem5 Developer List 
> >> Cc: Jason Lowe-Power 
> >> Subject: [gem5-dev] All tests failing: Please don't commit anything!
> >>
> >> Hi gem5 developers!
> >>
> >>
> >>
> >> You may or may not have noticed that as of this morning (3/5) all of
> the tests on our Jenkins server are failing. This includes the nightly
> tests, weekly tests, and the compiler tests.
> >>
> >>
> >>
> >> I'd like to ask everyone to refrain from committing anything else to
> develop until these tests are passing again. It's incredibly difficult to
> track down the offending commit when the target is moving and new changes
> may introduce new bugs.
> >>
> >>
> >>
> >> If you have some time to help track down these issues, we would also
> greatly appreciate the help! You can find all of the logs from the failing
> tests on the jenkins server: https://jenkins.gem5.org/. All of the build
> artifacts are available for download.
> >>
> >>
> >>
> >> If you find any leads, please let us know! Given that today is a
> Saturday, it will be Monday at the earliest that we will be able to dive in
> ourselves.
> >>
> >>
> >>
> >> Thanks,
> >>
> >> Jason
> >>
> >> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
> >
> > ___
> > gem5-dev mailing list -- gem5-dev@gem5.org
> > To unsubscribe send an email to gem5-dev-le...@gem5.org
> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
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[gem5-dev] Re: All tests failing: Please don't commit anything!

2022-03-07 Thread Jason Lowe-Power via gem5-dev
Thanks, Giacomo!

Now we just have to track down the others...

Jason

On Mon, Mar 7, 2022 at 2:02 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hi Jason,
>
>
>
> https://gem5-review.googlesource.com/c/public/gem5/+/57349 might fix the
> compiler-check failure (gcc-version-7)
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> *From: *Jason Lowe-Power via gem5-dev 
> *Date: *Saturday, 5 March 2022 at 17:27
> *To: *gem5 Developer List 
> *Cc: *Jason Lowe-Power 
> *Subject: *[gem5-dev] All tests failing: Please don't commit anything!
>
> Hi gem5 developers!
>
>
>
> You may or may not have noticed that as of this morning (3/5) all of the
> tests on our Jenkins server are failing. This includes the nightly tests,
> weekly tests, and the compiler tests.
>
>
>
> *I'd like to ask everyone to refrain from committing anything else to
> develop* until these tests are passing again. It's incredibly difficult
> to track down the offending commit when the target is moving and new
> changes may introduce new bugs.
>
>
>
> If you have some time to help track down these issues, we would also
> greatly appreciate the help! You can find all of the logs from the failing
> tests on the jenkins server: https://jenkins.gem5.org/. All of the build
> artifacts are available for download.
>
>
>
> If you find any leads, please let us know! Given that today is a Saturday,
> it will be Monday at the earliest that we will be able to dive in ourselves.
>
>
>
> Thanks,
>
> Jason
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
___
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[gem5-dev] All tests failing: Please don't commit anything!

2022-03-05 Thread Jason Lowe-Power via gem5-dev
Hi gem5 developers!

You may or may not have noticed that as of this morning (3/5) all of the
tests on our Jenkins server are failing. This includes the nightly tests,
weekly tests, and the compiler tests.

*I'd like to ask everyone to refrain from committing anything else to
develop* until these tests are passing again. It's incredibly difficult to
track down the offending commit when the target is moving and new changes
may introduce new bugs.

If you have some time to help track down these issues, we would also
greatly appreciate the help! You can find all of the logs from the failing
tests on the jenkins server: https://jenkins.gem5.org/. All of the build
artifacts are available for download.

If you find any leads, please let us know! Given that today is a Saturday,
it will be Monday at the earliest that we will be able to dive in ourselves.

Thanks,
Jason
___
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Reset stats in Ruby correctly

2022-03-02 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57269 )


Change subject: mem-ruby: Reset stats in Ruby correctly
..

mem-ruby: Reset stats in Ruby correctly

Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57269
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/mem/ruby/system/RubySystem.cc
1 file changed, 16 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 76d3f25..91c4bc3 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -477,6 +477,7 @@
 for (auto& network : m_networks) {
 network->resetStats();
 }
+ClockedObject::resetStats();
 }

 #ifndef PARTIAL_FUNC_READS

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/57269
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Gerrit-Change-Number: 57269
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Reset stats in Ruby correctly

2022-03-01 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57269 )



Change subject: mem-ruby: Reset stats in Ruby correctly
..

mem-ruby: Reset stats in Ruby correctly

Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/system/RubySystem.cc
1 file changed, 11 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 76d3f25..91c4bc3 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -477,6 +477,7 @@
 for (auto& network : m_networks) {
 network->resetStats();
 }
+ClockedObject::resetStats();
 }

 #ifndef PARTIAL_FUNC_READS

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Gerrit-Change-Number: 57269
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Revert 7018c2b34

2022-02-26 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57109 )


Change subject: mem-ruby: Revert 7018c2b34
..

mem-ruby: Revert 7018c2b34

This reverts commit 7018c2b34e83c592843bd4ad714f93bc6179866d. This
commit needs more work which will take a while. Meanwhile the nightly
tests are broken because of this.

Change-Id: I11d01d50ab3a2d8fd649f1a825911e14815b1ca6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57109
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
1 file changed, 81 insertions(+), 94 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm  
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm

index bcac2c1..2496935 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -61,29 +61,26 @@
 {
   // STATES
   state_declaration(State, desc="Directory states",  
default="Directory_State_U") {

-U, AccessPermission:Backing_Store,  desc="unblocked";
+U, AccessPermission:Backing_Store, desc="unblocked";
+BL, AccessPermission:Busy,  desc="got L3 WB request";
 // BL is Busy because it's possible for the data only to be in the  
network
 // in the WB, L3 has sent it and gone on with its business in possibly  
I

 // state.
-BL, AccessPermission:Busy,  desc="got L3 WB request";
-BL_WM, AccessPermission:Busy,   desc="writing L3 WB to  
memory, waiting for ack";
-BDR_M, AccessPermission:Backing_Store,  desc="DMA read, blocked  
waiting for memory";
-BS_M, AccessPermission:Backing_Store,   desc="blocked waiting for  
memory";
-BM_M, AccessPermission:Backing_Store,   desc="blocked waiting for  
memory";
-B_M, AccessPermission:Backing_Store,desc="blocked waiting for  
memory";
-BP, AccessPermission:Backing_Store, desc="blocked waiting for  
probes, no need for memory";
-BDR_PM, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes and memory";
-BS_PM, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes and Memory";
-BM_PM, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes and Memory";
-B_PM, AccessPermission:Backing_Store,   desc="blocked waiting for  
probes and Memory";
-BDW_P, AccessPermission:Backing_Store,  desc="DMA write, blocked  
waiting for probes, no need for memory";
-BDW_WM, AccessPermission:Backing_Store, desc="DMA write, writing  
to memory, waiting for ack";
-BDR_Pm, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes, already got memory";
-BS_Pm, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes, already got memory";
-BM_Pm, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes, already got memory";
-B_Pm, AccessPermission:Backing_Store,   desc="blocked waiting for  
probes, already got memory";
-B_WM, AccessPermission:Backing_Store,   desc="writing to memory,  
waiting for ack";
-B, AccessPermission:Backing_Store,  desc="sent response,  
Blocked til ack";
+BDR_M, AccessPermission:Backing_Store,  desc="DMA read, blocked  
waiting for memory";
+BS_M, AccessPermission:Backing_Store, desc="blocked  
waiting for memory";
+BM_M, AccessPermission:Backing_Store, desc="blocked  
waiting for memory";
+B_M, AccessPermission:Backing_Store, desc="blocked  
waiting for memory";
+BP, AccessPermission:Backing_Store, desc="blocked  
waiting for probes, no need for memory";
+BDR_PM, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes and memory";
+BS_PM, AccessPermission:Backing_Store,desc="blocked  
waiting for probes and Memory";
+BM_PM, AccessPermission:Backing_Store,desc="blocked  
waiting for probes and Memory";
+B_PM, AccessPermission:Backing_Store,desc="blocked  
waiting for probes and Memory";
+BDW_P, AccessPermission:Backing_Store, desc="DMA write, blocked  
waiting for probes, no need for memory";
+BDR_Pm, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes, already got memory";
+BS_Pm, AccessPermission:B

[gem5-dev] Re: Build failed in Jenkins: nightly #135

2022-02-20 Thread Jason Lowe-Power via gem5-dev
Hey Matt,

It looks like one of the Ruby changes you recently pushed is breaking the
nightly tests. Can you take a look?

Thanks!
Jason

On Sat, Feb 19, 2022 at 2:06 PM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/135/display/redirect?page=changes>
>
> Changes:
>
> [tiago.muck] mem-ruby: Fix handling of stale CleanUnique
>
> [matthew.poremba] mem-ruby: Ensure MOESI_AMD_Base-dir has probe
> destinations
>
> [matthew.poremba] mem-ruby: Remove DirectoryMemory storage in
> MOESI_AMD_BASE-dir
>
> [matthew.poremba] mem-ruby: Add protocol prints to MOESI_AMD_BASE-dma
>
> [matthew.poremba] cpu: Only acquire needed tokens in PTL tester
>
> [matthew.poremba] configs: Allow for no DMAs in Ruby GPU tester
>
> [tiago.muck] cpu: fix issues with ruby's memtest
>
> [mattdsinclair] gpu-compute: Set scratch_base, lds_base for gfx902
>
> [mattdsinclair] gpu-compute: Fix register checking and allocation in dyn
> manager
>
> [gabe.black] ext-testlib: Import MutableSet properly.
>
>
> --
> [...truncated 1.65 MB...]
>  [ CXX] GCN3_X86/debug/VIOBlock.cc -> .o
>  [ CXX] GCN3_X86/debug/VIO9P.cc -> .o
>  [ CXX] GCN3_X86/debug/VIO9PData.cc -> .o
>  [ CXX] GCN3_X86/python/m5/defines.py.cc -> .o
>  [ CXX] GCN3_X86/python/m5/info.py.cc -> .o
>  [   SHCXX] iostream3/zfstream.cc -> .os
>  [   SHCXX] nomali/lib/gpu.cc -> .os
>  [   SHCXX] nomali/lib/gpublock.cc -> .os
>  [   SHCXX] nomali/lib/gpucontrol.cc -> .os
>  [   SHCXX] nomali/lib/jobcontrol.cc -> .os
>  [   SHCXX] nomali/lib/jobslot.cc -> .os
>  [   SHCXX] nomali/lib/mali_midgard.cc -> .os
>  [   SHCXX] nomali/lib/mali_t6xx.cc -> .os
>  [   SHCXX] nomali/lib/mali_t7xx.cc -> .os
>  [   SHCXX] nomali/lib/addrspace.cc -> .os
>  [   SHCXX] nomali/lib/mmu.cc -> .os
>  [   SHCXX] nomali/lib/nomali_api.cc -> .os
>  [   SHCXX] drampower/src/CommandAnalysis.cc -> .os
>  [   SHCXX] drampower/src/MemArchitectureSpec.cc -> .os
>  [   SHCXX] drampower/src/MemCommand.cc -> .os
>  [   SHCXX] drampower/src/MemPowerSpec.cc -> .os
>  [   SHCXX] drampower/src/MemTimingSpec.cc -> .os
>  [   SHCXX] drampower/src/MemoryPowerModel.cc -> .os
>  [   SHCXX] drampower/src/MemorySpecification.cc -> .os
>  [   SHCXX] drampower/src/Parameter.cc -> .os
>  [   SHCXX] drampower/src/Parametrisable.cc -> .os
>  [   SHCXX] drampower/src/libdrampower/LibDRAMPower.cc -> .os
>  [   SHCXX] drampower/src/CAHelpers.cc -> .os
>  [   SHCXX] drampower/src/CmdHandlers.cc -> .os
>  [   SHCXX] drampower/src/MemBankWiseParams.cc -> .os
>  [ CXX] GCN3_X86/base/date.cc -> .o
>  [LINK]  -> GCN3_X86/gem5.opt
> scons: done building targets.
> *** Summary of Warnings ***
> Warning: Deprecated namespaces are not supported by this compiler.
>  Please make sure to check the mailing list for deprecation
>  announcements.
> + wget -qN http://dist.gem5.org/dist/develop/test-progs/square/square
> + mkdir -p tests/testing-results
> + docker run --rm -u 118: --volume
> /nobackup/jenkins/workspace/nightly/tests/..:/nobackup/jenkins/workspace/nightly/tests/..
> -w /nobackup/jenkins/workspace/nightly/tests/..
> gcr.io/gem5-test/gcn-gpu:latest build/GCN3_X86/gem5.opt
> configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c square
> Global frequency set at 1 ticks per second
> build/GCN3_X86/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (5) does not
> divide range [1:75] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (2) does not
> divide range [1:10] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (2) does not
> divide range [1:64] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (1) does
> not divide range [1:1e+06] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (5) does not
> divide range [1:75] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (2) does not
> divide range [1:10] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (2) does not
> divide range [1:64] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (1) does
> not divide range [1:1e+06] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (5) does not
> divide range [1:75] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (2) does not
> divide range [1:10] into equal-sized buckets. Rounding up.
> build/GCN3_X86/base/stats/storage.hh:279: warn: Bucket size (2) does not
> divide range [1:64] into equal-sized buckets. Roundi

[gem5-dev] Re: build configuration overhaul

2022-01-28 Thread Jason Lowe-Power via gem5-dev
Hi Gabe,

Thanks for writing this up. The first part of your document is the best
documentation on the current build system I've seen to date! We should
convert it to markdown and put it up on the website!

Overall, I really like the direction you're going here. I strongly agree
with the problems of the current build system that you enumerate. I also
strongly back the "there is one way to do it" idea from your solution.

I have a couple of small concerns:
1. I believe we should be able to use flat text files for configuring and
not require something as complex as kconfig. The option of kconfig is OK,
but flat text files give us the ability to offer defaults to users.
2. One requirement that wasn't listed is to make the common case easy. We
should allow users to build gem5 just as easily as they do today (i.e.,
with a single simple command).
3. Backwards compatibility is important. There's a huge amount of
documentation written about gem5 all over the internet (e.g., on class
webpages for assignments), and we can't update all of it overnight. Keeping
at least a symlink to build/X86/gem5.opt, etc. will be important for our
many users.

It may be feasible to do this in steps. E.g., we could update the files in
build_opts to *require* all sticky variables and we could make all
variables either sticky or environment variables. Similarly, we could
remove the common build directory. These things would solve some of the
problems you enumerate without breaking compatibility. It's definitely
low-hanging fruit.

Cheers,
Jason



On Wed, Jan 26, 2022 at 6:45 PM Gabe Black via gem5-dev 
wrote:

> Hi folks. I have a design document here:
>
>
> https://docs.google.com/document/d/11KspjOClPzGRqLUgNTfKQPrrkmsqx-2ulC71nZUJ2qA/edit?usp=sharing
>
> which describes my proposal to overhaul how gem5 builds are configured.
> Please take a look and provide feedback.
>
> Important points to note are (optionally but recommended) collapsing the
> global vs. variant separation in the build directory, and using a kconfig
> like system for enabling/disabling/configuring features, individual models,
> mixtures of ISAs, etc. Also setting up a build directory with a new config
> would be a separate step instead of being implied by the build path. All
> the details are in the doc, PTAL.
>
> Gabe
> ___
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[gem5-dev] Re: LupIO: Friendly IO Devices for gem5 (reviews appreciated!)

2021-12-20 Thread Jason Lowe-Power via gem5-dev
Hey Boris,

Absolutely, it should be easy for this to work with POWER, Arm, etc. I
believe that Joel is actually working on Arm support (not sure about
POWER). We chose to only support RISC-V at this release since we haven't
tested others. That said, it should be mostly just SConscript changes to
compile these in when other versions of gem5 are built.

Cheers,
Jason

On Sat, Dec 18, 2021 at 12:24 PM Boris Shingarov via gem5-dev <
gem5-dev@gem5.org> wrote:

> This is very interesting especially in view of what Prof. Wu Feng said in
> this year's OpenPOWER conference about "vertically integrated" teaching:
> https://www.youtube.com/watch?v=nfOzppTBiQE
> His curriculum is also based on gem5 (although for the ISA he uses
> OpenPOWER, not RISC-V).
> I would like to hope that what we are witnessing is the start of a common
> phenomenon which will rapidly grow beyond VT and UC Davis.
>
> I don't imagine there is much RISC-V-specific stuff in this
> relation-chain, so it should be easy to make LupIO work with OpenPOWER too,
> right?
>
> -"Bobby Bruce via gem5-dev"  wrote: -
> To: "gem5 Developer List" 
> From: "Bobby Bruce via gem5-dev" 
> Date: 12/03/2021 09:43PM
> Cc: "Melissa Jost" , llhin...@ucdavis.edu, "Joël
> Porquet-Lupine" , "Bobby Bruce" 
> Subject: [gem5-dev] LupIO: Friendly IO Devices for gem5 (reviews
> appreciated!)
>
> Dear all,
>
> Here at UC Davis two undergraduate students, Melissa Jost and Laura
> Hinman, have been working on incorporating LupIO devices into gem5.
>
> For those unaware, LupIO devices were developed by Prof. Joel
> Porquet-Lupine as a set of open-source I/O devices to be used for teaching.
> They were designed to model a complete set of I/O devices that are neither
> too complex to teach in a classroom setting, or too simple to translate to
> understanding real-world devices. Our collection consists of a real-time
> clock, random number generator, terminal device, block device, system
> controller, timer device, programmable interrupt controller, as well as an
> inter-processor interrupt controller. A more detailed outline of LupIO can
> be found here:
> https://luplab.cs.ucdavis.edu/assets/lupio/wcae21-porquet-lupio-paper.pdf
> . Within gem5, these devices offer the capability to run simulations with a
> complete set of I/O devices that are both easy to understand and manipulate.
>
> Prior to Melissa and Laura's work these devices were only available for
> use with QEMU. They have worked diligently over the past term to
> incorporate these into gem5 for the RISCV ISA. They have incrementally
> added each device into gem5, and into a LupV gem5 Board (LupvBoard) which,
> when using gem5 alongside the correct device drivers in Linux, provides the
> capability of booting a RISC-V Linux system with SMP support.
>
> At present this work exists as a relation-chain in Gerrit:
> https://gem5-review.googlesource.com/c/public/gem5/+/53040. We would
> appreciate feedback on this relation-chain by those interested in this
> work. We hope we can get this chain submitted into the develop branch soon
> so it can be part of the gem5 v21.2 release.
>
> For those interested in setting up and running the LupvBoard, an example
> configuration script has been included at the top of the relation chain:
> https://gem5-review.googlesource.com/c/public/gem5/+/53046.
>
> Kind regards,
> Bobby
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
> ___
> gem5-dev mailing list -- gem5-dev@gem5.org
> To unsubscribe send an email to gem5-dev-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-dev] Re: Commit message guidelines (was: LupIO: Friendly IO Devices for gem5)

2021-12-20 Thread Jason Lowe-Power via gem5-dev
Hey Boris,

Feel free to make a gerrit change request to the CONTRIBUTING.md file. We
can discuss more there.

>From my perspective, it's not a big deal to me what the conjugation of a
change request is. As long as it's clear, I'm ok with whatever. I'm also OK
with putting a preference in the CONTRIBUTING document. However, I think
it's unlikely that this will be strictly enforced, especially because we
don't have bot for it :).

Cheers,
Jason

On Sat, Dec 18, 2021 at 12:24 PM Boris Shingarov via gem5-dev <
gem5-dev@gem5.org> wrote:

> I was reading through this relation-chain and the only thing that looked
> not quite right is the inconsistent commit message style: some of these
> commits have it in indicative mood, sometimes in imperative, sometimes
> plural and sometimes singular.  Frankly this is rather distracting.  I was
> hoping that somewhere on the "Contributing" page the standard what the
> commit message should look like would be spelled out.  For example in the
> Eclipse project we say this on the "Contributing" page: "The first line
> describes the change made. It is written in the imperative mood, and should
> say what happens when the patch is applied. ..."  (
> https://github.com/eclipse-openj9/openj9/blob/master/CONTRIBUTING.md)  To
> my surprise, gem5's "Contributing" page is silent on this matter --
> although (at least on the few first pages of the commit log) all other
> commits but the ones in this relation-chain are consistent.
>
> What is the procedure for PRs to the Contributing Guide?
>
>
> -"Bobby Bruce via gem5-dev"  wrote: -
> To: "gem5 Developer List" 
> From: "Bobby Bruce via gem5-dev" 
> Date: 12/03/2021 09:43PM
> Cc: "Melissa Jost" , llhin...@ucdavis.edu, "Joël
> Porquet-Lupine" , "Bobby Bruce" 
> Subject: [gem5-dev] LupIO: Friendly IO Devices for gem5 (reviews
> appreciated!)
>
> Dear all,
>
> Here at UC Davis two undergraduate students, Melissa Jost and Laura
> Hinman, have been working on incorporating LupIO devices into gem5.
>
> For those unaware, LupIO devices were developed by Prof. Joel
> Porquet-Lupine as a set of open-source I/O devices to be used for teaching.
> They were designed to model a complete set of I/O devices that are neither
> too complex to teach in a classroom setting, or too simple to translate to
> understanding real-world devices. Our collection consists of a real-time
> clock, random number generator, terminal device, block device, system
> controller, timer device, programmable interrupt controller, as well as an
> inter-processor interrupt controller. A more detailed outline of LupIO can
> be found here:
> https://luplab.cs.ucdavis.edu/assets/lupio/wcae21-porquet-lupio-paper.pdf
> . Within gem5, these devices offer the capability to run simulations with a
> complete set of I/O devices that are both easy to understand and manipulate.
>
> Prior to Melissa and Laura's work these devices were only available for
> use with QEMU. They have worked diligently over the past term to
> incorporate these into gem5 for the RISCV ISA. They have incrementally
> added each device into gem5, and into a LupV gem5 Board (LupvBoard) which,
> when using gem5 alongside the correct device drivers in Linux, provides the
> capability of booting a RISC-V Linux system with SMP support.
>
> At present this work exists as a relation-chain in Gerrit:
> https://gem5-review.googlesource.com/c/public/gem5/+/53040. We would
> appreciate feedback on this relation-chain by those interested in this
> work. We hope we can get this chain submitted into the develop branch soon
> so it can be part of the gem5 v21.2 release.
>
> For those interested in setting up and running the LupvBoard, an example
> configuration script has been included at the top of the relation chain:
> https://gem5-review.googlesource.com/c/public/gem5/+/53046.
>
> Kind regards,
> Bobby
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
> ___
> gem5-dev mailing list -- gem5-dev@gem5.org
> To unsubscribe send an email to gem5-dev-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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