[gem5-dev] [S] Change in gem5/gem5[develop]: base: Use the MSB rather than the LSB in AddrRange:removeIntlvBits
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70057?usp=email )
Change subject: base: Use the MSB rather than the LSB in
AddrRange:removeIntlvBits
..
base: Use the MSB rather than the LSB in AddrRange:removeIntlvBits
In many cases, the LSB (as constrained by the masks) of an interleaved
address range falls within the virtual page offset. For typical
workloads, the page offset and the least significant bits have more
entropy than the most significant bits. Consequently, removing a
bit closer to the MSB preserves bits tends to provide a more uniform
utilization of resources.
Change-Id: I361d8130d080a1be23f85de12afef0432efcd11e
Signed-off-by: Nikos Nikoleris
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 11fb1cd..40545ba 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -523,17 +523,17 @@
}
// Get the LSB set from each mask
-int masks_lsb[masks.size()];
+int masks_msb[masks.size()];
for (unsigned int i = 0; i < masks.size(); i++) {
-masks_lsb[i] = ctz64(masks[i]);
+masks_msb[i] = sizeof(Addr) * 8 - clz64(masks[i]) - 1;
}
// we need to sort the list of bits we will discard as we
// discard them one by one starting.
-std::sort(masks_lsb, masks_lsb + masks.size());
+std::sort(masks_msb, masks_msb + masks.size());
for (unsigned int i = 0; i < masks.size(); i++) {
-const int intlv_bit = masks_lsb[i];
+const int intlv_bit = masks_msb[i];
if (intlv_bit > 0) {
// on every iteration we remove one bit from the input
// address, and therefore the lowest invtl_bit has
@@ -562,15 +562,15 @@
}
// Get the LSB set from each mask
-int masks_lsb[masks.size()];
+int masks_msb[masks.size()];
for (unsigned int i = 0; i < masks.size(); i++) {
-masks_lsb[i] = ctz64(masks[i]);
+masks_msb[i] = sizeof(Addr) * CHAR_BIT - clz64(masks[i]) - 1;
}
// Add bits one-by-one from the LSB side.
-std::sort(masks_lsb, masks_lsb + masks.size());
+std::sort(masks_msb, masks_msb + masks.size());
for (unsigned int i = 0; i < masks.size(); i++) {
-const int intlv_bit = masks_lsb[i];
+const int intlv_bit = masks_msb[i];
if (intlv_bit > 0) {
// on every iteration we add one bit from the input
// address, but the lowest invtl_bit in the iteration is
@@ -583,7 +583,7 @@
}
for (unsigned int i = 0; i < masks.size(); i++) {
-const int lsb = ctz64(masks[i]);
+const int lsb = sizeof(Addr) * CHAR_BIT - clz64(masks[i]) - 1;
const Addr intlv_bit = bits(intlvMatch, i);
// Calculate the mask ignoring the LSB
const Addr masked = a & masks[i] & ~(1 << lsb);
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 1e86154..bf7d2f7 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -743,16 +743,17 @@
uint8_t intlv_match = 1;
AddrRange r(start, end, masks, intlv_match);
-Addr input = (1 << 9) | (1 << 8) | 1;
+Addr input = (1 << 10) | (1 << 9) | (1 << 3);
/*
* (1 << 8) and 1 are interleaving bits to be removed.
*/
Addr output = r.removeIntlvBits(input);
/*
- * The bit, formally at position 9, is now at 7.
+ * The bit, previously at position 10, is now at 9 and the bit
+ * previously at position 9, is now at 8 and bit 3 has been discarded.
*/
-EXPECT_EQ((1 << 7), output);
+EXPECT_EQ((1 << 9) | (1 << 8), output);
/*
* Re-adding the interleaving.
@@ -826,7 +827,7 @@
uint8_t intlv_match = 0;
AddrRange r(start, end, masks, intlv_match);
-Addr value = ((1 << 10) | (1 << 9) | (1 << 8) | (1 << 2) | (1 << 1) |
1);
+Addr value = ((1 << 10) | (1 << 9) | (1 << 8) | (1 << 4) | (1 << 1) |
1);
Addr value_interleaving_bits_removed =
((1 << 9) | (1 << 8) | (1 << 7) | (1 << 1) |
1);
--
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Gerrit-Change-Id: I361d8130d080a1be23f85de12afef0432efcd11e
Gerrit-Change-Number: 70057
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Gerrit-Owner: Nikos Nikoleris
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[gem5-dev] [S] Change in gem5/gem5[develop]: python: Ensure that m5.internal.params is available
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67797?usp=email )
Change subject: python: Ensure that m5.internal.params is available
..
python: Ensure that m5.internal.params is available
Add an import to m5.internal.params which became necessary after:
95f9017c2e configs,python: Clean some cruft out of m5.objects.
This import is necessary but also causes problems when scons calls
build_tools/sim_object_param_struct_hh.py to generate
params/SimObject.hh. m5.internal.params itself imports _m5 and _m5 is
unavalailable resulting in an ImportError. This is bening and we can
safely ignore it.
Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67797
Maintainer: Giacomo Travaglini
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M src/python/m5/SimObject.py
M src/python/m5/internal/params.py
2 files changed, 40 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b5dfca9..6caa532 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -445,6 +445,9 @@
return cls.__name__
def getCCClass(cls):
+# Ensure that m5.internal.params is available.
+import m5.internal.params
+
return getattr(m5.internal.params, cls.pybind_class)
# See ParamValue.cxx_predecls for description.
diff --git a/src/python/m5/internal/params.py
b/src/python/m5/internal/params.py
index 8762a69..8225d0b 100644
--- a/src/python/m5/internal/params.py
+++ b/src/python/m5/internal/params.py
@@ -37,8 +37,17 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import inspect
-import _m5
-for name, module in inspect.getmembers(_m5):
-if name.startswith("param_") or name.startswith("enum_"):
-exec("from _m5.%s import *" % name)
+try:
+# Avoid ImportErrors at build time when _m5 is not available
+import _m5
+
+in_gem5 = True
+except ImportError:
+# The import failed, we're being called from the build system
+in_gem5 = False
+
+if in_gem5:
+for name, module in inspect.getmembers(_m5):
+if name.startswith("param_") or name.startswith("enum_"):
+exec("from _m5.%s import *" % name)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Gerrit-Change-Number: 67797
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: python: Ensure that m5.internal.params is available
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67797?usp=email )
Change subject: python: Ensure that m5.internal.params is available
..
python: Ensure that m5.internal.params is available
Add an import to m5.internal.params which became necessary after:
95f9017c2e configs,python: Clean some cruft out of m5.objects.
This import is necessary but also causes problems when scons calls
build_tools/sim_object_param_struct_hh.py to generate
params/SimObject.hh. m5.internal.params itself imports _m5 and _m5 is
unavalailable resulting in an ImportError. This is bening and we can
safely ignore it.
Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Signed-off-by: Nikos Nikoleris
---
M src/python/m5/SimObject.py
M src/python/m5/internal/params.py
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b5dfca9..e3ff0ab 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -445,6 +445,8 @@
return cls.__name__
def getCCClass(cls):
+# Ensure that m5.internal.params is available.
+import m5.internal.params
return getattr(m5.internal.params, cls.pybind_class)
# See ParamValue.cxx_predecls for description.
diff --git a/src/python/m5/internal/params.py
b/src/python/m5/internal/params.py
index 8762a69..8225d0b 100644
--- a/src/python/m5/internal/params.py
+++ b/src/python/m5/internal/params.py
@@ -37,8 +37,17 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import inspect
-import _m5
-for name, module in inspect.getmembers(_m5):
-if name.startswith("param_") or name.startswith("enum_"):
-exec("from _m5.%s import *" % name)
+try:
+# Avoid ImportErrors at build time when _m5 is not available
+import _m5
+
+in_gem5 = True
+except ImportError:
+# The import failed, we're being called from the build system
+in_gem5 = False
+
+if in_gem5:
+for name, module in inspect.getmembers(_m5):
+if name.startswith("param_") or name.startswith("enum_"):
+exec("from _m5.%s import *" % name)
--
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Gerrit-Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Gerrit-Change-Number: 67797
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Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Make the random number generator public
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47859 )
Change subject: base: Make the random number generator public
..
base: Make the random number generator public
There are cases where we need a random number generator engine. The
Random class has such an engine but its interface currently only
allows for generating random numbers. To make sure we can reuse the
same random number generator in as many places as possible this patch
makes the engine in the Random class public.
Change-Id: I80153dd39f5b0d12537e4c0cf54773e7725b2a94
Signed-off-by: Nikos Nikoleris
---
M src/base/random.hh
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/base/random.hh b/src/base/random.hh
index 9a3d696..55d7245 100644
--- a/src/base/random.hh
+++ b/src/base/random.hh
@@ -61,14 +61,15 @@
class Random : public Serializable
{
- private:
-
-std::mt19937_64 gen;
-
public:
/**
* @ingroup api_base_utils
+ */
+std::mt19937_64 gen;
+
+/**
+ * @ingroup api_base_utils
* @{
*/
Random();
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: Substitute calls to functions removed in c++-17
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47799 )
Change subject: cpu-minor: Substitute calls to functions removed in c++-17
..
cpu-minor: Substitute calls to functions removed in c++-17
Change-Id: Ib15234b37e577afd7ff186f1ba7cc5896aea1430
Signed-off-by: Nikos Nikoleris
---
M src/cpu/minor/cpu.hh
M src/cpu/minor/execute.cc
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 57b73b7..929048f 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -44,6 +44,8 @@
#ifndef __CPU_MINOR_CPU_HH__
#define __CPU_MINOR_CPU_HH__
+#include
+
#include "base/compiler.hh"
#include "cpu/minor/activity.hh"
#include "cpu/minor/stats.hh"
@@ -184,7 +186,11 @@
for (ThreadID i = 0; i < numThreads; i++) {
prio_list.push_back(i);
}
-std::random_shuffle(prio_list.begin(), prio_list.end());
+
+std::random_device r;
+std::shuffle(prio_list.begin(), prio_list.end(),
+ std::default_random_engine(r()));
+
return prio_list;
}
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 793ed7e..81850cb 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -37,6 +37,8 @@
#include "cpu/minor/execute.hh"
+#include
+
#include "arch/locked_mem.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/exec_context.hh"
@@ -1685,7 +1687,7 @@
stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0));
std::for_each(funcUnits.begin(), funcUnits.end(),
-std::mem_fun(::minorTrace));
+std::mem_fn(::minorTrace));
executeInfo[0].inFlightInsts->minorTrace();
executeInfo[0].inFUMemInsts->minorTrace();
--
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Gerrit-Change-Number: 47799
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix indexing policies in prefetchers
ddress -Addr sr_addr = pfi.getAddr() / spatialRegionSize; +Addr sr_addr = pfi.getAddr(); Addr paddr = pfi.getPaddr(); // Offset in cachelines within the spatial region -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37597 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia2273cb34705fecce10480881e102ad1764050e0 Gerrit-Change-Number: 37597 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base: Add operator~() in ChannelAddr class
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37595 )
Change subject: base: Add operator~() in ChannelAddr class
..
base: Add operator~() in ChannelAddr class
Change-Id: I3e9c0130d1bd110ad9d42c851a16a9de322e0fb4
Signed-off-by: Nikos Nikoleris
---
M src/base/channel_addr.hh
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 2cfe380..0c2b65b 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -129,6 +129,10 @@
return ChannelAddr(a - b.a);
}
+constexpr ChannelAddr operator~() const {
+return ChannelAddr(~a);
+}
+
constexpr bool operator>(const ChannelAddr ) const { return a > b.a;
}
constexpr bool operator>=(const ChannelAddr ) const { return a >=
b.a; }
constexpr bool operator<(const ChannelAddr ) const { return a < b.a;
}
--
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[gem5-dev] Change in gem5/gem5[develop]: util: Relax commit message checker to allow fixups
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37598 )
Change subject: util: Relax commit message checker to allow fixups
..
util: Relax commit message checker to allow fixups
Change-Id: I094de0a9cb65af0ba0a8700d77cd51c6537d7beb
Signed-off-by: Nikos Nikoleris
---
M util/git-commit-msg.py
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index 9cba896..836bc4d 100755
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -113,10 +113,12 @@
commit_message_lines = commit_message.splitlines()
commit_header = commit_message_lines[0]
commit_header_match = \
-re.search("^(\S[\w\-][,\s*[\w\-]+]*:.+\S$)", commit_header)
+re.search("^(fixup! )?(\S[\w\-][,\s*[\w\-]+]*:.+\S$)", commit_header)
if ((commit_header_match is None)):
_printErrorQuit("Invalid commit header")
-_validateTags(commit_header)
+if commit_header_match.group(1) == "fixup! ":
+sys.exit(0)
+_validateTags(commit_header_match.group(2))
# Make sure commit title does not exceed threshold. This line is limited to
# a smaller number because version control systems may add a prefix,
causing
--
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[gem5-dev] Change in gem5/gem5[develop]: ext: Disable range-loop-analysis warnings for pybind11
Nikos Nikoleris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/35296 ) Change subject: ext: Disable range-loop-analysis warnings for pybind11 .. ext: Disable range-loop-analysis warnings for pybind11 Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115 Signed-off-by: Nikos Nikoleris --- M ext/pybind11/include/pybind11/pybind11.h 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/ext/pybind11/include/pybind11/pybind11.h b/ext/pybind11/include/pybind11/pybind11.h index a9ee31a..04ef30f 100644 --- a/ext/pybind11/include/pybind11/pybind11.h +++ b/ext/pybind11/include/pybind11/pybind11.h @@ -12,6 +12,7 @@ #ifdef __clang__ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wunused-value" +#pragma clang diagnostic warning "-Wrange-loop-analysis" #endif #if defined(__INTEL_COMPILER) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35296 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115 Gerrit-Change-Number: 35296 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: mem: Fix some reference use in range loops
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34776 )
Change subject: mem: Fix some reference use in range loops
..
mem: Fix some reference use in range loops
This change fixes two cases of range loops, one where we can't use
lvalue reference, and one more where we have to use an lvalue
reference as we can't create a copy. In both cases clang would warn.
Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34776
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/common/BoolVec.cc
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/system/Sequencer.cc
3 files changed, 5 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/BoolVec.cc b/src/mem/ruby/common/BoolVec.cc
index 603f714..1c29532 100644
--- a/src/mem/ruby/common/BoolVec.cc
+++ b/src/mem/ruby/common/BoolVec.cc
@@ -41,8 +41,8 @@
#include
std::ostream& operator<<(std::ostream& os, const BoolVec& myvector) {
-for (const auto& it: myvector) {
-os << " " << it;
+for (const bool e: myvector) {
+os << " " << e;
}
return os;
}
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 8ff8884..155d134 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -256,8 +256,8 @@
countBoolVec(BoolVec bVec)
{
int count = 0;
-for (const auto : bVec) {
-if (it) {
+for (const bool e: bVec) {
+if (e) {
count++;
}
}
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 75c58d6..dbc85c4 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -167,7 +167,7 @@
int total_outstanding = 0;
for (const auto _entry : m_RequestTable) {
-for (const auto seq_req : table_entry.second) {
+for (const auto _req : table_entry.second) {
if (current_time - seq_req.issue_time < m_deadlock_threshold)
continue;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Gerrit-Change-Number: 34776
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Bobby R. Bruce
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Fix some reference use in range loops
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34776 )
Change subject: mem: Fix some reference use in range loops
..
mem: Fix some reference use in range loops
This change fixes two cases of range loops, one where we can't use
lvalue reference, and one more where we have to use an lvalue
reference as we can't create a copy. In both cases clang would warn.
Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Signed-off-by: Nikos Nikoleris
---
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/system/Sequencer.cc
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 8ff8884..317bded 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -256,8 +256,8 @@
countBoolVec(BoolVec bVec)
{
int count = 0;
-for (const auto : bVec) {
-if (it) {
+for (const auto &: bVec) {
+if (e) {
count++;
}
}
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 75c58d6..dbc85c4 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -167,7 +167,7 @@
int total_outstanding = 0;
for (const auto _entry : m_RequestTable) {
-for (const auto seq_req : table_entry.second) {
+for (const auto _req : table_entry.second) {
if (current_time - seq_req.issue_time < m_deadlock_threshold)
continue;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Gerrit-Change-Number: 34776
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Avoid the unsupported option -Wno-c99-designator in MacOS
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/33775 ) Change subject: scons: Avoid the unsupported option -Wno-c99-designator in MacOS .. scons: Avoid the unsupported option -Wno-c99-designator in MacOS Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Signed-off-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33775 Reviewed-by: Gabe Black Reviewed-by: Jason Lowe-Power Maintainer: Gabe Black Tested-by: kokoro --- M SConstruct 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/SConstruct b/SConstruct index d229ab8..4e47bda 100755 --- a/SConstruct +++ b/SConstruct @@ -440,7 +440,8 @@ # interchangeably. '-Wno-mismatched-tags', ]) -if compareVersions(clang_version, "10.0") >= 0: +if sys.platform != "darwin" and \ + compareVersions(clang_version, "10.0") >= 0: main.Append(CCFLAGS=['-Wno-c99-designator']) if compareVersions(clang_version, "8.0") >= 0: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33775 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Gerrit-Change-Number: 33775 Gerrit-PatchSet: 2 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Remove unused variable pcbb from ThreadInfo
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33776 )
Change subject: arch: Remove unused variable pcbb from ThreadInfo
..
arch: Remove unused variable pcbb from ThreadInfo
Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33776
Reviewed-by: Gabe Black
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/generic/linux/threadinfo.hh
1 file changed, 2 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/generic/linux/threadinfo.hh
b/src/arch/generic/linux/threadinfo.hh
index 0127105..e5ba7e2 100644
--- a/src/arch/generic/linux/threadinfo.hh
+++ b/src/arch/generic/linux/threadinfo.hh
@@ -39,7 +39,6 @@
private:
ThreadContext *tc;
System *sys;
-Addr pcbb;
ByteOrder byteOrder;
@@ -62,8 +61,8 @@
}
public:
-ThreadInfo(ThreadContext *_tc, Addr _pcbb = 0)
-: tc(_tc), sys(tc->getSystemPtr()), pcbb(_pcbb),
+ThreadInfo(ThreadContext *_tc)
+: tc(_tc), sys(tc->getSystemPtr()),
byteOrder(tc->getSystemPtr()->getGuestByteOrder())
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Gerrit-Change-Number: 33776
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add missing overrides in the *Fault classes
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33777 )
Change subject: sim: Add missing overrides in the *Fault classes
..
sim: Add missing overrides in the *Fault classes
Change-Id: I7a74df78f0f85ccf7fd896f98b301c1f998c1497
Signed-off-by: Nikos Nikoleris
---
M src/sim/faults.hh
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index e9a57c6..4b5c1a5 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -55,7 +55,11 @@
public:
UnimpFault(std::string _str) : panicStr(_str) {}
-FaultName name() const { return "Unimplemented simulator feature"; }
+FaultName
+name() const override
+{
+return "Unimplemented simulator feature";
+}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
};
@@ -63,7 +67,7 @@
class ReExec : public FaultBase
{
public:
-virtual FaultName name() const { return "Re-execution fault"; }
+virtual FaultName name() const override { return "Re-execution fault";
}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
};
@@ -78,7 +82,7 @@
class SyscallRetryFault : public FaultBase
{
public:
-virtual FaultName name() const { return "System call retry fault"; }
+FaultName name() const override { return "System call retry fault"; }
SyscallRetryFault() {}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
@@ -89,7 +93,7 @@
private:
Addr vaddr;
public:
-FaultName name() const { return "Generic page table fault"; }
+FaultName name() const override { return "Generic page table fault"; }
GenericPageTableFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
@@ -101,7 +105,7 @@
private:
Addr vaddr;
public:
-FaultName name() const { return "Generic alignment fault"; }
+FaultName name() const override { return "Generic alignment fault"; }
GenericAlignmentFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr) override;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a74df78f0f85ccf7fd896f98b301c1f998c1497
Gerrit-Change-Number: 33777
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Avoid the unsupported option -Wno-c99-designator in MacOS
Nikos Nikoleris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/33775 ) Change subject: scons: Avoid the unsupported option -Wno-c99-designator in MacOS .. scons: Avoid the unsupported option -Wno-c99-designator in MacOS Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Signed-off-by: Nikos Nikoleris --- M SConstruct 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/SConstruct b/SConstruct index bbfa37a..efd2a9d 100755 --- a/SConstruct +++ b/SConstruct @@ -473,7 +473,8 @@ # interchangeably. '-Wno-mismatched-tags', ]) -if compareVersions(clang_version, "10.0") >= 0: +if sys.platform != "darwin" and \ + compareVersions(clang_version, "10.0") >= 0: main.Append(CCFLAGS=['-Wno-c99-designator']) if compareVersions(clang_version, "8.0") >= 0: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33775 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef Gerrit-Change-Number: 33775 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Remove unused variable pcbb from ThreadInfo
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33776 )
Change subject: arch: Remove unused variable pcbb from ThreadInfo
..
arch: Remove unused variable pcbb from ThreadInfo
Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Signed-off-by: Nikos Nikoleris
---
M src/arch/generic/linux/threadinfo.hh
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/arch/generic/linux/threadinfo.hh
b/src/arch/generic/linux/threadinfo.hh
index 0127105..e5ba7e2 100644
--- a/src/arch/generic/linux/threadinfo.hh
+++ b/src/arch/generic/linux/threadinfo.hh
@@ -39,7 +39,6 @@
private:
ThreadContext *tc;
System *sys;
-Addr pcbb;
ByteOrder byteOrder;
@@ -62,8 +61,8 @@
}
public:
-ThreadInfo(ThreadContext *_tc, Addr _pcbb = 0)
-: tc(_tc), sys(tc->getSystemPtr()), pcbb(_pcbb),
+ThreadInfo(ThreadContext *_tc)
+: tc(_tc), sys(tc->getSystemPtr()),
byteOrder(tc->getSystemPtr()->getGuestByteOrder())
{
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Gerrit-Change-Number: 33776
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Use beats_per_clock as the DDR data rate for DRAMPower
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30056 )
Change subject: mem: Use beats_per_clock as the DDR data rate for DRAMPower
..
mem: Use beats_per_clock as the DDR data rate for DRAMPower
The data rate is used by the drampower lib to estimate the power
consumption of the DRAM Core. Previously, we used the formula:
burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
data_rate = p->burst_length / burst_cycles;
to derive the data_rate. However, under certain configurations this
formula computes the wrong result due to rounding errors. This patch
simplifies the way we derive the data_rate by passing the value of the
DRAM parameter beats_per_clock.
Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Signed-off-by: Nikos Nikoleris
Reviewed-by: Wendy Elsasser
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30056
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M src/mem/drampower.cc
M src/mem/drampower.hh
2 files changed, 1 insertion(+), 17 deletions(-)
Approvals:
Wendy Elsasser: Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/drampower.cc b/src/mem/drampower.cc
index f506928..13551a0 100644
--- a/src/mem/drampower.cc
+++ b/src/mem/drampower.cc
@@ -53,7 +53,7 @@
archSpec.nbrOfBanks = p->banks_per_rank;
// One DRAMPower instance per rank, hence set this to 1
archSpec.nbrOfRanks = 1;
-archSpec.dataRate = getDataRate(p);
+archSpec.dataRate = p->beats_per_clock;
// For now we can ignore the number of columns and rows as they
// are not used in the power calculation.
archSpec.nbrOfColumns = 0;
@@ -146,14 +146,3 @@
{
return p->VDD2 == 0 ? false : true;
}
-
-uint8_t
-DRAMPower::getDataRate(const DRAMCtrlParams* p)
-{
-uint32_t burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
-uint8_t data_rate = p->burst_length / burst_cycles;
-// 4 for GDDR5
-if (data_rate != 1 && data_rate != 2 && data_rate != 4 && data_rate !=
8)
-fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
-return data_rate;
-}
diff --git a/src/mem/drampower.hh b/src/mem/drampower.hh
index ed47476..da24bca 100644
--- a/src/mem/drampower.hh
+++ b/src/mem/drampower.hh
@@ -74,11 +74,6 @@
static Data::MemPowerSpec getPowerParams(const DRAMCtrlParams* p);
/**
- * Determine data rate, either one or two.
- */
-static uint8_t getDataRate(const DRAMCtrlParams* p);
-
-/**
* Determine if DRAM has two voltage domains (or one)
*/
static bool hasTwoVDD(const DRAMCtrlParams* p);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Gerrit-Change-Number: 30056
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Wendy Elsasser
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Fix latency handling in MemDelay
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30055 )
Change subject: mem: Fix latency handling in MemDelay
..
mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.
Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30055
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/mem/mem_delay.cc
1 file changed, 14 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index 83177fd..9adc072 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -87,7 +87,12 @@
bool
MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayResp(pkt);
+// technically the packet only reaches us after the header delay,
+// and typically we also need to deserialise any payload
+const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
parent.slavePort.schedTimingResp(pkt, when);
@@ -136,7 +141,13 @@
bool
MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayReq(pkt);
+// technically the packet only reaches us after the header
+// delay, and typically we also need to deserialise any
+// payload
+Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
parent.masterPort.schedTimingReq(pkt, when);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Gerrit-Change-Number: 30055
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Assignee: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add a header latency parameter to the XBar
/** the width of the xbar in bytes */ const uint32_t width; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30054 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8 Gerrit-Change-Number: 30054 Gerrit-PatchSet: 2 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Make indexing policies range-aware
t;getSet();
-return (tag << tagShift) |
- ((deskew(addr_set, entry->getWay()) & setMask) << setShift);
+const Addr set = deskew(addr_set, entry->getWay()) & setMask;
+return ChannelAddr((tag << tagShift) | (set << setShift));
}
std::vector
-SkewedAssociative::getPossibleEntries(const Addr addr) const
+SkewedAssociative::getPossibleEntries(const ChannelAddr addr) const
{
std::vector entries;
// Parse all ways
for (uint32_t way = 0; way < assoc; ++way) {
// Apply hash to get set, and get way entry in it
-entries.push_back(sets[extractSet(addr, way)][way]);
+entries.push_back(sets[extractSet(Addr(addr), way)][way]);
}
return entries;
diff --git a/src/mem/cache/tags/indexing_policies/skewed_associative.hh
b/src/mem/cache/tags/indexing_policies/skewed_associative.hh
index cff3b3c..e913d56 100644
--- a/src/mem/cache/tags/indexing_policies/skewed_associative.hh
+++ b/src/mem/cache/tags/indexing_policies/skewed_associative.hh
@@ -149,6 +149,8 @@
*/
~SkewedAssociative() {};
+ protected:
+
/**
* Find all possible entries for insertion and replacement of an
address.
* Should be called immediately before ReplacementPolicy's findVictim()
@@ -157,8 +159,8 @@
* @param addr The addr to a find possible entries for.
* @return The possible entries.
*/
-std::vector getPossibleEntries(const Addr addr)
const
-
override;
+std::vector getPossibleEntries(
+const ChannelAddr addr) const override;
/**
* Regenerate an entry's address from its tag and assigned set and way.
@@ -168,8 +170,8 @@
* @param entry The entry.
* @return the entry's address.
*/
-Addr regenerateAddr(const Addr tag, const ReplaceableEntry* entry)
const
-
override;
+ChannelAddr getChannelAddr(
+const Addr tag, const ReplaceableEntry* entry) const override;
};
#endif //__MEM_CACHE_INDEXING_POLICIES_SKEWED_ASSOCIATIVE_HH__
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ibdee97be47f9bd4161d74c5625ab7d5036bad689
Gerrit-Change-Number: 30095
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add support for blocking the cache on fills
e_tick); return blk; } diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 3efc7c7..1f02c86 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -105,6 +105,7 @@ Blocked_NoMSHRs = MSHRQueue_MSHRs, Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, Blocked_NoTargets, +Blocked_DataArray, NUM_BLOCKED_CAUSES }; @@ -857,7 +858,13 @@ */ const Cycles forwardLatency; -/** The latency to fill a cache block */ +const bool blockOnFills; + +/** + * The latency of filling the data array. It occurs when there is + * a fill to the cache and renders the data array in accessible + * until it is completed. + */ const Cycles fillLatency; /** @@ -916,6 +923,8 @@ * Normally this is all possible memory addresses. */ const AddrRangeList addrRanges; +EventFunctionWrapper dataArrayUnblockEvent; + public: /** System we are currently operating in. */ System *system; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30096 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0b15139cf457e4c34d4f11a6b95ca4f6bd64e4ce Gerrit-Change-Number: 30096 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add support for blocking on reads
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30097 )
Change subject: mem-cache: Add support for blocking on reads
..
mem-cache: Add support for blocking on reads
Change-Id: I1aab914956640e38e72df0da392cfaa9f95be0d6
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/base.hh
3 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index a55ed2a..14668ea 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -79,6 +79,10 @@
tag_latency = Param.Cycles("Tag lookup latency")
data_latency = Param.Cycles("Data access latency")
+block_on_reads = Param.Bool(False, "Block the cache for further "
+"read/writes until read completes")
+data_read_latency = Param.Cycles(Self.data_latency,
+ "Data array read latency")
block_on_fills = Param.Bool(False, "Block the cache for further "
"read/writes until fill completes")
fill_latency = Param.Cycles(Self.data_latency, "Fill latency")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 6614d16..5a0075c 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -92,6 +92,8 @@
lookupLatency(p->tag_latency),
dataLatency(p->data_latency),
forwardLatency(p->tag_latency),
+ blockOnReads(p->block_on_reads),
+ dataArrayReadLatency(p->data_read_latency),
blockOnFills(p->block_on_fills),
fillLatency(p->fill_latency),
responseLatency(p->response_latency),
@@ -219,6 +221,10 @@
assert(pkt->payloadDelay == 0);
pkt->makeTimingResponse();
+if (blockOnReads && pkt->isRead()) {
+setBlocked(Blocked_DataArray);
+schedule(dataArrayUnblockEvent,
clockEdge(dataArrayReadLatency));
+}
// In this case we are considering request_time that takes
// into account the delay of the xbar, if any, and just
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 1f02c86..6d9b602 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -858,6 +858,9 @@
*/
const Cycles forwardLatency;
+const bool blockOnReads;
+const Cycles dataArrayReadLatency;
+
const bool blockOnFills;
/**
--
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix ChannelAddr<->Addr conversation
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30094 )
Change subject: base: Fix ChannelAddr<->Addr conversation
..
base: Fix ChannelAddr<->Addr conversation
Previously calculating a ChannelAddr from an Addr and converting back
ignored that the start of the address range can be different than
0. After this change, ChannelAddr is always an address in the
continuous range [0, MaxChannelAddr).
Change-Id: Icd8b611c43da7f8ff102c1872b175be59ece7ae9
Signed-off-by: Nikos Nikoleris
---
M src/base/channel_addr.hh
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 06fae72..56812c7 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -63,14 +63,14 @@
constexpr ChannelAddr() : a(0) { }
ChannelAddr(const AddrRange , Addr _a)
-: a(range.removeIntlvBits(_a)) {}
+: a(range.removeIntlvBits(_a) - range.start()) {}
ChannelAddr(const ChannelAddr &) = default;
ChannelAddr =(const ChannelAddr &) = default;
Addr getPA(const AddrRange ) const {
-return range.addIntlvBits(a);
+return range.addIntlvBits(a) + range.start();
}
constexpr ChannelAddr operator|(const Type b) const {
--
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add a header latency parameter to the XBar
esource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8 Gerrit-Change-Number: 30054 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: Fix latency handling in MemDelay
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30055 )
Change subject: mem: Fix latency handling in MemDelay
..
mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.
Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris
---
M src/mem/mem_delay.cc
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index 83177fd..52c1ca8 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -87,7 +87,13 @@
bool
MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayResp(pkt);
+// technically the packet only reaches us after the header delay,
+// and typically we also need to deserialise any payload (unless
+// the two sides of the bridge are synchronous)
+const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
parent.slavePort.schedTimingResp(pkt, when);
@@ -136,7 +142,14 @@
bool
MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
{
-const Tick when = curTick() + parent.delayReq(pkt);
+// technically the packet only reaches us after the header
+// delay, and typically we also need to deserialise any
+// payload (unless the two sides of the bridge are
+// synchronous)
+Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
parent.masterPort.schedTimingReq(pkt, when);
--
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[gem5-dev] Change in gem5/gem5[develop]: mem: Use beats_per_clock as the DDR data rate for DRAMPower
Hello Wendy Elsasser,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30056
to review the following change.
Change subject: mem: Use beats_per_clock as the DDR data rate for DRAMPower
..
mem: Use beats_per_clock as the DDR data rate for DRAMPower
The data rate is used by the drampower lib to estimate the power
consumption of the DRAM Core. Previously, we used the formula:
burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
data_rate = p->burst_length / burst_cycles;
to derive the date_rate. However, under certain configurations this
formula computes the wrong result due to rounding errors. This patch
simplifies the way we derive the date_rate by passing the value of the
DRAM parameter beats_per_clock.
Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Signed-off-by: Nikos Nikoleris
Reviewed-by: Wendy Elsasser
---
M src/mem/drampower.cc
M src/mem/drampower.hh
2 files changed, 1 insertion(+), 17 deletions(-)
diff --git a/src/mem/drampower.cc b/src/mem/drampower.cc
index f506928..13551a0 100644
--- a/src/mem/drampower.cc
+++ b/src/mem/drampower.cc
@@ -53,7 +53,7 @@
archSpec.nbrOfBanks = p->banks_per_rank;
// One DRAMPower instance per rank, hence set this to 1
archSpec.nbrOfRanks = 1;
-archSpec.dataRate = getDataRate(p);
+archSpec.dataRate = p->beats_per_clock;
// For now we can ignore the number of columns and rows as they
// are not used in the power calculation.
archSpec.nbrOfColumns = 0;
@@ -146,14 +146,3 @@
{
return p->VDD2 == 0 ? false : true;
}
-
-uint8_t
-DRAMPower::getDataRate(const DRAMCtrlParams* p)
-{
-uint32_t burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
-uint8_t data_rate = p->burst_length / burst_cycles;
-// 4 for GDDR5
-if (data_rate != 1 && data_rate != 2 && data_rate != 4 && data_rate !=
8)
-fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
-return data_rate;
-}
diff --git a/src/mem/drampower.hh b/src/mem/drampower.hh
index ed47476..da24bca 100644
--- a/src/mem/drampower.hh
+++ b/src/mem/drampower.hh
@@ -74,11 +74,6 @@
static Data::MemPowerSpec getPowerParams(const DRAMCtrlParams* p);
/**
- * Determine data rate, either one or two.
- */
-static uint8_t getDataRate(const DRAMCtrlParams* p);
-
-/**
* Determine if DRAM has two voltage domains (or one)
*/
static bool hasTwoVDD(const DRAMCtrlParams* p);
--
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Gerrit-Reviewer: Wendy Elsasser
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[gem5-dev] Change in gem5/gem5[develop]: scons: Build the marshal binary in a bare minimum environment
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28428 )
Change subject: scons: Build the marshal binary in a bare minimum
environment
..
scons: Build the marshal binary in a bare minimum environment
This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.
Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28428
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
M src/SConscript
2 files changed, 10 insertions(+), 7 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 3345148..ba4affa 100755
--- a/SConstruct
+++ b/SConstruct
@@ -709,6 +709,10 @@
if not conf.CheckLib(lib):
error("Can't find library %s required by python." % lib)
+main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
+# Bare minimum environment that only includes python
+base_py_env = main.Clone()
+
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
if not conf.CheckLibWithHeader('socket', 'sys/socket.h',
@@ -1100,8 +1104,6 @@
gdb_xml_dir = joinpath(ext_dir, 'gdb-xml')
Export('gdb_xml_dir')
-main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
-
###
#
# This builder and wrapper method are used to set up a directory with
@@ -1259,7 +1261,8 @@
# The src/SConscript file sets up the build rules in 'env' according
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir = variant_path, exports
= 'env')
+SConscript('src/SConscript', variant_dir=variant_path,
+ exports=['env', 'base_py_env'])
# base help text
Help('''
diff --git a/src/SConscript b/src/SConscript
index c7251fc..134e2a5 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018, 2020 ARM Limited
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
@@ -1140,7 +1140,7 @@
# Build a small helper that marshals the Python code using the same
# version of Python as gem5. This is in an unorthodox location to
# avoid building it for every variant.
-py_marshal = env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
@@ -1196,8 +1196,8 @@
code.write(str(target[0]))
for source in PySource.all:
-env.Command(source.cpp, [ py_marshal, source.tnode ],
-MakeAction(embedPyFile, Transform("EMBED PY")))
+base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
+MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Gerrit-Change-Number: 28428
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Build the marshal binary in a bare minimum environment
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28428 )
Change subject: scons: Build the marshal binary in a bare minimum
environment
..
scons: Build the marshal binary in a bare minimum environment
This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.
Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris
---
M SConstruct
M src/SConscript
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/SConstruct b/SConstruct
index 3345148..ba4affa 100755
--- a/SConstruct
+++ b/SConstruct
@@ -709,6 +709,10 @@
if not conf.CheckLib(lib):
error("Can't find library %s required by python." % lib)
+main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
+# Bare minimum environment that only includes python
+base_py_env = main.Clone()
+
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
if not conf.CheckLibWithHeader('socket', 'sys/socket.h',
@@ -1100,8 +1104,6 @@
gdb_xml_dir = joinpath(ext_dir, 'gdb-xml')
Export('gdb_xml_dir')
-main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
-
###
#
# This builder and wrapper method are used to set up a directory with
@@ -1259,7 +1261,8 @@
# The src/SConscript file sets up the build rules in 'env' according
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir = variant_path, exports
= 'env')
+SConscript('src/SConscript', variant_dir=variant_path,
+ exports=['env', 'base_py_env'])
# base help text
Help('''
diff --git a/src/SConscript b/src/SConscript
index c7251fc..134e2a5 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018, 2020 ARM Limited
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
@@ -1140,7 +1140,7 @@
# Build a small helper that marshals the Python code using the same
# version of Python as gem5. This is in an unorthodox location to
# avoid building it for every variant.
-py_marshal = env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
@@ -1196,8 +1196,8 @@
code.write(str(target[0]))
for source in PySource.all:
-env.Command(source.cpp, [ py_marshal, source.tnode ],
-MakeAction(embedPyFile, Transform("EMBED PY")))
+base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
+MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, mem-ruby, sim: Add missing overrides
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28168 )
Change subject: arch-arm, mem-ruby, sim: Add missing overrides
..
arch-arm, mem-ruby, sim: Add missing overrides
Change-Id: I5ab18960bd61953e6846426adb657818f825
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28168
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/arm/isa.hh
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.hh
M src/sim/kernel_workload.hh
4 files changed, 15 insertions(+), 15 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 5fec2db..b4fbbbf 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -726,14 +726,14 @@
unsigned eCount);
void
-serialize(CheckpointOut ) const
+serialize(CheckpointOut ) const override
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
}
void
-unserialize(CheckpointIn )
+unserialize(CheckpointIn ) override
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 620b5ee..1321173 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -102,9 +102,9 @@
void wakeup(); // Used only for deadlock detection
void printProgress(std::ostream& out) const;
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address, DataBlock& data);
@@ -157,18 +157,18 @@
void recordCPWriteCallBack(MachineID myMachID, MachineID senderMachID);
// Alternate implementations in VIPER Coalescer
-virtual RequestStatus makeRequest(PacketPtr pkt);
+virtual RequestStatus makeRequest(PacketPtr pkt) override;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
bool
-isDeadlockEventScheduled() const
+isDeadlockEventScheduled() const override
{
return deadlockCheckEvent.scheduled();
}
void
-descheduleDeadlockEvent()
+descheduleDeadlockEvent() override
{
deschedule(deadlockCheckEvent);
}
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 0569478..bb2819b 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -86,9 +86,9 @@
// Public Methods
void wakeup(); // Used only for deadlock detection
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address,
DataBlock& data,
@@ -106,14 +106,14 @@
const Cycles forwardRequestTime = Cycles(0),
const Cycles firstResponseTime = Cycles(0));
-RequestStatus makeRequest(PacketPtr pkt);
+RequestStatus makeRequest(PacketPtr pkt) override;
bool empty() const;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
-bool isDeadlockEventScheduled() const
+bool isDeadlockEventScheduled() const override
{ return deadlockCheckEvent.scheduled(); }
-void descheduleDeadlockEvent()
+void descheduleDeadlockEvent() override
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index 972a539..b88051a 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -98,7 +98,7 @@
}
bool
-insertSymbol(Addr address, const std::string )
+insertSymbol(Addr address, const std::string ) override
{
return kernelSymtab->insert(address, symbol);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ab18960bd61953e6846426adb657818f825
Gerrit-Change-Number: 28168
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerr
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed the unused parameter m_id from VirtualChannel
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28171 )
Change subject: mem-ruby: Removed the unused parameter m_id from
VirtualChannel
..
mem-ruby: Removed the unused parameter m_id from VirtualChannel
Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28171
Reviewed-by: Jason Lowe-Power
Reviewed-by: Srikant Bharadwaj
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/network/garnet2.0/InputUnit.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.hh
3 files changed, 4 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Srikant Bharadwaj: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/garnet2.0/InputUnit.cc
b/src/mem/ruby/network/garnet2.0/InputUnit.cc
index 8fdce06..640e3b4 100644
--- a/src/mem/ruby/network/garnet2.0/InputUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/InputUnit.cc
@@ -52,7 +52,7 @@
// Instantiating the virtual channels
virtualChannels.reserve(m_num_vcs);
for (int i=0; i < m_num_vcs; i++) {
-virtualChannels.emplace_back(i);
+virtualChannels.emplace_back();
}
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
index 3b077d4..a469a84 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
@@ -31,8 +31,8 @@
#include "mem/ruby/network/garnet2.0/VirtualChannel.hh"
-VirtualChannel::VirtualChannel(int id)
- : m_id(id), inputBuffer(), m_vc_state(IDLE_, Cycles(0)),
m_output_port(-1),
+VirtualChannel::VirtualChannel()
+ : inputBuffer(), m_vc_state(IDLE_, Cycles(0)), m_output_port(-1),
m_enqueue_time(INFINITE_), m_output_vc(-1)
{
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
index 52963c8..752dfb4 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
@@ -40,7 +40,7 @@
class VirtualChannel
{
public:
-VirtualChannel(int id);
+VirtualChannel();
~VirtualChannel() = default;
bool need_stage(flit_stage stage, Cycles time);
@@ -89,7 +89,6 @@
uint32_t functionalWrite(Packet *pkt);
private:
-int m_id;
flitBuffer inputBuffer;
std::pair m_vc_state;
int m_output_port;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Gerrit-Change-Number: 28171
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Srikant Bharadwaj
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Avoid const from member due to ::operator=(...)
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28249 )
Change subject: mem-ruby: Avoid const from member due to
::operator=(...)
..
mem-ruby: Avoid const from member due to ::operator=(...)
Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28249
Reviewed-by: Matthew Poremba
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/Message.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/Message.hh
b/src/mem/ruby/slicc_interface/Message.hh
index 0c2e0aa..1044fe0 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -104,7 +104,7 @@
void setVnet(int net) { vnet = net; }
private:
-const Tick m_time;
+Tick m_time;
Tick m_LastEnqueueTime; // my last enqueue time
Tick m_DelayedTicks; // my delayed cycles
uint64_t m_msg_counter; // FIXME, should this be a 64-bit value?
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Gerrit-Change-Number: 28249
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix inconsistency in variable name
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28172 ) Change subject: arch-arm: Fix inconsistency in variable name .. arch-arm: Fix inconsistency in variable name Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28172 Maintainer: Giacomo Travaglini Tested-by: kokoro --- M src/arch/arm/freebsd/process.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/freebsd/process.cc b/src/arch/arm/freebsd/process.cc index 3955f85..d8a7d68 100644 --- a/src/arch/arm/freebsd/process.cc +++ b/src/arch/arm/freebsd/process.cc @@ -118,7 +118,7 @@ void *holdp = (void *)buf2.bufferPtr(); size_t *holdlenp = (size_t *)buf3.bufferPtr(); -ret = sysctl((int *)hnamep, namelen, holdp, holdlenp, hnewp, newlen); +ret = sysctl((int *)hnamep, nameLen, holdp, holdlenp, hnewp, newlen); buf.copyOut(tc->getVirtProxy()); buf2.copyOut(tc->getVirtProxy()); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28172 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Gerrit-Change-Number: 28172 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Downgrade constexpr causing build errors to const
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28167 )
Change subject: arch-arm: Downgrade constexpr causing build errors to const
..
arch-arm: Downgrade constexpr causing build errors to const
Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28167
Tested-by: kokoro
---
M src/arch/arm/aapcs32.hh
1 file changed, 7 insertions(+), 7 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index fd63483..e2e5d09 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -489,12 +489,12 @@
if (state.variadic)
return getArgument(tc, state);
-int index = state.allocate(Float{}, 1);
+const int index = state.allocate(Float{}, 1);
if (index >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Float);
-constexpr int reg = index / lane_per_reg;
-constexpr int lane = index % lane_per_reg;
+const int reg = index / lane_per_reg;
+const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
@@ -558,14 +558,14 @@
if (useBaseABI(state))
return getArgument(tc, state);
-int base = state.allocate(Elem{}, Count);
+const int base = state.allocate(Elem{}, Count);
if (base >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Elem);
HA ha;
for (int i = 0; i < Count; i++) {
-constexpr int index = base + i;
-constexpr int reg = index / lane_per_reg;
-constexpr int lane = index % lane_per_reg;
+const int index = base + i;
+const int reg = index / lane_per_reg;
+const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
--
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Gerrit-Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Gerrit-Change-Number: 28167
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Disable unsupported -Wl,--as-needed in MacOS
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28173 )
Change subject: scons: Disable unsupported -Wl,--as-needed in MacOS
..
scons: Disable unsupported -Wl,--as-needed in MacOS
Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28173
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 4 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 215c0b6..3345148 100755
--- a/SConstruct
+++ b/SConstruct
@@ -359,7 +359,10 @@
main.Append(CCFLAGS=['-I/usr/local/include'])
main.Append(CXXFLAGS=['-I/usr/local/include'])
-main.Append(LINKFLAGS='-Wl,--as-needed')
+# On Mac OS X/Darwin the default linker doesn't support the
+# option --as-needed
+if sys.platform != "darwin":
+main.Append(LINKFLAGS='-Wl,--as-needed')
main['FILTER_PSHLINKFLAGS'] = lambda x: str(x).replace(' -shared', '')
main['PSHLINKFLAGS'] =
main.subst('${FILTER_PSHLINKFLAGS(SHLINKFLAGS)}')
if GetOption('gold_linker'):
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Gerrit-Change-Number: 28173
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix access modifier in Arm*ProcessBits class
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28248 )
Change subject: arch-arm: Fix access modifier in Arm*ProcessBits class
..
arch-arm: Fix access modifier in Arm*ProcessBits class
Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Reviewed-by: Giacomo Travaglini
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28248
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/arm/freebsd/process.hh
M src/arch/arm/linux/process.hh
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/freebsd/process.hh
b/src/arch/arm/freebsd/process.hh
index ac0092e..d52512a 100644
--- a/src/arch/arm/freebsd/process.hh
+++ b/src/arch/arm/freebsd/process.hh
@@ -39,7 +39,7 @@
class ArmFreebsdProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
index 0662d9f..0c15c28 100644
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -1,5 +1,5 @@
/*
-* Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,7 +47,7 @@
class ArmLinuxProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
--
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Gerrit-Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Gerrit-Change-Number: 28248
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix function signature inconsistencies in semihosting
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28170 )
Change subject: arch-arm: Fix function signature inconsistencies in
semihosting
..
arch-arm: Fix function signature inconsistencies in semihosting
Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28170
Reviewed-by: Gabe Black
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/semihosting.cc
1 file changed, 6 insertions(+), 6 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 7718cd0..7711a86 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -305,7 +305,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callClose(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callClose(ThreadContext *tc, Handle handle)
{
if (handle > files.size()) {
DPRINTF(Semihosting, "Semihosting SYS_CLOSE(%i): Illegal file\n");
@@ -350,7 +350,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callWrite(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callWrite(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -371,7 +371,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callRead(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callRead(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -404,7 +404,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callIsTTY(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callIsTTY(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -418,7 +418,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callSeek(ThreadContext *tc, uint64_t handle, uint64_t pos)
+ArmSemihosting::callSeek(ThreadContext *tc, Handle handle, uint64_t pos)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -432,7 +432,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callFLen(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callFLen(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
--
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Gerrit-Change-Number: 28170
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix mismatch between #ifndef and #define in varargs.hh
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28169 ) Change subject: sim: Fix mismatch between #ifndef and #define in varargs.hh .. sim: Fix mismatch between #ifndef and #define in varargs.hh Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28169 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M src/sim/guest_abi/varargs.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh index 41e3c62..6a19db8 100644 --- a/src/sim/guest_abi/varargs.hh +++ b/src/sim/guest_abi/varargs.hh @@ -26,7 +26,7 @@ */ #ifndef __SIM_GUEST_ABI_VARARGS_HH__ -#define __SIM_GUEST_ABI_VARRAGS_HH__ +#define __SIM_GUEST_ABI_VARARGS_HH__ #include #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28169 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Gerrit-Change-Number: 28169 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Inheritance fixes in varargs
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28250 )
Change subject: sim: Inheritance fixes in varargs
..
sim: Inheritance fixes in varargs
Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28250
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/guest_abi/varargs.hh
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh
index 6a19db8..07ed2a1 100644
--- a/src/sim/guest_abi/varargs.hh
+++ b/src/sim/guest_abi/varargs.hh
@@ -70,6 +70,8 @@
class VarArgsBase : public VarArgsBase
{
public:
+virtual ~VarArgsBase() = default;
+
// The virtual function takes a reference parameter so that the
different
// _getImpl methods can co-exist through overloading.
virtual void _getImpl(First &) = 0;
@@ -126,6 +128,8 @@
// Declare state to pass to the Argument<>::get methods.
ThreadContext *tc;
typename ABI::State state;
+// Make sure base class _getImpl-es don't get hidden by ours.
+using Base::_getImpl;
// Give the "using" statement in our subclass something to refer to.
void _getImpl();
--
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Gerrit-Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Gerrit-Change-Number: 28250
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Creation of PowerState class
TIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * PowerState declaration and implementation.
+ */
+
+#ifndef __SIM_POWER_STATE_HH__
+#define __SIM_POWER_STATE_HH__
+
+#include
+
+#include "base/callback.hh"
+#include "base/statistics.hh"
+#include "enums/PwrState.hh"
+#include "params/PowerState.hh"
+#include "sim/core.hh"
+#include "sim/sim_object.hh"
+
+/**
+ * Helper class for objects that have power states. This class provides the
+ * basic functionality to change between power states.
+ */
+class PowerState : public SimObject
+{
+ public:
+PowerState(const PowerStateParams *p);
+
+/** Parameters of PowerState object */
+typedef PowerStateParams Params;
+const Params* params() const
+{
+return reinterpret_cast(_params);
+}
+
+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;
+
+/**
+ * Change the power state of this object to the power state p
+ */
+void set(Enums::PwrState p);
+
+
+inline Enums::PwrState get() const
+{
+return _currState;
+}
+
+inline std::string getName() const
+{
+return Enums::PwrStateStrings[_currState];
+}
+
+/** Returns the percentage residency for each power state */
+std::vector getWeights() const;
+
+/**
+ * Record stats values like state residency by computing the time
+ * difference from previous update. Also, updates the previous
evaluation
+ * tick once all stats are recorded.
+ * Usually called on power state change and stats dump callback.
+ */
+void computeStats();
+
+ protected:
+
+/** To keep track of the current power state */
+Enums::PwrState _currState;
+
+/** Last tick the power stats were calculated */
+Tick prvEvalTick = 0;
+
+struct PowerStateStats : public Stats::Group
+{
+PowerStateStats(PowerState );
+
+void regStats() override;
+void preDumpStats() override;
+
+PowerState
+
+Stats::Scalar numTransitions;
+Stats::Distribution ticksClkGated;
+/** Tracks the time spent in each of the power states */
+Stats::Vector pwrStateResidencyTicks;
+} stats;
+};
+
+class PowerStateDumpCallback : public Callback
+{
+ PowerState *co;
+ public:
+PowerStateDumpCallback(PowerState *co_t) : co(co_t) {}
+virtual void process() { co->computeStats(); };
+};
+
+#endif //__SIM_POWER_STATE_HH__
--
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Gerrit-Change-Number: 28049
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-Reviewer: Bobby R. Bruce
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Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: configs: Change fs_power.py to use absolute paths for stats
ject: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c Gerrit-Change-Number: 27893 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim-power: Addition of PowerDomains
at this power state leads, nullptr if it
+ * doesn't lead any.
+ */
+PowerDomain* controlledDomain = nullptr;
+
struct PowerStateStats : public Stats::Group
{
PowerStateStats(PowerState );
@@ -127,6 +144,7 @@
PowerState
Stats::Scalar numTransitions;
+Stats::Scalar numPwrMatchStateTransitions;
Stats::Distribution ticksClkGated;
/** Tracks the time spent in each of the power states */
Stats::Vector pwrStateResidencyTicks;
--
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Gerrit-Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff
Gerrit-Change-Number: 28051
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Specify the states a PowerState object can be in
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28050 )
Change subject: sim-power: Specify the states a PowerState object can be in
..
sim-power: Specify the states a PowerState object can be in
This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.
Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28050
Reviewed-by: Bobby R. Bruce
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/BaseCPU.py
M src/sim/PowerState.py
M src/sim/power_state.cc
M src/sim/power_state.hh
4 files changed, 28 insertions(+), 1 deletion(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 67d95d0..ab70d1d 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -303,3 +303,7 @@
cpus_node.append(node)
yield cpus_node
+
+def __init__(self, **kwargs):
+super(BaseCPU, self).__init__(**kwargs)
+self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py
index 59491ec..bfa53e2 100644
--- a/src/sim/PowerState.py
+++ b/src/sim/PowerState.py
@@ -62,6 +62,11 @@
# routine
default_state = Param.PwrState("UNDEFINED", "Default Power State")
+# Possible power states this object can be in sorted from the most
+# to the least performant
+possible_states = VectorParam.PwrState(
+[], "Power states this object can be in")
+
clk_gate_min = Param.Latency('1ns',"Min value of the distribution")
clk_gate_max = Param.Latency('1s',"Max value of the distribution")
clk_gate_bins = Param.Unsigned('20', "# bins in clk gated
distribution")
diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index 28b0b83..a2ed7fe 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -41,7 +41,9 @@
PowerState::PowerState(const PowerStateParams *p) :
SimObject(p), _currState(p->default_state),
-stats(*this)
+possibleStates(p->possible_states.begin(),
+ p->possible_states.end()),
+prvEvalTick(0), stats(*this)
{
}
@@ -68,6 +70,11 @@
void
PowerState::set(Enums::PwrState p)
{
+// Check if this power state is actually allowed by checking whether
it is
+// present in pwrStateToIndex-dictionary
+panic_if(possibleStates.find(p) == possibleStates.end(),
+ "Cannot go to %s in %s \n", Enums::PwrStateStrings[p],
name());
+
// Function should ideally be called only when there is a state change
if (_currState == p) {
warn_once("PowerState: Already in the requested power state, "
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index 8b93b45..4565c2b 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -98,11 +98,22 @@
*/
void computeStats();
+/**
+ * Return the power states this object can be in
+ */
+std::set getPossibleStates() const
+{
+return possibleStates;
+}
+
protected:
/** To keep track of the current power state */
Enums::PwrState _currState;
+/** The possible power states this object can be in */
+const std::set possibleStates;
+
/** Last tick the power stats were calculated */
Tick prvEvalTick = 0;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Gerrit-Change-Number: 28050
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Fix the way the power model accesses stats
if (si) return si->value(); diff --git a/src/sim/power/mathexpr_powermodel.hh b/src/sim/power/mathexpr_powermodel.hh index d8bd239..1edb800 100644 --- a/src/sim/power/mathexpr_powermodel.hh +++ b/src/sim/power/mathexpr_powermodel.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017 ARM Limited + * Copyright (c) 2016-2017, 2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -82,9 +82,8 @@ */ double getStatValue(const std::string & name) const; -void startup(); - -void regStats(); +void startup() override; +void regStats() override; private: /** @@ -96,27 +95,11 @@ */ double eval(const MathExpr ) const; -/** - * Evaluate an expression in the context of this object, set - * failed if evaluation failed. - * - * @param expr Expression to evaluate - * @return Value of expression. - */ -double tryEval(const MathExpr ) const; - // Math expressions for dynamic and static power MathExpr dyn_expr, st_expr; -// Basename of the object in the gem5 stats hierachy -std::string basename; - // Map that contains relevant stats for this power model -std::unordered_map stats_map; - -// Did the expression fail to evaluate (e.g., because a stat value -// can't be resolved) -mutable bool failed; +std::unordered_map statsMap; }; #endif -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27892 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iedaa97eeddf51f7a0a1f222918715da309943be3 Gerrit-Change-Number: 27892 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base, python, sim: Add support for resoving a stat using its name
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27891 )
Change subject: base, python, sim: Add support for resoving a stat using
its name
..
base, python, sim: Add support for resoving a stat using its name
This CL adds resolve, a function in the Stats namespace that allows
access to a stat as specified by its name.
Change-Id: I4fa8bed394b4cb35d9c6cf5d8db062b8d6bb9ca5
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27891
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/base/statistics.cc
M src/base/statistics.hh
2 files changed, 15 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index 036029b..e4315ba 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -54,6 +54,7 @@
#include "base/str.hh"
#include "base/time.hh"
#include "base/trace.hh"
+#include "sim/root.hh"
using namespace std;
@@ -573,6 +574,17 @@
fatal("No registered Stats::reset handler");
}
+const Info *
+resolve(const std::string )
+{
+const auto = nameMap().find(name);
+if (it != nameMap().cend()) {
+return it->second;
+} else {
+return Root::root()->resolveStat(name);
+}
+}
+
void
registerDumpCallback(Callback *cb)
{
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 24a0d06..8f665fe 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -3349,6 +3349,7 @@
void reset();
void enable();
bool enabled();
+const Info* resolve(const std::string );
/**
* Register reset and dump handlers. These are the functions which
--
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Gerrit-Change-Id: I4fa8bed394b4cb35d9c6cf5d8db062b8d6bb9ca5
Gerrit-Change-Number: 27891
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: base: Add support for resolving stats within groups by name
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27890 )
Change subject: base: Add support for resolving stats within groups by name
..
base: Add support for resolving stats within groups by name
This change adds a member function to the Group class that returns a
stat given its name. The function will go through all stats in the
group and its subgroups and will return the stat that matches the
name. For example, if g is the Group system.bigCluster.cpus then a
call to
p = g.resolveStat("ipc")
will return a pointer to the stat system.bigCluster.cpus.ipc.
Change-Id: I5af8401b38b41aee611728f6d1a595f99d22d9de
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27890
Reviewed-by: Bobby R. Bruce
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/base/stats/group.cc
M src/base/stats/group.hh
M src/python/pybind11/stats.cc
3 files changed, 51 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index d054b7a..06eaa46 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019, 2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -117,6 +117,38 @@
statGroups[name] = block;
}
+const Info *
+Group::resolveStat(std::string name) const
+{
+auto pos = name.find(".");
+if (pos == std::string::npos) {
+// look for the stat in this group
+for (auto : stats) {
+if (info->name == name) {
+return info;
+}
+}
+} else {
+// look for the stat in subgroups
+const std::string gname = name.substr(0, pos);
+for (auto : statGroups) {
+if (g.first == gname) {
+return g.second->resolveStat(name.substr(pos + 1));
+}
+}
+}
+
+// finally look for the stat in groups that have been merged
+for (auto : mergedStatGroups) {
+auto info = g->resolveStat(name);
+if (info) {
+return info;
+}
+}
+
+return nullptr;
+}
+
void
Group::mergeStatGroup(Group *block)
{
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index f54df5c..4fd9e79 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019, 2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -157,6 +157,22 @@
*/
void addStatGroup(const char *name, Group *block);
+/**
+ * Resolve a stat by its name within this group.
+ *
+ * This method goes through the stats in this group and sub-groups
+ * and returns a pointer to the the stat that matches the provided
+ * name. The input name has to be relative to the name of this
+ * group. For example, if this group is the SimObject
+ * system.bigCluster.cpus and we want the stat
+ * system.bigCluster.cpus.ipc, the input param should be the
+ * string "ipc".
+ *
+ * @param name Name of the desired stat
+ * @return Pointer to the stat with the provided name
+ */
+const Info * resolveStat(std::string name) const;
+
private:
/**
* Merge the contents (stats & children) of a block to this block.
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 32c3b8b..1149eba 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -128,5 +128,6 @@
.def("getStats", ::Group::getStats)
.def("getStatGroups", ::Group::getStatGroups)
.def("addStatGroup", ::Group::addStatGroup)
+.def("resolveStat", ::Group::resolveStat)
;
}
--
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Gerrit-Change-Id: I5af8401b38b41aee611728f6d1a595f99d22d9de
Gerrit-Change-Number: 27890
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add function that returns all variables in a MathExpr
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27889 )
Change subject: sim: Add function that returns all variables in a MathExpr
..
sim: Add function that returns all variables in a MathExpr
This changes adds support for retrieving all variables in a math
expression. The added function can be called in all valid expressions
and will return the variables in a vector of strings.
Change-Id: I086ba04aa1f798400c97a0b6bf982018a2457c64
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27889
Reviewed-by: Bobby R. Bruce
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/mathexpr.cc
M src/sim/mathexpr.hh
2 files changed, 37 insertions(+), 4 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/mathexpr.cc b/src/sim/mathexpr.cc
index f80c535..0cbcd90 100644
--- a/src/sim/mathexpr.cc
+++ b/src/sim/mathexpr.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -174,3 +174,17 @@
return ret;
}
+void
+MathExpr::getVariables(const Node *n,
+ std::vector ) const
+{
+if (!n || n->op == sValue || n->op == nInvalid) {
+return;
+} else if (n->op == sVariable) {
+variables.push_back(n->variable);
+} else {
+getVariables(n->l, variables);
+getVariables(n->r, variables);
+}
+}
+
diff --git a/src/sim/mathexpr.hh b/src/sim/mathexpr.hh
index b8db739..3dfe2b8 100644
--- a/src/sim/mathexpr.hh
+++ b/src/sim/mathexpr.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
class MathExpr {
public:
@@ -66,6 +67,22 @@
*/
double eval(EvalCallback fn) const { return eval(root, fn); }
+/**
+ * Return all variables in the this expression.
+ *
+ * This function starts from the root node and traverses all nodes
+ * while adding the variables it finds to a vector. Returns the
+ * found variables in a vector of strings
+ *
+ * @return A Vector with the names of all variables
+*/
+std::vector getVariables() const
+{
+std::vector vars;
+getVariables(root, vars);
+return vars;
+}
+
private:
enum Operator {
bAdd, bSub, bMul, bDiv, bPow, uNeg, sValue, sVariable, nInvalid
@@ -119,8 +136,10 @@
/** Eval a node */
double eval(const Node *n, EvalCallback fn) const;
+
+/** Return all variable reachable from a node to a vector of
+ * strings */
+void getVariables(const Node *n, std::vector ) const;
};
#endif
-
-
--
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Gerrit-Change-Id: I086ba04aa1f798400c97a0b6bf982018a2457c64
Gerrit-Change-Number: 27889
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Inheritance fixes in varargs
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28250 )
Change subject: sim: Inheritance fixes in varargs
..
sim: Inheritance fixes in varargs
Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris
---
M src/sim/guest_abi/varargs.hh
1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh
index 6a19db8..07ed2a1 100644
--- a/src/sim/guest_abi/varargs.hh
+++ b/src/sim/guest_abi/varargs.hh
@@ -70,6 +70,8 @@
class VarArgsBase : public VarArgsBase
{
public:
+virtual ~VarArgsBase() = default;
+
// The virtual function takes a reference parameter so that the
different
// _getImpl methods can co-exist through overloading.
virtual void _getImpl(First &) = 0;
@@ -126,6 +128,8 @@
// Declare state to pass to the Argument<>::get methods.
ThreadContext *tc;
typename ABI::State state;
+// Make sure base class _getImpl-es don't get hidden by ours.
+using Base::_getImpl;
// Give the "using" statement in our subclass something to refer to.
void _getImpl();
--
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Gerrit-Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Gerrit-Change-Number: 28250
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Avoid const from member due to ::operator=(...)
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28249 )
Change subject: mem-ruby: Avoid const from member due to
::operator=(...)
..
mem-ruby: Avoid const from member due to ::operator=(...)
Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Signed-off-by: Nikos Nikoleris
---
M src/mem/ruby/slicc_interface/Message.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/ruby/slicc_interface/Message.hh
b/src/mem/ruby/slicc_interface/Message.hh
index 0c2e0aa..1044fe0 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -104,7 +104,7 @@
void setVnet(int net) { vnet = net; }
private:
-const Tick m_time;
+Tick m_time;
Tick m_LastEnqueueTime; // my last enqueue time
Tick m_DelayedTicks; // my delayed cycles
uint64_t m_msg_counter; // FIXME, should this be a 64-bit value?
--
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Gerrit-Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Gerrit-Change-Number: 28249
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Gerrit-Owner: Nikos Nikoleris
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove unused SFINAE causing compilation errors
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28251 )
Change subject: arch-arm: Remove unused SFINAE causing compilation errors
..
arch-arm: Remove unused SFINAE causing compilation errors
clang on MacOS is unable to deduce the template parameters with the
following warning which is turned to an error due to -Werror
build/ARM/arch/arm/aapcs64.hh:90:8: error:
class template partial specialization contains template parameters
that cannot be deduced; this partial specialization will never be used
[-Wunusable-partial-specialization]
Change-Id: Id3cf820c636a5479e2ccd761817cc29a530fe5cc
Signed-off-by: Nikos Nikoleris
---
M src/arch/arm/aapcs64.hh
1 file changed, 0 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 203846d..4dff86a 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -86,10 +86,6 @@
template
struct IsAapcs64ShortVector : public std::false_type {};
-template
-struct IsAapcs64ShortVector> : public
std::true_type
-{};
-
/*
* Composite Types
*/
--
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Gerrit-Change-Id: Id3cf820c636a5479e2ccd761817cc29a530fe5cc
Gerrit-Change-Number: 28251
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Gerrit-Owner: Nikos Nikoleris
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix access modifier in Arm*ProcessBits class
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28248
to review the following change.
Change subject: arch-arm: Fix access modifier in Arm*ProcessBits class
..
arch-arm: Fix access modifier in Arm*ProcessBits class
Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Reviewed-by: Giacomo Travaglini
Signed-off-by: Nikos Nikoleris
---
M src/arch/arm/freebsd/process.hh
M src/arch/arm/linux/process.hh
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/freebsd/process.hh
b/src/arch/arm/freebsd/process.hh
index ac0092e..d52512a 100644
--- a/src/arch/arm/freebsd/process.hh
+++ b/src/arch/arm/freebsd/process.hh
@@ -39,7 +39,7 @@
class ArmFreebsdProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
index 0662d9f..0c15c28 100644
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -1,5 +1,5 @@
/*
-* Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,7 +47,7 @@
class ArmLinuxProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
--
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Gerrit-Change-Number: 28248
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Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove alignment specified from alias declararions
Nikos Nikoleris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28252 ) Change subject: arch-arm: Remove alignment specified from alias declararions .. arch-arm: Remove alignment specified from alias declararions This causes a compilation error on MacOS and it's unclear whether it should be allowed in the first place. In addition, it doesn't seem to be used at the moment. https://stackoverflow.com/questions/15788947/where-can-i-use-alignas-in-c11 Change-Id: Icae4b21de62d69efe4937bdf9a51a473a5323acb Signed-off-by: Nikos Nikoleris --- M src/arch/arm/aapcs64.hh 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh index 4dff86a..d2e45a9 100644 --- a/src/arch/arm/aapcs64.hh +++ b/src/arch/arm/aapcs64.hh @@ -74,8 +74,7 @@ // appropriate alignment requirement. template -using Aapcs64ShortVectorCandidate = -alignas(sizeof(T) * count) uint8_t [sizeof(T) * count]; +using Aapcs64ShortVectorCandidate = uint8_t [sizeof(T) * count]; template using Aapcs64ShortVector = Aapcs64ShortVectorCandidatehttps://gem5-review.googlesource.com/c/public/gem5/+/28252 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icae4b21de62d69efe4937bdf9a51a473a5323acb Gerrit-Change-Number: 28252 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix function signature inconsistencies in semihosting
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28170
to review the following change.
Change subject: arch-arm: Fix function signature inconsistencies in
semihosting
..
arch-arm: Fix function signature inconsistencies in semihosting
Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/semihosting.cc
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 7718cd0..7711a86 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -305,7 +305,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callClose(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callClose(ThreadContext *tc, Handle handle)
{
if (handle > files.size()) {
DPRINTF(Semihosting, "Semihosting SYS_CLOSE(%i): Illegal file\n");
@@ -350,7 +350,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callWrite(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callWrite(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -371,7 +371,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callRead(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callRead(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -404,7 +404,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callIsTTY(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callIsTTY(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -418,7 +418,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callSeek(ThreadContext *tc, uint64_t handle, uint64_t pos)
+ArmSemihosting::callSeek(ThreadContext *tc, Handle handle, uint64_t pos)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -432,7 +432,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callFLen(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callFLen(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
--
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Gerrit-Change-Number: 28170
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, mem-ruby, sim: Add missing overrides
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28168
to review the following change.
Change subject: arch-arm, mem-ruby, sim: Add missing overrides
..
arch-arm, mem-ruby, sim: Add missing overrides
Change-Id: I5ab18960bd61953e6846426adb657818f825
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/isa.hh
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.hh
M src/sim/kernel_workload.hh
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 5fec2db..b4fbbbf 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -726,14 +726,14 @@
unsigned eCount);
void
-serialize(CheckpointOut ) const
+serialize(CheckpointOut ) const override
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
}
void
-unserialize(CheckpointIn )
+unserialize(CheckpointIn ) override
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 620b5ee..1321173 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -102,9 +102,9 @@
void wakeup(); // Used only for deadlock detection
void printProgress(std::ostream& out) const;
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address, DataBlock& data);
@@ -157,18 +157,18 @@
void recordCPWriteCallBack(MachineID myMachID, MachineID senderMachID);
// Alternate implementations in VIPER Coalescer
-virtual RequestStatus makeRequest(PacketPtr pkt);
+virtual RequestStatus makeRequest(PacketPtr pkt) override;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
bool
-isDeadlockEventScheduled() const
+isDeadlockEventScheduled() const override
{
return deadlockCheckEvent.scheduled();
}
void
-descheduleDeadlockEvent()
+descheduleDeadlockEvent() override
{
deschedule(deadlockCheckEvent);
}
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 0569478..bb2819b 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -86,9 +86,9 @@
// Public Methods
void wakeup(); // Used only for deadlock detection
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address,
DataBlock& data,
@@ -106,14 +106,14 @@
const Cycles forwardRequestTime = Cycles(0),
const Cycles firstResponseTime = Cycles(0));
-RequestStatus makeRequest(PacketPtr pkt);
+RequestStatus makeRequest(PacketPtr pkt) override;
bool empty() const;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
-bool isDeadlockEventScheduled() const
+bool isDeadlockEventScheduled() const override
{ return deadlockCheckEvent.scheduled(); }
-void descheduleDeadlockEvent()
+void descheduleDeadlockEvent() override
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index 972a539..b88051a 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -98,7 +98,7 @@
}
bool
-insertSymbol(Addr address, const std::string )
+insertSymbol(Addr address, const std::string ) override
{
return kernelSymtab->insert(address, symbol);
}
--
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Gerrit-Change-Number: 28168
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix mismatch between #ifndef and #define in varargs.hh
Hello Giacomo Travaglini, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28169 to review the following change. Change subject: sim: Fix mismatch between #ifndef and #define in varargs.hh .. sim: Fix mismatch between #ifndef and #define in varargs.hh Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini --- M src/sim/guest_abi/varargs.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh index 41e3c62..6a19db8 100644 --- a/src/sim/guest_abi/varargs.hh +++ b/src/sim/guest_abi/varargs.hh @@ -26,7 +26,7 @@ */ #ifndef __SIM_GUEST_ABI_VARARGS_HH__ -#define __SIM_GUEST_ABI_VARRAGS_HH__ +#define __SIM_GUEST_ABI_VARARGS_HH__ #include #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28169 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Gerrit-Change-Number: 28169 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix inconsistency in variable name
Hello Giacomo Travaglini, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28172 to review the following change. Change subject: arch-arm: Fix inconsistency in variable name .. arch-arm: Fix inconsistency in variable name Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini --- M src/arch/arm/freebsd/process.cc 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/freebsd/process.cc b/src/arch/arm/freebsd/process.cc index 3955f85..d8a7d68 100644 --- a/src/arch/arm/freebsd/process.cc +++ b/src/arch/arm/freebsd/process.cc @@ -118,7 +118,7 @@ void *holdp = (void *)buf2.bufferPtr(); size_t *holdlenp = (size_t *)buf3.bufferPtr(); -ret = sysctl((int *)hnamep, namelen, holdp, holdlenp, hnewp, newlen); +ret = sysctl((int *)hnamep, nameLen, holdp, holdlenp, hnewp, newlen); buf.copyOut(tc->getVirtProxy()); buf2.copyOut(tc->getVirtProxy()); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28172 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Gerrit-Change-Number: 28172 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed the unused parameter m_id from VirtualChannel
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28171
to review the following change.
Change subject: mem-ruby: Removed the unused parameter m_id from
VirtualChannel
..
mem-ruby: Removed the unused parameter m_id from VirtualChannel
Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/mem/ruby/network/garnet2.0/InputUnit.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.hh
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mem/ruby/network/garnet2.0/InputUnit.cc
b/src/mem/ruby/network/garnet2.0/InputUnit.cc
index 8fdce06..640e3b4 100644
--- a/src/mem/ruby/network/garnet2.0/InputUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/InputUnit.cc
@@ -52,7 +52,7 @@
// Instantiating the virtual channels
virtualChannels.reserve(m_num_vcs);
for (int i=0; i < m_num_vcs; i++) {
-virtualChannels.emplace_back(i);
+virtualChannels.emplace_back();
}
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
index 3b077d4..a469a84 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
@@ -31,8 +31,8 @@
#include "mem/ruby/network/garnet2.0/VirtualChannel.hh"
-VirtualChannel::VirtualChannel(int id)
- : m_id(id), inputBuffer(), m_vc_state(IDLE_, Cycles(0)),
m_output_port(-1),
+VirtualChannel::VirtualChannel()
+ : inputBuffer(), m_vc_state(IDLE_, Cycles(0)), m_output_port(-1),
m_enqueue_time(INFINITE_), m_output_vc(-1)
{
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
index 52963c8..752dfb4 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
@@ -40,7 +40,7 @@
class VirtualChannel
{
public:
-VirtualChannel(int id);
+VirtualChannel();
~VirtualChannel() = default;
bool need_stage(flit_stage stage, Cycles time);
@@ -89,7 +89,6 @@
uint32_t functionalWrite(Packet *pkt);
private:
-int m_id;
flitBuffer inputBuffer;
std::pair m_vc_state;
int m_output_port;
--
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Gerrit-Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Gerrit-Change-Number: 28171
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: scons: Disable unsupported -Wl,--as-needed in MacOS
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28173
to review the following change.
Change subject: scons: Disable unsupported -Wl,--as-needed in MacOS
..
scons: Disable unsupported -Wl,--as-needed in MacOS
Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M SConstruct
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/SConstruct b/SConstruct
index 215c0b6..3345148 100755
--- a/SConstruct
+++ b/SConstruct
@@ -359,7 +359,10 @@
main.Append(CCFLAGS=['-I/usr/local/include'])
main.Append(CXXFLAGS=['-I/usr/local/include'])
-main.Append(LINKFLAGS='-Wl,--as-needed')
+# On Mac OS X/Darwin the default linker doesn't support the
+# option --as-needed
+if sys.platform != "darwin":
+main.Append(LINKFLAGS='-Wl,--as-needed')
main['FILTER_PSHLINKFLAGS'] = lambda x: str(x).replace(' -shared', '')
main['PSHLINKFLAGS'] =
main.subst('${FILTER_PSHLINKFLAGS(SHLINKFLAGS)}')
if GetOption('gold_linker'):
--
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Gerrit-Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Gerrit-Change-Number: 28173
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Make variable const to allow derived constexpr
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28167
to review the following change.
Change subject: arch-arm: Make variable const to allow derived constexpr
..
arch-arm: Make variable const to allow derived constexpr
Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/aapcs32.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index fd63483..269c83f 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -558,7 +558,7 @@
if (useBaseABI(state))
return getArgument(tc, state);
-int base = state.allocate(Elem{}, Count);
+const int base = state.allocate(Elem{}, Count);
if (base >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Elem);
HA ha;
--
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Gerrit-Change-Number: 28167
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Creation of PowerState class
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * PowerState declaration and implementation.
+ */
+
+#ifndef __SIM_POWER_STATE_HH__
+#define __SIM_POWER_STATE_HH__
+
+#include
+
+#include "base/callback.hh"
+#include "base/statistics.hh"
+#include "enums/PwrState.hh"
+#include "params/PowerState.hh"
+#include "sim/core.hh"
+#include "sim/sim_object.hh"
+
+/**
+ * Helper class for objects that have power states. This class provides the
+ * basic functionality to change between power states.
+ */
+class PowerState : public SimObject
+{
+ public:
+PowerState(const PowerStateParams *p);
+
+/** Parameters of PowerState object */
+typedef PowerStateParams Params;
+const Params* params() const
+{
+return reinterpret_cast(_params);
+}
+
+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;
+
+/**
+ * Change the power state of this object to the power state p
+ */
+void set(Enums::PwrState p);
+
+
+inline Enums::PwrState get() const
+{
+return _currState;
+}
+
+inline std::string getName() const
+{
+return Enums::PwrStateStrings[_currState];
+}
+
+/** Returns the percentage residency for each power state */
+std::vector getWeights() const;
+
+/**
+ * Record stats values like state residency by computing the time
+ * difference from previous update. Also, updates the previous
evaluation
+ * tick once all stats are recorded.
+ * Usually called on power state change and stats dump callback.
+ */
+void computeStats();
+
+ protected:
+
+/** To keep track of the current power state */
+Enums::PwrState _currState;
+
+/** Last tick the power stats were calculated */
+Tick prvEvalTick;
+
+struct PowerStateStats : public Stats::Group
+{
+PowerStateStats(PowerState );
+
+void regStats() override;
+void preDumpStats() override;
+
+PowerState
+
+Stats::Scalar numTransitions;
+Stats::Distribution ticksClkGated;
+/** Tracks the time spent in each of the power states */
+Stats::Vector pwrStateResidencyTicks;
+} stats;
+};
+
+class PowerStateDumpCallback : public Callback
+{
+PowerState *co;
+ public:
+PowerStateDumpCallback(PowerState *co_t) : co(co_t) {}
+virtual void process() { co->computeStats(); };
+};
+
+#endif //__SIM_POWER_STATE_HH__
--
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Specify the states a PowerState object can be in
Hello Andreas Sandberg, Anouk Van Laer,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28050
to review the following change.
Change subject: sim-power: Specify the states a PowerState object can be in
..
sim-power: Specify the states a PowerState object can be in
This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.
Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg
Signed-off-by: Nikos Nikoleris
---
M src/cpu/BaseCPU.py
M src/sim/PowerState.py
M src/sim/power_state.cc
M src/sim/power_state.hh
4 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 53652bf..feb0eed 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -302,3 +302,7 @@
cpus_node.append(node)
yield cpus_node
+
+def __init__(self, **kwargs):
+super(BaseCPU, self).__init__(**kwargs)
+self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py
index 59491ec..bfa53e2 100644
--- a/src/sim/PowerState.py
+++ b/src/sim/PowerState.py
@@ -62,6 +62,11 @@
# routine
default_state = Param.PwrState("UNDEFINED", "Default Power State")
+# Possible power states this object can be in sorted from the most
+# to the least performant
+possible_states = VectorParam.PwrState(
+[], "Power states this object can be in")
+
clk_gate_min = Param.Latency('1ns',"Min value of the distribution")
clk_gate_max = Param.Latency('1s',"Max value of the distribution")
clk_gate_bins = Param.Unsigned('20', "# bins in clk gated
distribution")
diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index 7074dd6..a2ed7fe 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -40,8 +40,10 @@
#include "base/logging.hh"
PowerState::PowerState(const PowerStateParams *p) :
-SimObject(p), _currState(p->default_state), prvEvalTick(0),
-stats(*this)
+SimObject(p), _currState(p->default_state),
+possibleStates(p->possible_states.begin(),
+ p->possible_states.end()),
+prvEvalTick(0), stats(*this)
{
}
@@ -68,6 +70,11 @@
void
PowerState::set(Enums::PwrState p)
{
+// Check if this power state is actually allowed by checking whether
it is
+// present in pwrStateToIndex-dictionary
+panic_if(possibleStates.find(p) == possibleStates.end(),
+ "Cannot go to %s in %s \n", Enums::PwrStateStrings[p],
name());
+
// Function should ideally be called only when there is a state change
if (_currState == p) {
warn_once("PowerState: Already in the requested power state, "
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index 8cb3b3b..af7527f 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -98,11 +98,22 @@
*/
void computeStats();
+/**
+ * Return the power states this object can be in
+ */
+std::set getPossibleStates() const
+{
+return possibleStates;
+}
+
protected:
/** To keep track of the current power state */
Enums::PwrState _currState;
+/** The possible power states this object can be in */
+const std::set possibleStates;
+
/** Last tick the power stats were calculated */
Tick prvEvalTick;
--
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Gerrit-Change-Number: 28050
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Addition of PowerDomains
egister this object as a follower. This object is
+// dependent on pm for power state transitions
+pm->addFollower(this);
+}
+}
+
+void
+PowerState::setControlledDomain(PowerDomain* pwr_dom)
+{
+// Only a power domain can register as dependant of a power stated
+// object
+controlledDomain = pwr_dom;
+DPRINTF(PowerDomain, "%s is registered as controlled by %s \n",
+ pwr_dom->name(), name());
}
void
@@ -102,6 +119,58 @@
_currState = p;
stats.numTransitions++;
+
+// Update the domain this object controls, if there is one
+if (controlledDomain) {
+controlledDomain->pwrStateChangeCallback(p, this);
+}
+
+}
+
+Enums::PwrState
+PowerState::matchPwrState(Enums::PwrState p)
+{
+// If the object is asked to match a power state, it has to be a
follower
+// and hence should not have a pointer to a powerDomain
+assert(controlledDomain == nullptr);
+
+// If we are already in this power state, ignore request
+if (_currState == p) {
+DPRINTF(PowerDomain, "Already in p-state %s requested to match \n",
+Enums::PwrStateStrings[p]);
+return _currState;
+}
+
+Enums::PwrState old_state = _currState;
+if (possibleStates.find(p) != possibleStates.end()) {
+// If this power state is allowed in this object, just go there
+set(p);
+} else {
+// Loop over all power states in this object and find a power state
+// which is more performant than the requested one (considering we
+// cannot match it exactly)
+for (auto rev_it = possibleStates.crbegin();
+ rev_it != possibleStates.crend(); rev_it++) {
+if (*(rev_it) <= p) {
+// This power state is the least performant power state
that is
+// still more performant than the requested one
+DPRINTF(PowerDomain, "Best match for %s is %s \n",
+ Enums::PwrStateStrings[p],
+ Enums::PwrStateStrings[*(rev_it)]);
+set(*(rev_it));
+break;
+}
+}
+}
+// Check if the transition happened
+// The only case in which the power state cannot change is if the
+// object is already at in its most performant state.
+warn_if((_currState == old_state) &&
+possibleStates.find(_currState) != possibleStates.begin(),
+"Something went wrong in matchPwrState");
+
+stats.numPwrMatchStateTransitions++;
+return _currState;
}
void
@@ -147,6 +216,8 @@
powerState(co),
ADD_STAT(numTransitions,
"Number of power state transitions"),
+ADD_STAT(numPwrMatchStateTransitions,
+ "Number of power state transitions due match request"),
ADD_STAT(ticksClkGated,
"Distribution of time spent in the clock gated state"),
ADD_STAT(pwrStateResidencyTicks,
@@ -164,6 +235,7 @@
const PowerStateParams *p = powerState.params();
numTransitions.flags(nozero);
+numPwrMatchStateTransitions.flags(nozero);
// Each sample is time in ticks
unsigned num_bins = std::max(p->clk_gate_bins, 10U);
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index af7527f..c81a22f 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -52,6 +52,8 @@
#include "sim/core.hh"
#include "sim/sim_object.hh"
+class PowerDomain;
+
/**
* Helper class for objects that have power states. This class provides the
* basic functionality to change between power states.
@@ -68,6 +70,9 @@
return reinterpret_cast(_params);
}
+virtual void addFollower(PowerState* pwr_obj) {};
+void setControlledDomain(PowerDomain* pwr_dom);
+
void serialize(CheckpointOut ) const override;
void unserialize(CheckpointIn ) override;
@@ -99,6 +104,12 @@
void computeStats();
/**
+ * Change the power state of this object to a power state equal to OR
more
+ * performant than p. Returns the power state the object actually went
to.
+ */
+Enums::PwrState matchPwrState(Enums::PwrState p);
+
+/**
* Return the power states this object can be in
*/
std::set getPossibleStates() const
@@ -112,11 +123,17 @@
Enums::PwrState _currState;
/** The possible power states this object can be in */
-const std::set possibleStates;
+std::set possibleStates;
/** Last tick the power stats were calculated */
Tick prvEvalTick;
+/**
+ * The power domain that this power state leads, nullptr if it
+ * doesn't lead any.
+ */
+PowerDomain* controlledDomain;
+
struct PowerStateStats : public Stats::Group
{
PowerStateStats(PowerState );
@@ -127,6 +144,7 @@
PowerState
Stats::Scalar numTransitions;
+Stats::Scalar nu
[gem5-dev] Change in gem5/gem5[develop]: base, python, sim: Add support for resoving a stat using its name
registerHandlers(pythonReset, pythonDump); +registerHandlers(pythonReset, pythonDump, pythonResolve); } } // namespace Stats -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27891 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4fa8bed394b4cb35d9c6cf5d8db062b8d6bb9ca5 Gerrit-Change-Number: 27891 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: base: Add support for resolving stats within groups by name
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27890 )
Change subject: base: Add support for resolving stats within groups by name
..
base: Add support for resolving stats within groups by name
This change adds a member function to the Group class that returns a
stat given its name. The function will go through all stats in the
group and its subgroups and will return the stat that matches the
name. For example, if g is the Group system.bigCluster.cpus then a
call to
p = g.resolveStat("ipc")
will return a pointer to the stat system.bigCluster.cpus.ipc.
Change-Id: I5af8401b38b41aee611728f6d1a595f99d22d9de
Signed-off-by: Nikos Nikoleris
---
M src/base/stats/group.cc
M src/base/stats/group.hh
M src/python/pybind11/stats.cc
3 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index d054b7a..06eaa46 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019, 2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -117,6 +117,38 @@
statGroups[name] = block;
}
+const Info *
+Group::resolveStat(std::string name) const
+{
+auto pos = name.find(".");
+if (pos == std::string::npos) {
+// look for the stat in this group
+for (auto : stats) {
+if (info->name == name) {
+return info;
+}
+}
+} else {
+// look for the stat in subgroups
+const std::string gname = name.substr(0, pos);
+for (auto : statGroups) {
+if (g.first == gname) {
+return g.second->resolveStat(name.substr(pos + 1));
+}
+}
+}
+
+// finally look for the stat in groups that have been merged
+for (auto : mergedStatGroups) {
+auto info = g->resolveStat(name);
+if (info) {
+return info;
+}
+}
+
+return nullptr;
+}
+
void
Group::mergeStatGroup(Group *block)
{
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index f54df5c..4fd9e79 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019, 2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -157,6 +157,22 @@
*/
void addStatGroup(const char *name, Group *block);
+/**
+ * Resolve a stat by its name within this group.
+ *
+ * This method goes through the stats in this group and sub-groups
+ * and returns a pointer to the the stat that matches the provided
+ * name. The input name has to be relative to the name of this
+ * group. For example, if this group is the SimObject
+ * system.bigCluster.cpus and we want the stat
+ * system.bigCluster.cpus.ipc, the input param should be the
+ * string "ipc".
+ *
+ * @param name Name of the desired stat
+ * @return Pointer to the stat with the provided name
+ */
+const Info * resolveStat(std::string name) const;
+
private:
/**
* Merge the contents (stats & children) of a block to this block.
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 32c3b8b..1149eba 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -128,5 +128,6 @@
.def("getStats", ::Group::getStats)
.def("getStatGroups", ::Group::getStatGroups)
.def("addStatGroup", ::Group::addStatGroup)
+.def("resolveStat", ::Group::resolveStat)
;
}
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add function that returns all variables in a MathExpr
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27889 )
Change subject: sim: Add function that returns all variables in a MathExpr
..
sim: Add function that returns all variables in a MathExpr
This changes adds support for retrieving all variables in a math
expression. The added function can be called in all valid expressions
and will return the variables in a vector of strings.
Change-Id: I086ba04aa1f798400c97a0b6bf982018a2457c64
Signed-off-by: Nikos Nikoleris
---
M src/sim/mathexpr.cc
M src/sim/mathexpr.hh
2 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/src/sim/mathexpr.cc b/src/sim/mathexpr.cc
index f80c535..0cbcd90 100644
--- a/src/sim/mathexpr.cc
+++ b/src/sim/mathexpr.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -174,3 +174,17 @@
return ret;
}
+void
+MathExpr::getVariables(const Node *n,
+ std::vector ) const
+{
+if (!n || n->op == sValue || n->op == nInvalid) {
+return;
+} else if (n->op == sVariable) {
+variables.push_back(n->variable);
+} else {
+getVariables(n->l, variables);
+getVariables(n->r, variables);
+}
+}
+
diff --git a/src/sim/mathexpr.hh b/src/sim/mathexpr.hh
index b8db739..3dfe2b8 100644
--- a/src/sim/mathexpr.hh
+++ b/src/sim/mathexpr.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
class MathExpr {
public:
@@ -66,6 +67,22 @@
*/
double eval(EvalCallback fn) const { return eval(root, fn); }
+/**
+ * Return all variables in the this expression.
+ *
+ * This function starts from the root node and traverses all nodes
+ * while adding the variables it finds to a vector. Returns the
+ * found variables in a vector of strings
+ *
+ * @return A Vector with the names of all variables
+*/
+std::vector getVariables() const
+{
+std::vector vars;
+getVariables(root, vars);
+return vars;
+}
+
private:
enum Operator {
bAdd, bSub, bMul, bDiv, bPow, uNeg, sValue, sVariable, nInvalid
@@ -119,8 +136,10 @@
/** Eval a node */
double eval(const Node *n, EvalCallback fn) const;
+
+/** Return all variable reachable from a node to a vector of
+ * strings */
+void getVariables(const Node *n, std::vector ) const;
};
#endif
-
-
--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Change fs_power.py to use absolute paths for stats
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27893 )
Change subject: configs: Change fs_power.py to use absolute paths for stats
..
configs: Change fs_power.py to use absolute paths for stats
fs_power.py is an example script that demonstrates how power models
can be used with gem5. Previously, the formulas used to calculate the
dynamic and static power of the cores and the L2 cache were using
stats in equations as determined by their path relative to the
SimObject where the power model is attached to or full paths. This CL
changes these formulas to refer to the stats only by their full paths.
Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c
Signed-off-by: Nikos Nikoleris
---
M configs/example/arm/fs_power.py
1 file changed, 35 insertions(+), 25 deletions(-)
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index 13afe90..abc759e 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -49,42 +49,52 @@
class CpuPowerOn(MathExprPowerModel):
-# 2A per IPC, 3pA per cache miss
-# and then convert to Watt
-dyn = "voltage * (2 * ipc + " \
-"3 * 0.1 * dcache.overall_misses / sim_seconds)"
-st = "4 * temp"
+def __init__(self, cpu_path, **kwargs):
+super(CpuPowerOn, self).__init__(**kwargs)
+# 2A per IPC, 3pA per cache miss
+# and then convert to Watt
+self.dyn = "voltage * (2 * {}.ipc + 3 * 0.1 * " \
+"{}.dcache.overall_misses /
sim_seconds)".format(cpu_path,
+
cpu_path)
+self.st = "4 * temp"
class CpuPowerOff(MathExprPowerModel):
dyn = "0"
st = "0"
class CpuPowerModel(PowerModel):
-pm = [
-CpuPowerOn(), # ON
-CpuPowerOff(), # CLK_GATED
-CpuPowerOff(), # SRAM_RETENTION
-CpuPowerOff(), # OFF
-]
+def __init__(self, cpu_path, **kwargs):
+super(CpuPowerModel, self).__init__(**kwargs)
+self.pm = [
+CpuPowerOn(cpu_path), # ON
+CpuPowerOff(), # CLK_GATED
+CpuPowerOff(), # SRAM_RETENTION
+CpuPowerOff(), # OFF
+]
class L2PowerOn(MathExprPowerModel):
-# Example to report l2 Cache overall_accesses
-# The estimated power is converted to Watt and will vary based on the
size of the cache
-dyn = "overall_accesses*0.18000"
-st = "(voltage * 3)/10"
+def __init__(self, l2_path, **kwargs):
+super(L2PowerOn, self).__init__(**kwargs)
+# Example to report l2 Cache overall_accesses
+# The estimated power is converted to Watt and will vary based
+# on the size of the cache
+self.dyn = "{}.overall_accesses * 0.18000".format(l2_path)
+self.st = "(voltage * 3)/10"
class L2PowerOff(MathExprPowerModel):
dyn = "0"
st = "0"
class L2PowerModel(PowerModel):
-# Choose a power model for every power state
-pm = [
-L2PowerOn(), # ON
-L2PowerOff(), # CLK_GATED
-L2PowerOff(), # SRAM_RETENTION
-L2PowerOff(), # OFF
-]
+def __init__(self, l2_path, **kwargs):
+super(L2PowerModel, self).__init__(**kwargs)
+# Choose a power model for every power state
+self.pm = [
+L2PowerOn(l2_path), # ON
+L2PowerOff(), # CLK_GATED
+L2PowerOff(), # SRAM_RETENTION
+L2PowerOff(), # OFF
+]
def main():
@@ -105,7 +115,7 @@
continue
cpu.default_p_state = "ON"
-cpu.power_model = CpuPowerModel()
+cpu.power_model = CpuPowerModel(cpu.path())
# Example power model for the L2 Cache of the bigCluster
for l2 in root.system.bigCluster.l2.descendants():
@@ -113,7 +123,7 @@
continue
l2.default_p_state = "ON"
-l2.power_model = L2PowerModel()
+l2.power_model = L2PowerModel(l2.path())
bL.instantiate(options)
--
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Fix the way the power model accesses stats
5 +1,5 @@ /* - * Copyright (c) 2016-2017 ARM Limited + * Copyright (c) 2016-2017, 2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -82,9 +82,8 @@ */ double getStatValue(const std::string & name) const; -void startup(); - -void regStats(); +void startup() override; +void regStats() override; private: /** @@ -96,27 +95,11 @@ */ double eval(const MathExpr ) const; -/** - * Evaluate an expression in the context of this object, set - * failed if evaluation failed. - * - * @param expr Expression to evaluate - * @return Value of expression. - */ -double tryEval(const MathExpr ) const; - // Math expressions for dynamic and static power MathExpr dyn_expr, st_expr; -// Basename of the object in the gem5 stats hierachy -std::string basename; - // Map that contains relevant stats for this power model -std::unordered_map stats_map; - -// Did the expression fail to evaluate (e.g., because a stat value -// can't be resolved) -mutable bool failed; +std::unordered_map statsMap; }; #endif -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27892 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iedaa97eeddf51f7a0a1f222918715da309943be3 Gerrit-Change-Number: 27892 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing include in QARMA implementation
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/27407 ) Change subject: arch-arm: Add missing include in QARMA implementation .. arch-arm: Add missing include in QARMA implementation Change-Id: Ic8a0146968d45ab1007687686eb73639a1c85513 Signed-off-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27407 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com> --- M src/arch/arm/qarma.cc 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved Gem5 Cloud Project GCB service account: Regressions pass diff --git a/src/arch/arm/qarma.cc b/src/arch/arm/qarma.cc index afb8e7c..4e18b7d 100644 --- a/src/arch/arm/qarma.cc +++ b/src/arch/arm/qarma.cc @@ -37,6 +37,8 @@ #include "arch/arm/qarma.hh" +#include + #include "base/bitfield.hh" using namespace QARMA; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27407 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic8a0146968d45ab1007687686eb73639a1c85513 Gerrit-Change-Number: 27407 Gerrit-PatchSet: 2 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com> Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing include in QARMA implementation
Nikos Nikoleris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/27407 ) Change subject: arch-arm: Add missing include in QARMA implementation .. arch-arm: Add missing include in QARMA implementation Change-Id: Ic8a0146968d45ab1007687686eb73639a1c85513 Signed-off-by: Nikos Nikoleris --- M src/arch/arm/qarma.cc 1 file changed, 2 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/qarma.cc b/src/arch/arm/qarma.cc index afb8e7c..4e18b7d 100644 --- a/src/arch/arm/qarma.cc +++ b/src/arch/arm/qarma.cc @@ -37,6 +37,8 @@ #include "arch/arm/qarma.hh" +#include + #include "base/bitfield.hh" using namespace QARMA; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27407 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic8a0146968d45ab1007687686eb73639a1c85513 Gerrit-Change-Number: 27407 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: sim-power: Fix power model to work with stat groups
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26785 )
Change subject: sim-power: Fix power model to work with stat groups
..
sim-power: Fix power model to work with stat groups
The MathExpr framework used by the power model to derive power
estimations requires access to stats from the whole system and
individual SimObjects. Since the introduction of stat groups these
stats can be standalone, in groups or in the default group. This
changeset fixes the power model to look for stats in all possible
locations.
JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-319
Change-Id: I8365d5c17ddc854a03265b204ce974e5168ad5bc
Signed-off-by: Nikos Nikoleris
---
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/mathexpr_powermodel.hh
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/sim/power/mathexpr_powermodel.cc
b/src/sim/power/mathexpr_powermodel.cc
index 13af0fd..fb18410 100644
--- a/src/sim/power/mathexpr_powermodel.cc
+++ b/src/sim/power/mathexpr_powermodel.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017 ARM Limited
+ * Copyright (c) 2016-2017, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -72,6 +72,19 @@
}
}
+// Also collect stats that might be in groups
+for (auto : clocked_object->getStatGroups()) {
+for (auto : g.second->getStats()) {
+const std::string rel_path = g.first + "." + i->name;
+stats_map[rel_path] = i;
+}
+}
+
+// Also collect stats that are in the default group
+for (auto : clocked_object->getStats()) {
+stats_map[i->name] = i;
+}
+
tryEval(st_expr);
const bool st_failed = failed;
diff --git a/src/sim/power/mathexpr_powermodel.hh
b/src/sim/power/mathexpr_powermodel.hh
index d8bd239..9a65302 100644
--- a/src/sim/power/mathexpr_powermodel.hh
+++ b/src/sim/power/mathexpr_powermodel.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017 ARM Limited
+ * Copyright (c) 2016-2017, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -82,7 +82,7 @@
*/
double getStatValue(const std::string & name) const;
-void startup();
+void startup() override;
void regStats();
@@ -112,7 +112,7 @@
std::string basename;
// Map that contains relevant stats for this power model
-std::unordered_map stats_map;
+std::unordered_map stats_map;
// Did the expression fail to evaluate (e.g., because a stat value
// can't be resolved)
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unnecessary exports from pybind enums
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25709 )
Change subject: python: Remove unnecessary exports from pybind enums
..
python: Remove unnecessary exports from pybind enums
According to pybind documentation [1], enum entries use
.export_values() to export the enum entries into the parent
scope. However, strongly typed C++11 class enums are in their own
scope and therefore do not need to be exported.
[1]: https://pybind11.readthedocs.io/en/stable/classes.html#enume
rations-and-internal-types
Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25709
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/python/m5/params.py
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 6033096..3593f95 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1433,7 +1433,8 @@
for val in cls.vals:
code('.value("${val}", ${wrapper_name}::${val})')
code('.value("Num_${name}", ${wrapper_name}::Num_${enum_name})')
-code('.export_values()')
+if not cls.is_class:
+code('.export_values()')
code(';')
code.dedent()
--
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Gerrit-Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Gerrit-Change-Number: 25709
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix argument handling sweep.py
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25710 )
Change subject: configs: Fix argument handling sweep.py
..
configs: Fix argument handling sweep.py
Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25710
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/common/ObjectList.py
M configs/dram/sweep.py
2 files changed, 20 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/common/ObjectList.py b/configs/common/ObjectList.py
index 875fc94..8bffa5f 100644
--- a/configs/common/ObjectList.py
+++ b/configs/common/ObjectList.py
@@ -150,11 +150,26 @@
self._is_obj_class):
self._sub_classes[name] = cls
+class EnumList(ObjectList):
+""" Creates a list of possible values for a given enum class. """
+
+def _add_objects(self):
+""" Add all enum values to the ObjectList """
+self._sub_classes = {}
+for (key, value) in self.base_cls.__members__.items():
+# All Enums have a value Num_NAME at the end which we
+# do not want to include
+if not key.startswith("Num_"):
+self._sub_classes[key] = value
+
+
bp_list = ObjectList(getattr(m5.objects, 'BranchPredictor', None))
cpu_list = CPUList(getattr(m5.objects, 'BaseCPU', None))
hwp_list = ObjectList(getattr(m5.objects, 'BasePrefetcher', None))
indirect_bp_list = ObjectList(getattr(m5.objects, 'IndirectPredictor',
None))
mem_list = ObjectList(getattr(m5.objects, 'AbstractMemory', None))
+dram_addr_map_list = EnumList(getattr(m5.internal.params, 'enum_AddrMap',
+ None))
# Platform aliases. The platforms listed here might not be compiled,
# we make sure they exist before we add them to the platform list.
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index f1f97dc..c2650a7 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -77,9 +77,9 @@
help = "DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and
ranks")
-parser.add_argument("--addr-map",
-choices=m5.objects.AddrMap.vals,
-default="RoRaBaCoCh", help = "DRAM address map policy")
+parser.add_option("--addr-map", type="choice",
+ choices=ObjectList.dram_addr_map_list.get_names(),
+ default="RoRaBaCoCh", help = "DRAM address map policy")
(options, args) = parser.parse_args()
@@ -122,7 +122,7 @@
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
-system.mem_ctrls[0].addr_mapping = args.addr_map
+system.mem_ctrls[0].addr_mapping = options.addr_map
# stay in each state for 0.25 ms, long enough to warm things up, and
# short enough to avoid hitting a refresh
@@ -177,9 +177,8 @@
m5.instantiate()
-addr_map = m5.objects.AddrMap.map[args.addr_map]
-
def trace():
+addr_map = ObjectList.dram_addr_map_list.get(options.addr_map)
generator = dram_generators[options.mode](system.tgen)
for bank in range(1, nbr_banks + 1):
for stride_size in range(burst_size, max_stride + 1, burst_size):
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc
Gerrit-Change-Number: 25710
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix argument handling sweep.py
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25710 )
Change subject: configs: Fix argument handling sweep.py
..
configs: Fix argument handling sweep.py
Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc
Signed-off-by: Nikos Nikoleris
---
M configs/dram/sweep.py
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index f18e44e..af7ca74 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -79,9 +79,9 @@
help = "DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and
ranks")
-parser.add_argument("--addr-map",
-choices=m5.objects.AddrMap.vals,
-default="RoRaBaCoCh", help = "DRAM address map policy")
+parser.add_option("--addr-map", type="choice",
+ choices=m5.objects.AddrMap.vals,
+ default="RoRaBaCoCh", help = "DRAM address map policy")
(options, args) = parser.parse_args()
@@ -124,7 +124,7 @@
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
-system.mem_ctrls[0].addr_mapping = args.addr_map
+system.mem_ctrls[0].addr_mapping = options.addr_map
# stay in each state for 0.25 ms, long enough to warm things up, and
# short enough to avoid hitting a refresh
@@ -179,8 +179,7 @@
m5.instantiate()
-addr_map = m5.objects.AddrMap.map[args.addr_map]
-
+addr_map = m5.internal.params.enum_AddrMap.__members__[options.addr_map]
def trace():
generator = dram_generators[options.mode](system.tgen)
for bank in range(1, nbr_banks + 1):
--
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Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unnecessary exports from pybind enums
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25709 )
Change subject: python: Remove unnecessary exports from pybind enums
..
python: Remove unnecessary exports from pybind enums
According to pybind documentation [1], enum entries use
.export_values() to export the enum entries into the parent
scope. However, strongly typed C++11 class enums are in their own
scope and therefore do not need to be exported.
[1]: https://pybind11.readthedocs.io/en/stable/classes.html#enume
rations-and-internal-types
Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Signed-off-by: Nikos Nikoleris
---
M src/python/m5/params.py
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 9b4198b..e82e96a 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1438,7 +1438,8 @@
for val in cls.vals:
code('.value("${val}", ${wrapper_name}::${val})')
code('.value("Num_${name}", ${wrapper_name}::Num_${enum_name})')
-code('.export_values()')
+if not cls.is_class:
+code('.export_values()')
code(';')
code.dedent()
--
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Gerrit-Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Gerrit-Change-Number: 25709
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Forward snoops when the cache is not responding
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23668 )
Change subject: mem-cache: Forward snoops when the cache is not responding
..
mem-cache: Forward snoops when the cache is not responding
When the MSHR is handling a request that will make the block dirty the
current cache commits respond. When that's not the case the cache
should forward any snoops. This CL fixes MSHR::handleSnoop() to
implement this behavior.
Change-Id: I207e3ca4968fd9528fd4cdbfb3eb95f470b4744d
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23668
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M src/mem/cache/mshr.cc
1 file changed, 5 insertions(+), 6 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 1b21546..00dbe90 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -465,6 +465,10 @@
return true;
}
+// Start by determining if we will eventually respond or not,
+// matching the conditions checked in Cache::handleSnoop
+const bool will_respond = isPendingModified() && pkt->needsResponse()
&&
+!pkt->isClean();
if (isPendingModified() || pkt->isInvalidate()) {
// We need to save and replay the packet in two cases:
// 1. We're awaiting a writable copy (Modified or Exclusive),
@@ -474,11 +478,6 @@
//to forward the snoop up the hierarchy after the current
//transaction completes.
-// Start by determining if we will eventually respond or not,
-// matching the conditions checked in Cache::handleSnoop
-bool will_respond = isPendingModified() && pkt->needsResponse() &&
- !pkt->isClean();
-
// The packet we are snooping may be deleted by the time we
// actually process the target, and we consequently need to
// save a copy here. Clear flags and also allocate new data as
@@ -535,7 +534,7 @@
pkt->setHasSharers();
}
-return true;
+return will_respond;
}
MSHR::TargetList
--
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Gerrit-Branch: master
Gerrit-Change-Id: I207e3ca4968fd9528fd4cdbfb3eb95f470b4744d
Gerrit-Change-Number: 23668
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Ensure that responses get data from the right source
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23667 )
Change subject: mem-cache: Ensure that responses get data from the right
source
..
mem-cache: Ensure that responses get data from the right source
This CL makes sure that we use the right source for data for
responses after a response from the cache below.
Change-Id: I7329f3e6bcb7ce2054e912eb9dea48c9d169d45a
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23667
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M src/mem/cache/cache.cc
1 file changed, 31 insertions(+), 14 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index e7dd5ef..a4f2bae 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -756,7 +756,14 @@
assert(blk->isWritable());
}
-if (blk && blk->isValid() && !mshr->isForward) {
+// Here we decide whether we will satisfy the target using
+// data from the block or from the response. We use the
+// block data to satisfy the request when the block is
+// present and valid and in addition the response in not
+// forwarding data to the cache above (we didn't fill
+// either); otherwise we use the packet data.
+if (blk && blk->isValid() &&
+(!mshr->isForward || !pkt->hasData())) {
satisfyRequest(tgt_pkt, blk, true,
mshr->hasPostDowngrade());
// How many bytes past the first request is this one
@@ -791,15 +798,15 @@
pkt->payloadDelay;
tgt_pkt->req->setExtraData(0);
} else {
-// We are about to send a response to a cache above
-// that asked for an invalidation; we need to
-// invalidate our copy immediately as the most
-// up-to-date copy of the block will now be in the
-// cache above. It will also prevent this cache from
-// responding (if the block was previously dirty) to
-// snoops as they should snoop the caches above where
-// they will get the response from.
if (is_invalidate && blk && blk->isValid()) {
+// We are about to send a response to a cache above
+// that asked for an invalidation; we need to
+// invalidate our copy immediately as the most
+// up-to-date copy of the block will now be in the
+// cache above. It will also prevent this cache from
+// responding (if the block was previously dirty) to
+// snoops as they should snoop the caches above where
+// they will get the response from.
invalidateBlock(blk);
}
// not a cache fill, just forwarding response
@@ -807,12 +814,22 @@
// from lower level cahces/memory to the core.
completion_time += clockEdge(responseLatency) +
pkt->payloadDelay;
-if (pkt->isRead() && !is_error) {
-// sanity check
-assert(pkt->matchAddr(tgt_pkt));
-assert(pkt->getSize() >= tgt_pkt->getSize());
+if (!is_error) {
+if (pkt->isRead()) {
+// sanity check
+assert(pkt->matchAddr(tgt_pkt));
+assert(pkt->getSize() >= tgt_pkt->getSize());
-tgt_pkt->setData(pkt->getConstPtr());
+tgt_pkt->setData(pkt->getConstPtr());
+} else {
+// MSHR targets can read data either from the
+// block or the response pkt. If we can't get data
+// from the block (i.e., invalid or has old data)
+// or the response (did not bring in any data)
+// then make sure that the target didn't expect
+// any.
+assert(!tgt_pkt->hasRespData());
+}
}
// this response did not allocate here and therefore
--
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[gem5-dev] Change in gem5/gem5[master]: scons: Cleanup code that enables asan and ubsan
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23883 )
Change subject: scons: Cleanup code that enables asan and ubsan
..
scons: Cleanup code that enables asan and ubsan
Change-Id: Ie29efc99067dac051536bb099a89f29c940192ec
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23883
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 20 insertions(+), 39 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 5a90808..ec74d69 100755
--- a/SConstruct
+++ b/SConstruct
@@ -435,12 +435,6 @@
main.Append(PSHLINKFLAGS='-flinker-output=rel')
main.Append(PLINKFLAGS='-flinker-output=rel')
-# Make sure we warn if the user has requested to compile with the
-# Undefined Benahvior Sanitizer and this version of gcc does not
-# support it.
-if GetOption('with_ubsan') and compareVersions(gcc_version, '4.9') < 0:
-warning('UBSan is only supported using gcc 4.9 and later.')
-
disable_lto = GetOption('no_lto')
if not disable_lto and main.get('BROKEN_INCREMENTAL_LTO', False) and \
not GetOption('force_lto'):
@@ -466,25 +460,6 @@
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',
'-fno-builtin-realloc', '-fno-builtin-free'])
-# The address sanitizer is available for gcc >= 4.8
-if GetOption('with_asan'):
-if GetOption('with_ubsan') and \
-compareVersions(main['GCC_VERSION'], '4.9') >= 0:
-main.Append(CCFLAGS=['-fsanitize=address,undefined',
- '-fno-omit-frame-pointer'],
-LINKFLAGS='-fsanitize=address,undefined')
-else:
-main.Append(CCFLAGS=['-fsanitize=address',
- '-fno-omit-frame-pointer'],
-LINKFLAGS='-fsanitize=address')
-# Only gcc >= 4.9 supports UBSan, so check both the version
-# and the command-line option before adding the compiler and
-# linker flags.
-elif GetOption('with_ubsan') and \
-compareVersions(main['GCC_VERSION'], '4.9') >= 0:
-main.Append(CCFLAGS='-fsanitize=undefined')
-main.Append(LINKFLAGS='-fsanitize=undefined')
-
elif main['CLANG']:
# Check for a supported version of clang, >= 3.1 is needed to
# support similar features as gcc 4.8. See
@@ -523,21 +498,27 @@
if sys.platform.startswith('freebsd'):
main.Append(LIBS=['thr'])
-# We require clang >= 3.1, so there is no need to check any
-# versions here.
-if GetOption('with_ubsan'):
-if GetOption('with_asan'):
-main.Append(CCFLAGS=['-fsanitize=address,undefined',
- '-fno-omit-frame-pointer'],
- LINKFLAGS='-fsanitize=address,undefined')
-else:
-main.Append(CCFLAGS='-fsanitize=undefined',
-LINKFLAGS='-fsanitize=undefined')
-
-elif GetOption('with_asan'):
-main.Append(CCFLAGS=['-fsanitize=address',
+# Add sanitizers flags
+sanitizers=[]
+if GetOption('with_ubsan'):
+# Only gcc >= 4.9 supports UBSan, so check both the version
+# and the command-line option before adding the compiler and
+# linker flags.
+if not main['GCC'] or compareVersions(main['GCC_VERSION'], '4.9') >= 0:
+sanitizers.append('undefined')
+if GetOption('with_asan'):
+# Available for gcc >= 4.8 or llvm >= 3.1 both a requirement
+# by the build system
+sanitizers.append('address')
+if sanitizers:
+sanitizers = ','.join(sanitizers)
+if main['GCC'] or main['CLANG']:
+main.Append(CCFLAGS=['-fsanitize=%s' % sanitizers,
'-fno-omit-frame-pointer'],
- LINKFLAGS='-fsanitize=address')
+LINKFLAGS='-fsanitize=%s' % sanitizers)
+else:
+warning("Don't know how to enable %s sanitizer(s) for your "
+"compiler." % sanitizers)
# Set up common yacc/bison flags (needed for Ruby)
main['YACCFLAGS'] = '-d'
--
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Gerrit-Change-Number: 23883
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Avoid write merging if there are reads in between
-- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/23666 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b3195858fb33ef85d7aae27376506057dd53ea7 Gerrit-Change-Number: 23666 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: scons: Cleanup code that enables asan and ubsan
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23883 )
Change subject: scons: Cleanup code that enables asan and ubsan
..
scons: Cleanup code that enables asan and ubsan
Change-Id: Ie29efc99067dac051536bb099a89f29c940192ec
Signed-off-by: Nikos Nikoleris
---
M SConstruct
1 file changed, 15 insertions(+), 34 deletions(-)
diff --git a/SConstruct b/SConstruct
index 5a90808..d8ab70d 100755
--- a/SConstruct
+++ b/SConstruct
@@ -466,25 +466,6 @@
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',
'-fno-builtin-realloc', '-fno-builtin-free'])
-# The address sanitizer is available for gcc >= 4.8
-if GetOption('with_asan'):
-if GetOption('with_ubsan') and \
-compareVersions(main['GCC_VERSION'], '4.9') >= 0:
-main.Append(CCFLAGS=['-fsanitize=address,undefined',
- '-fno-omit-frame-pointer'],
-LINKFLAGS='-fsanitize=address,undefined')
-else:
-main.Append(CCFLAGS=['-fsanitize=address',
- '-fno-omit-frame-pointer'],
-LINKFLAGS='-fsanitize=address')
-# Only gcc >= 4.9 supports UBSan, so check both the version
-# and the command-line option before adding the compiler and
-# linker flags.
-elif GetOption('with_ubsan') and \
-compareVersions(main['GCC_VERSION'], '4.9') >= 0:
-main.Append(CCFLAGS='-fsanitize=undefined')
-main.Append(LINKFLAGS='-fsanitize=undefined')
-
elif main['CLANG']:
# Check for a supported version of clang, >= 3.1 is needed to
# support similar features as gcc 4.8. See
@@ -523,21 +504,21 @@
if sys.platform.startswith('freebsd'):
main.Append(LIBS=['thr'])
-# We require clang >= 3.1, so there is no need to check any
-# versions here.
-if GetOption('with_ubsan'):
-if GetOption('with_asan'):
-main.Append(CCFLAGS=['-fsanitize=address,undefined',
- '-fno-omit-frame-pointer'],
- LINKFLAGS='-fsanitize=address,undefined')
-else:
-main.Append(CCFLAGS='-fsanitize=undefined',
-LINKFLAGS='-fsanitize=undefined')
-
-elif GetOption('with_asan'):
-main.Append(CCFLAGS=['-fsanitize=address',
- '-fno-omit-frame-pointer'],
- LINKFLAGS='-fsanitize=address')
+# Add sanitizers' flags
+sanitizers=[]
+if GetOption('with_ubsan'):
+sanitizers.append('undefined')
+if GetOption('with_asan'):
+# Only gcc >= 4.9 supports UBSan, so check both the version
+# and the command-line option before adding the compiler and
+# linker flags.
+if not main['GCC'] or compareVersions(main['GCC_VERSION'], '4.9') >= 0:
+sanitizers.append('address')
+if sanitizers:
+sanitizers = ','.join(sanitizers)
+main.Append(CCFLAGS=['-fsanitize=%s' % sanitizers,
+ '-fno-omit-frame-pointer'],
+LINKFLAGS='-fsanitize=%s' % sanitizers)
# Set up common yacc/bison flags (needed for Ruby)
main['YACCFLAGS'] = '-d'
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ie29efc99067dac051536bb099a89f29c940192ec
Gerrit-Change-Number: 23883
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
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[gem5-dev] Change in gem5/gem5[master]: base: Fix AddrRange::isSubset() check
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23663 )
Change subject: base: Fix AddrRange::isSubset() check
..
base: Fix AddrRange::isSubset() check
Making _end non-inclusive, introduced a bug in isSubset() which was
checking if _end is included in the input address range. This CL
changes the behavior and now we test if _end - 1 is in the range.
Change-Id: Ib8822472b7c266e10d55f3d5cf22a46aa45c1fc7
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23663
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 26 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 2a18551..f53c08b 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -390,7 +390,7 @@
// whether it would fit in a continuous segment of the input
// addr range.
if (r.interleaved()) {
-return r.contains(_start) && r.contains(_end) &&
+return r.contains(_start) && r.contains(_end - 1) &&
size() <= r.granularity();
} else {
return _start >= r._start && _end <= r._end;
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 4ab4ae4..890fb4f 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -261,6 +261,30 @@
EXPECT_FALSE(r2.isSubset(r1));
}
+TEST(AddrRangeTest, isSubsetInterleavedCompleteOverlap)
+{
+AddrRange r1(0x00, 0x100, {0x40}, 0);
+AddrRange r2(0x00, 0x40);
+
+EXPECT_TRUE(r2.isSubset(r1));
+}
+
+TEST(AddrRangeTest, isSubsetInterleavedNoOverlap)
+{
+AddrRange r1(0x00, 0x100, {0x40}, 1);
+AddrRange r2(0x00, 0x40);
+
+EXPECT_FALSE(r2.isSubset(r1));
+}
+
+TEST(AddrRangeTest, isSubsetInterleavedPartialOverlap)
+{
+AddrRange r1(0x00, 0x100, {0x40}, 0);
+AddrRange r2(0x10, 0x50);
+
+EXPECT_FALSE(r2.isSubset(r1));
+}
+
TEST(AddrRangeTest, Contains)
{
AddrRange r(0xF0, 0xF5);
@@ -1038,4 +1062,4 @@
AddrRange r = RangeSize(0x5, 5);
EXPECT_EQ(0x5, r.start());
EXPECT_EQ(0xA, r.end());
-}
\ No newline at end of file
+}
--
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Gerrit-Change-Id: Ib8822472b7c266e10d55f3d5cf22a46aa45c1fc7
Gerrit-Change-Number: 23663
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Assignee: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Forward snoops when the cache is not responding
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23668 )
Change subject: mem-cache: Forward snoops when the cache is not responding
..
mem-cache: Forward snoops when the cache is not responding
When the MSHR is handling a request that will make the block dirty the
current cache commits respond. When that's not the case the cache
should forward any snoops. This CL fixes MSHR::handleSnoop() to
implement this behavior.
Change-Id: I207e3ca4968fd9528fd4cdbfb3eb95f470b4744d
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/mshr.cc
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 0e8d054..e487fba 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -465,6 +465,10 @@
return true;
}
+// Start by determining if we will eventually respond or not,
+// matching the conditions checked in Cache::handleSnoop
+const bool will_respond = isPendingModified() && pkt->needsResponse()
&&
+!pkt->isClean();
if (isPendingModified() || pkt->isInvalidate()) {
// We need to save and replay the packet in two cases:
// 1. We're awaiting a writable copy (Modified or Exclusive),
@@ -474,11 +478,6 @@
//to forward the snoop up the hierarchy after the current
//transaction completes.
-// Start by determining if we will eventually respond or not,
-// matching the conditions checked in Cache::handleSnoop
-bool will_respond = isPendingModified() && pkt->needsResponse() &&
- !pkt->isClean();
-
// The packet we are snooping may be deleted by the time we
// actually process the target, and we consequently need to
// save a copy here. Clear flags and also allocate new data as
@@ -535,7 +534,7 @@
pkt->setHasSharers();
}
-return true;
+return will_respond;
}
MSHR::TargetList
--
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Avoid write merging if there are reads in between
33ef85d7aae27376506057dd53ea7 Gerrit-Change-Number: 23666 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Ensure that responses get data from the right source
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23667 )
Change subject: mem-cache: Ensure that responses get data from the right
source
..
mem-cache: Ensure that responses get data from the right source
This CL makes sure that we use the right source for data for
responses after a response from the cache below.
Change-Id: I7329f3e6bcb7ce2054e912eb9dea48c9d169d45a
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/cache.cc
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index e7dd5ef..65ce9a6 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -756,7 +756,15 @@
assert(blk->isWritable());
}
-if (blk && blk->isValid() && !mshr->isForward) {
+// Here we decide whether we will satisfy targets using
+// data from the block or from the response. If the
+// response is forwarding data to the cache above then the
block
+// we use the block data to satisfy the request when the
+// block is present and valid and in addition the response
+// in not forwarding data to a cache above, otherwise we
+// use the packet data.
+if (blk && blk->isValid() &&
+(!mshr->isForward || !pkt->hasData())) {
satisfyRequest(tgt_pkt, blk, true,
mshr->hasPostDowngrade());
// How many bytes past the first request is this one
@@ -791,15 +799,15 @@
pkt->payloadDelay;
tgt_pkt->req->setExtraData(0);
} else {
-// We are about to send a response to a cache above
-// that asked for an invalidation; we need to
-// invalidate our copy immediately as the most
-// up-to-date copy of the block will now be in the
-// cache above. It will also prevent this cache from
-// responding (if the block was previously dirty) to
-// snoops as they should snoop the caches above where
-// they will get the response from.
if (is_invalidate && blk && blk->isValid()) {
+// We are about to send a response to a cache above
+// that asked for an invalidation; we need to
+// invalidate our copy immediately as the most
+// up-to-date copy of the block will now be in the
+// cache above. It will also prevent this cache from
+// responding (if the block was previously dirty) to
+// snoops as they should snoop the caches above where
+// they will get the response from.
invalidateBlock(blk);
}
// not a cache fill, just forwarding response
@@ -813,6 +821,14 @@
assert(pkt->getSize() >= tgt_pkt->getSize());
tgt_pkt->setData(pkt->getConstPtr());
+} else if (!is_error) {
+// MSHR targets can read data either from the
+// block or the response pkt. If we can't get data
+// from the block (i.e., invalid or has old data)
+// or the response (did not bring in any data)
+// then make sure that the target didn't expect
+// any.
+assert(!tgt_pkt->hasRespData());
}
// this response did not allocate here and therefore
--
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[gem5-dev] Change in gem5/gem5[master]: scons: Do not use sanitizers for the build/TARGET/marshal binary
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23665 )
Change subject: scons: Do not use sanitizers for the build/TARGET/marshal
binary
..
scons: Do not use sanitizers for the build/TARGET/marshal binary
The marshal binary uses a scoped python interpreter in which the
address sanitizer finds a number of leaks. This changeset disables the
use of sanitizers for the mashal binary where any leaks are beyond the
scope of gem5.
Change-Id: I76d49820c51c1067fa4a0c4538d44f59f667cc30
Signed-off-by: Nikos Nikoleris
---
M SConstruct
M src/SConscript
2 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/SConstruct b/SConstruct
index 5a90808..5496796 100755
--- a/SConstruct
+++ b/SConstruct
@@ -470,20 +470,20 @@
if GetOption('with_asan'):
if GetOption('with_ubsan') and \
compareVersions(main['GCC_VERSION'], '4.9') >= 0:
-main.Append(CCFLAGS=['-fsanitize=address,undefined',
- '-fno-omit-frame-pointer'],
-LINKFLAGS='-fsanitize=address,undefined')
+main.Append(SAN_CCFLAGS=['-fsanitize=address,undefined',
+ '-fno-omit-frame-pointer'],
+SAN_LINKFLAGS='-fsanitize=address,undefined')
else:
-main.Append(CCFLAGS=['-fsanitize=address',
- '-fno-omit-frame-pointer'],
-LINKFLAGS='-fsanitize=address')
+main.Append(SAN_CCFLAGS=['-fsanitize=address',
+ '-fno-omit-frame-pointer'],
+SAN_LINKFLAGS='-fsanitize=address')
# Only gcc >= 4.9 supports UBSan, so check both the version
# and the command-line option before adding the compiler and
# linker flags.
elif GetOption('with_ubsan') and \
compareVersions(main['GCC_VERSION'], '4.9') >= 0:
-main.Append(CCFLAGS='-fsanitize=undefined')
-main.Append(LINKFLAGS='-fsanitize=undefined')
+main.Append(SAN_CCFLAGS='-fsanitize=undefined')
+main.Append(SAN_LINKFLAGS='-fsanitize=undefined')
elif main['CLANG']:
# Check for a supported version of clang, >= 3.1 is needed to
@@ -527,17 +527,17 @@
# versions here.
if GetOption('with_ubsan'):
if GetOption('with_asan'):
-main.Append(CCFLAGS=['-fsanitize=address,undefined',
- '-fno-omit-frame-pointer'],
- LINKFLAGS='-fsanitize=address,undefined')
+main.Append(SAN_CCFLAGS=['-fsanitize=address,undefined',
+ '-fno-omit-frame-pointer'],
+ SAN_LINKFLAGS='-fsanitize=address,undefined')
else:
-main.Append(CCFLAGS='-fsanitize=undefined',
-LINKFLAGS='-fsanitize=undefined')
+main.Append(SAN_CCFLAGS='-fsanitize=undefined',
+SAN_LINKFLAGS='-fsanitize=undefined')
elif GetOption('with_asan'):
-main.Append(CCFLAGS=['-fsanitize=address',
- '-fno-omit-frame-pointer'],
- LINKFLAGS='-fsanitize=address')
+main.Append(SAN_CCFLAGS=['-fsanitize=address',
+ '-fno-omit-frame-pointer'],
+ SAN_LINKFLAGS='-fsanitize=address')
# Set up common yacc/bison flags (needed for Ruby)
main['YACCFLAGS'] = '-d'
diff --git a/src/SConscript b/src/SConscript
index 76bbb9e..c136116 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -464,6 +464,11 @@
else:
return env.Program(self.path(env), objs)
+# Add sanitizers compilate and link flags
+env['CCFLAGS'] += env.get('SAN_CCFLAGS', [])
+env['LINKFLAGS'] += env.get('SAN_LINKFLAGS', [])
+
+
class UnitTest(Executable):
'''Create a UnitTest'''
def __init__(self, target, *srcs_and_filts, **kwargs):
--
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[gem5-dev] Change in gem5/gem5[master]: base: Fix AddrRange::isSubset() check
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23663 )
Change subject: base: Fix AddrRange::isSubset() check
..
base: Fix AddrRange::isSubset() check
Making _end non-inclusive, introduced a bug in isSubset() which was
checking if _end is included in the input address range. This CL
changes the behavior and now we test if _end - 1 is in the range.
Change-Id: Ib8822472b7c266e10d55f3d5cf22a46aa45c1fc7
Signed-off-by: Nikos Nikoleris
---
M src/base/addr_range.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 2a18551..f53c08b 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -390,7 +390,7 @@
// whether it would fit in a continuous segment of the input
// addr range.
if (r.interleaved()) {
-return r.contains(_start) && r.contains(_end) &&
+return r.contains(_start) && r.contains(_end - 1) &&
size() <= r.granularity();
} else {
return _start >= r._start && _end <= r._end;
--
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Simplify AMO code generation templates
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22603 )
Change subject: arch-arm: Simplify AMO code generation templates
..
arch-arm: Simplify AMO code generation templates
This change simplifies the isa template for the atomic memory
operation (AMO). Previously the flow had unecessary if statements that
ended up breaking build using clang, due to variables that could
seemingly be used before they were unitialized.
Change-Id: I1b46dfd5f1e90377245c4f649c08b6532b507b9c
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22603
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/templates/mem64.isa
1 file changed, 14 insertions(+), 34 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/templates/mem64.isa
b/src/arch/arm/isa/templates/mem64.isa
index e5df801..3d0302a 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -737,34 +737,27 @@
Trace::InstRecord *traceData) const
{
Addr EA;
-Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
%(usrDecl)s;
-if (fault == NoFault) {
-%(memacc_code)s;
-}
-%(amo_code)s
+%(memacc_code)s;
+
+%(amo_code)s;
assert(amo_op);
-if (fault == NoFault) {
-fault = amoMemAtomic(xc, traceData, Mem, EA,
-memAccessFlags, amo_op);
-}
+const Fault fault = amoMemAtomic(xc, traceData, Mem, EA,
+ memAccessFlags, amo_op);
if (fault == NoFault) {
%(postacc_code)s;
-}
-
-if (fault == NoFault) {
%(op_wb)s;
}
- return fault;
+return fault;
}
}};
@@ -773,26 +766,19 @@
Trace::InstRecord *traceData) const
{
Addr EA;
-Fault fault = NoFault;
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;
%(usrDecl)s;
-if (fault == NoFault) {
-%(memacc_code)s;
-}
+%(memacc_code)s;
%(amo_code)s;
assert(amo_op);
-if (fault == NoFault) {
-fault = initiateMemAMO(xc, traceData, EA, Mem, memAccessFlags,
- amo_op);
-}
-
-return fault;
+return initiateMemAMO(xc, traceData, EA, Mem, memAccessFlags,
+ amo_op);
}
}};
@@ -800,23 +786,17 @@
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
+%(op_decl)s;
+%(op_rd)s;
// ARM instructions will not have a pkt if the predicate is false
getMem(pkt, Mem, traceData);
-if (fault == NoFault) {
-%(postacc_code)s;
-}
+%(postacc_code)s;
-if (fault == NoFault) {
-%(op_wb)s;
-}
+%(op_wb)s;
- return fault;
+return NoFault;
}
}};
--
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Gerrit-Change-Number: 22603
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Simplify AMO code generation templates
Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/22603
to review the following change.
Change subject: arch-arm: Simplify AMO code generation templates
..
arch-arm: Simplify AMO code generation templates
This change simplifies the isa template for the atomic memory
operation (AMO). Previously the flow had unecessary if statements that
ended up breaking build using clang, due to variables that could
seemingly be used before they were unitialized.
Change-Id: I1b46dfd5f1e90377245c4f649c08b6532b507b9c
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/isa/templates/mem64.isa
1 file changed, 14 insertions(+), 34 deletions(-)
diff --git a/src/arch/arm/isa/templates/mem64.isa
b/src/arch/arm/isa/templates/mem64.isa
index e5df801..3d0302a 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -737,34 +737,27 @@
Trace::InstRecord *traceData) const
{
Addr EA;
-Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
%(usrDecl)s;
-if (fault == NoFault) {
-%(memacc_code)s;
-}
-%(amo_code)s
+%(memacc_code)s;
+
+%(amo_code)s;
assert(amo_op);
-if (fault == NoFault) {
-fault = amoMemAtomic(xc, traceData, Mem, EA,
-memAccessFlags, amo_op);
-}
+const Fault fault = amoMemAtomic(xc, traceData, Mem, EA,
+ memAccessFlags, amo_op);
if (fault == NoFault) {
%(postacc_code)s;
-}
-
-if (fault == NoFault) {
%(op_wb)s;
}
- return fault;
+return fault;
}
}};
@@ -773,26 +766,19 @@
Trace::InstRecord *traceData) const
{
Addr EA;
-Fault fault = NoFault;
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;
%(usrDecl)s;
-if (fault == NoFault) {
-%(memacc_code)s;
-}
+%(memacc_code)s;
%(amo_code)s;
assert(amo_op);
-if (fault == NoFault) {
-fault = initiateMemAMO(xc, traceData, EA, Mem, memAccessFlags,
- amo_op);
-}
-
-return fault;
+return initiateMemAMO(xc, traceData, EA, Mem, memAccessFlags,
+ amo_op);
}
}};
@@ -800,23 +786,17 @@
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
+%(op_decl)s;
+%(op_rd)s;
// ARM instructions will not have a pkt if the predicate is false
getMem(pkt, Mem, traceData);
-if (fault == NoFault) {
-%(postacc_code)s;
-}
+%(postacc_code)s;
-if (fault == NoFault) {
-%(op_wb)s;
-}
+%(op_wb)s;
- return fault;
+return NoFault;
}
}};
--
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[gem5-dev] Change in gem5/gem5[master]: mem: Fix DRAM controller to operate on its own address space
// over the banks
bank = addr % banksPerRank;
@@ -343,28 +336,6 @@
// lastly, get the row bits, no need to remove them from addr
row = addr % rowsPerBank;
-} else if (addrMapping == Enums::RoRaBaCoCh) {
-// take out the lower-order column bits
-addr = addr / columnsPerStripe;
-
-// take out the channel part of the address
-addr = addr / channels;
-
-// next, the higher-order column bites
-addr = addr / (columnsPerRowBuffer / columnsPerStripe);
-
-// after the column bits, we get the bank bits to interleave
-// over the banks
-bank = addr % banksPerRank;
-addr = addr / banksPerRank;
-
-// after the bank, we get the rank bits which thus interleaves
-// over the ranks
-rank = addr % ranksPerChannel;
-addr = addr / ranksPerChannel;
-
-// lastly, get the row bits, no need to remove them from addr
-row = addr % rowsPerBank;
} else if (addrMapping == Enums::RoCoRaBaCh) {
// optimise for closed page mode and utilise maximum
// parallelism of the DRAM (at the cost of power)
@@ -372,11 +343,6 @@
// take out the lower-order column bits
addr = addr / columnsPerStripe;
-// take out the channel part of the address, not that this has
-// to match with how accesses are interleaved between the
-// controllers in the address mapping
-addr = addr / channels;
-
// start with the bank bits, as this provides the maximum
// opportunity for parallelism between requests
bank = addr % banksPerRank;
@@ -425,12 +391,13 @@
// address of first DRAM packet is kept unaliged. Subsequent DRAM
packets
// are aligned to burst size boundaries. This is to ensure we
accurately
// check read packets against packets in write queue.
-Addr addr = pkt->getAddr();
+const Addr base_addr = getCtrlAddr(pkt->getAddr());
+Addr addr = base_addr;
unsigned pktsServicedByWrQ = 0;
BurstHelper* burst_helper = NULL;
for (int cnt = 0; cnt < pktCount; ++cnt) {
unsigned size = std::min((addr | (burstSize - 1)) + 1,
-pkt->getAddr() + pkt->getSize()) - addr;
+ base_addr + pkt->getSize()) - addr;
stats.readPktSize[ceilLog2(size)]++;
stats.readBursts++;
stats.masterReadAccesses[pkt->masterId()]++;
@@ -525,10 +492,11 @@
// if the request size is larger than burst size, the pkt is split into
// multiple DRAM packets
-Addr addr = pkt->getAddr();
+const Addr base_addr = getCtrlAddr(pkt->getAddr());
+Addr addr = base_addr;
for (int cnt = 0; cnt < pktCount; ++cnt) {
unsigned size = std::min((addr | (burstSize - 1)) + 1,
-pkt->getAddr() + pkt->getSize()) - addr;
+ base_addr + pkt->getSize()) - addr;
stats.writePktSize[ceilLog2(size)]++;
stats.writeBursts++;
stats.masterWriteAccesses[pkt->masterId()]++;
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 8c8c245..ad2f051 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -819,6 +819,20 @@
unsigned int size, bool isRead) const;
/**
+ * Get an address in a dense range which starts from 0. The input
+ * address is the physical address of the request in an address
+ * space that contains other SimObjects apart from this
+ * controller.
+ *
+ * @param addr The intput address which should be in the addrRange
+ * @return An address in the continues range [0, max)
+ */
+Addr getCtrlAddr(Addr addr)
+{
+return range.getOffset(addr);
+}
+
+/**
* The memory schduler/arbiter - picks which request needs to
* go next, based on the specified policy such as FCFS or FR-FCFS
* and moves it to the head of the queue.
@@ -946,7 +960,6 @@
const uint32_t bankGroupsPerRank;
const bool bankGroupArch;
const uint32_t banksPerRank;
-const uint32_t channels;
uint32_t rowsPerBank;
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
--
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Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Daniel Carvalho
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Gerrit-Reviewer: Matthew Poremba
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Avoid promotion of incompatible deferred targets
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22127 )
Change subject: mem-cache: Avoid promotion of incompatible deferred targets
..
mem-cache: Avoid promotion of incompatible deferred targets
Often a request that hits on an MSHR has to be deferred as it can't be
serviced by the current response.
For example, a request that requires writable has to be deferred when
the response is expected to bring in a read-only copy of the
block. However, there are cases where the response, although not
expected to do so, brings a writable copy and as a result we also
service deferred targets. In such cases, we promote deferred targets
up until the first that can't be serviced by the current response
(e.g., cache maintainance operation). If the first deferred target is
incompatible we don't promote any targets at all.
Change-Id: Ib3e13be51120b7c0f0053b83b76bde03e1b7dd4e
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22127
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Daniel Carvalho
Maintainer: Jason Lowe-Power
---
M src/mem/cache/mshr.cc
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 13a5016..4241fa3 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -612,8 +612,10 @@
void
MSHR::promoteWritable()
{
+PacketPtr def_tgt_pkt = deferredTargets.front().pkt;
if (deferredTargets.needsWritable &&
-!(hasPostInvalidate() || hasPostDowngrade())) {
+!(hasPostInvalidate() || hasPostDowngrade()) &&
+!def_tgt_pkt->req->isCacheInvalidate()) {
// We got a writable response, but we have deferred targets
// which are waiting to request a writable copy (not because
// of a pending invalidate). This can happen if the original
--
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Gerrit-Change-Number: 22127
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix MSHR whole line write tracking
or the fill we therefore use
- * the wasWholeLineWrite field.
+ * Check if this list contains writes that cover an entire
+ * cache line. This is used as part of the miss-packet
+ * creation. Note that new requests may arrive after a
+ * miss-packet has been created, and for the corresponding
+ * fill we use the wasWholeLineWrite field.
*/
bool isWholeLineWrite() const
{
-return onlyWrites &&
-std::all_of(writesBitmap.begin(),
-writesBitmap.end(), [](bool i) { return i; });
+return std::all_of(writesBitmap.begin(), writesBitmap.end(),
+ [](bool i) { return i; });
}
private:
@@ -309,8 +318,8 @@
/** Size of the cache block. */
Addr blkSize;
-/** Are we only dealing with writes. */
-bool onlyWrites;
+/** Indicates whether we can merge incoming write requests */
+bool canMergeWrites;
// NOTE: std::vector might not meet satisfy the
// ForwardIterator requirement and therefore cannot be used
--
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix MSHR whole line write tracking
equirement and therefore cannot be used -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22126 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2 Gerrit-Change-Number: 22126 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Avoid promotion of incompatible deferred targets
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/22127 )
Change subject: mem-cache: Avoid promotion of incompatible deferred targets
..
mem-cache: Avoid promotion of incompatible deferred targets
Often a request that hits on an MSHR has to be deferred as it can't be
serviced by the current response.
For example, a request that requires writable has to be deferred when
the response is expected to bring in a read-only copy of the
block. However, there are cases where the response, although not
expected to do so, brings a writable copy and as a result we also
service deferred targets. In such cases, we promote deferred targets
up until the first that can't be serviced by the current response
(e.g., cache maintainance operation). If the first deferred target is
incompatible we don't promote any targets at all.
Change-Id: Ib3e13be51120b7c0f0053b83b76bde03e1b7dd4e
Signed-off-by: Nikos Nikoleris
---
M src/mem/cache/mshr.cc
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 13a5016..4241fa3 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -612,8 +612,10 @@
void
MSHR::promoteWritable()
{
+PacketPtr def_tgt_pkt = deferredTargets.front().pkt;
if (deferredTargets.needsWritable &&
-!(hasPostInvalidate() || hasPostDowngrade())) {
+!(hasPostInvalidate() || hasPostDowngrade()) &&
+!def_tgt_pkt->req->isCacheInvalidate()) {
// We got a writable response, but we have deferred targets
// which are waiting to request a writable copy (not because
// of a pending invalidate). This can happen if the original
--
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[gem5-dev] Change in gem5/gem5[master]: mem: Fix DRAM controller to operate on its own address space
Hello Wendy Elsasser, Andreas Sandberg, kokoro, Daniel Carvalho, Matthew Poremba, Anthony Gutierrez, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19328 to look at the new patch set (#4). Change subject: mem: Fix DRAM controller to operate on its own address space .. mem: Fix DRAM controller to operate on its own address space Typically, a memory controller is assigned an address range of the form [start, end). This address range might be interleaved and therefore only a non-continuous subset of the addresses in the address range is handed by this controller. Prior to this patch, the DRAM controller was unaware of the interleaving and as a result the address range could affect the mapping of addresses to DRAM ranks, rows and columns. This patch changes the DRAM controller, to transform the input address to a continuous range of the form [0, size). As a result the DRAM controller always operates on a dense and continuous address range regardlesss of the system configuration. Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Signed-off-by: Nikos Nikoleris --- M configs/common/MemConfig.py M src/mem/DRAMCtrl.py M src/mem/dram_ctrl.cc M src/mem/dram_ctrl.hh 4 files changed, 23 insertions(+), 50 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19328 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Gerrit-Change-Number: 19328 Gerrit-PatchSet: 4 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Wendy Elsasser Gerrit-Reviewer: kokoro Gerrit-CC: John Alsop Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Make use of DRAMCtrl::AddrMap in the traffic generators
itfield.hh"
#include "base/intmath.hh"
#include "dram_gen.hh"
+#include "enums/AddrMap.hh"
#include "mem/packet.hh"
class DramRotGen : public DramGen
@@ -84,7 +85,6 @@
* for N banks, we will use banks: 0->(N-1)
* @param nbr_of_ranks Number of ranks utilized,
* @param addr_mapping Address mapping to be used,
- * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramRotGen(SimObject , MasterID master_id, Tick _duration,
@@ -94,7 +94,7 @@
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
-unsigned int addr_mapping,
+Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
: DramGen(obj, master_id, _duration, start_addr, end_addr,
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc
b/src/cpu/testers/traffic_gen/traffic_gen.cc
index db1569b..298e3ea 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -223,12 +223,14 @@
unsigned int page_size;
unsigned int nbr_of_banks_DRAM;
unsigned int nbr_of_banks_util;
-unsigned int addr_mapping;
+unsigned _addr_mapping;
unsigned int nbr_of_ranks;
is >> stride_size >> page_size >>
nbr_of_banks_DRAM >>
-nbr_of_banks_util >> addr_mapping >>
+nbr_of_banks_util >> _addr_mapping >>
nbr_of_ranks;
+Enums::AddrMap addr_mapping =
+ static_cast(_addr_mapping);
if (stride_size > page_size)
warn("DRAM generator stride size (%d) is
greater "
--
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Gerrit-Change-Number: 21080
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Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
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[gem5-dev] Change in gem5/gem5[master]: cpu: Fix checker cpu instantiation
ew O3Checker(params); -return cpu; +return new O3Checker(this); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21079 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0e58ed096c9ea5f413f2e9b64d8d184d9b0fc84e Gerrit-Change-Number: 21079 Gerrit-PatchSet: 2 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Make use of DRAMCtrl::AddrMap in the traffic generators
for N banks, we will use banks: 0->(N-1)
* @param nbr_of_ranks Number of ranks utilized,
* @param addr_mapping Address mapping to be used,
- * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramRotGen(SimObject , MasterID master_id, Tick _duration,
@@ -94,7 +94,7 @@
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
-unsigned int addr_mapping,
+Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
: DramGen(obj, master_id, _duration, start_addr, end_addr,
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc
b/src/cpu/testers/traffic_gen/traffic_gen.cc
index db1569b..298e3ea 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -223,12 +223,14 @@
unsigned int page_size;
unsigned int nbr_of_banks_DRAM;
unsigned int nbr_of_banks_util;
-unsigned int addr_mapping;
+unsigned _addr_mapping;
unsigned int nbr_of_ranks;
is >> stride_size >> page_size >>
nbr_of_banks_DRAM >>
-nbr_of_banks_util >> addr_mapping >>
+nbr_of_banks_util >> _addr_mapping >>
nbr_of_ranks;
+Enums::AddrMap addr_mapping =
+static_cast(_addr_mapping);
if (stride_size > page_size)
warn("DRAM generator stride size (%d) is
greater "
--
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[gem5-dev] Change in gem5/gem5[master]: mem: Fix DRAM controller to operate on its own address space
Hello Wendy Elsasser, Andreas Sandberg, Daniel Carvalho, Matthew Poremba, Anthony Gutierrez, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19328 to look at the new patch set (#3). Change subject: mem: Fix DRAM controller to operate on its own address space .. mem: Fix DRAM controller to operate on its own address space Typically, a memory controller is assigned an address range of the form [start, end). This address range might be interleaved and therefore only a non-continuous subset of the addresses in the address range is handed by this controller. Prior to this patch, the DRAM controller was unaware of the interleaving and as a result the address range could affect the mapping of addresses to DRAM ranks, rows and columns. This patch changes the DRAM controller, to transform the input address to a continuous range of the form [0, size). As a result the DRAM controller always operates on a dense and continuous address range regardlesss of the system configuration. Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Signed-off-by: Nikos Nikoleris --- M configs/common/MemConfig.py M configs/dram/low_power_sweep.py M configs/dram/sweep.py M src/cpu/testers/traffic_gen/dram_gen.cc M src/cpu/testers/traffic_gen/dram_rot_gen.cc M src/mem/DRAMCtrl.py M src/mem/dram_ctrl.cc M src/mem/dram_ctrl.hh 8 files changed, 47 insertions(+), 77 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19328 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Gerrit-Change-Number: 19328 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Wendy Elsasser Gerrit-CC: John Alsop Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Fix checker cpu instantiation
Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0e58ed096c9ea5f413f2e9b64d8d184d9b0fc84e Gerrit-Change-Number: 21079 Gerrit-PatchSet: 1 Gerrit-Owner: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Add Arm full system regressions to the new framework
software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nikos Nikoleris + +''' +Arm FS simulation tests +''' + +from os.path import join as joinpath + +from testlib import * + +arm_fs_quick_tests = [ +'realview-simple-atomic', +'realview-simple-atomic-dual', +'realview-simple-atomic-checkpoint', +'realview-simple-timing', +'realview-simple-timing-dual', +'realview-switcheroo-atomic', +'realview-switcheroo-timing', +] + +arm_fs_long_tests = [ +'realview-o3', +'realview-o3-checker', +'realview-o3-dual', +'realview-minor', +'realview-minor-dual', +'realview-switcheroo-noncaching-timing', +'realview-switcheroo-o3', +'realview-switcheroo-full', +'realview64-simple-atomic', +'realview64-simple-atomic-checkpoint', +'realview64-simple-atomic-dual', +'realview64-simple-timing', +'realview64-simple-timing-dual', +'realview64-o3', +'realview64-o3-checker', +'realview64-o3-dual', +'realview64-minor', +'realview64-minor-dual', +'realview64-switcheroo-atomic', +'realview64-switcheroo-timing', +'realview64-switcheroo-o3', +'realview64-switcheroo-full', +'realview-simple-timing-ruby', +'realview-simple-timing-dual-ruby', +'realview64-simple-timing-ruby', +'realview64-simple-timing-dual-ruby', +] + +tarball = 'aarch-system-2014-10.tar.bz2' +url = "http://gem5.org/dist/current/arm/; + tarball +path = os.path.dirname(os.path.abspath(__file__)) +arm_fs_binaries = DownloadedArchive(url, path, tarball) + +for name in arm_fs_quick_tests: +args = [ joinpath(config.base_dir, 'tests', 'configs', name + '.py') ] +gem5_verify_config( +name=name, +verifiers=(), # Add basic stat verifiers +config=joinpath(path, 'run.py'), +config_args=args, +valid_isas=(constants.arm_tag,), +length=constants.quick_tag, +fixtures=(arm_fs_binaries,) +) + +for name in arm_fs_long_tests: +args = [ joinpath(config.base_dir, 'tests', 'configs', name + '.py') ] +gem5_verify_config( +name=name, +verifiers=(), # TODO: Add basic stat verifiers +config=joinpath(path, 'run.py'), +config_args=args, +valid_isas=(constants.arm_tag,), +length=constants.long_tag, +fixtures=(arm_fs_binaries,) +) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18989 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7e0499c8c3d63798d44f936580eecd40dc650694 Gerrit-Change-Number: 18989 Gerrit-PatchSet: 16 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Rahul Thakur Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Refactor the Gem5Fixture to derive from UniqueFixture
()
-globalfixture(SConsTarget.default_scons_invocation)
-
-invocation = self.default_scons_invocation
-self.invocation = invocation
-
-def schedule_finalized(self, schedule):
-self.invocation.targets.add(self.target)
-return Fixture.schedule_finalized(self, schedule)
-
-class Gem5Fixture(SConsTarget):
-other_invocations = {} # stores scons invocations other than the
default
-
-def __init__(self, isa, variant, protocol=None):
+class Gem5Fixture(SConsFixture):
+def __new__(cls, isa, variant, protocol=None):
+target_dir = joinpath(config.build_dir, isa.upper())
if protocol:
-# When specifying an non-default protocol, we have to make a
-# separate scons invocation with specific parameters. However,
if
-# more than one tests needs the same target, we need to make
sure
-# that we don't call scons too many times.
-target_dir = isa.upper()+'-'+protocol
-target = joinpath(target_dir, 'gem5.%s' % variant)
-if target_dir in self.other_invocations.keys():
-invocation = self.other_invocations[target_dir]
-else:
-options = ['PROTOCOL='+protocol, '--default='+isa.upper()]
-invocation = SConsFixture(options=options)
-globalfixture(invocation)
-Gem5Fixture.other_invocations[target_dir] = invocation
-else:
-target = joinpath(isa.upper(), 'gem5.%s' % variant)
-invocation = None # use default
-super(Gem5Fixture, self).__init__(target, invocation=invocation)
+target_dir += '_' + protocol
+target = joinpath(target_dir, 'gem5.%s' % variant)
+obj = super(Gem5Fixture, cls).__new__(cls, target)
+return obj
+def _init(self, isa, variant, protocol=None):
self.name = constants.gem5_binary_fixture_name
-self.path = self.target
-self.isa = isa
-self.variant = variant
+self.targets = [self.target]
+self.path = self.target
+self.directory = config.base_dir
+
+self.options = []
+if protocol:
+self.options = [ '--default=' + isa.upper(),
+ 'PROTOCOL=' + protocol ]
+self.set_global()
class MakeFixture(Fixture):
def __init__(self, directory, *args, **kwargs):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb
Gerrit-Change-Number: 19251
Gerrit-PatchSet: 12
Gerrit-Owner: Nikos Nikoleris
Gerrit-Assignee: Jason Lowe-Power
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: tests: Add support for downloaded archive fixtures
if e.errno != errno.EEXIST:
raise
-urllib.urlretrieve(self.url, self.path)
+urllib.urlretrieve(self.url, self.filename)
def _getremotetime(self):
-import urllib2, datetime, time
+import datetime, time
import _strptime # Needed for python threading bug
u = urllib2.urlopen(self.url)
@@ -284,18 +286,44 @@
u.info().getheaders("Last-Modified")[0],
"%a, %d %b %Y %X GMT").timetuple())
-def setup(self, testitem):
-import urllib2
+def _setup(self, testitem):
# Check to see if there is a file downloaded
-if not os.path.exists(self.path):
+if not os.path.exists(self.filename):
self._download()
else:
try:
t = self._getremotetime()
except urllib2.URLError:
# Problem checking the server, use the old files.
-log.debug("Could not contact server. Binaries may be old.")
+log.test_log.debug("Could not contact server. Binaries may
be old.")
return
# If the server version is more recent, download it
-if t > os.path.getmtime(self.path):
+if t > os.path.getmtime(self.filename):
self._download()
+
+class DownloadedArchive(DownloadedProgram):
+""" Like TestProgram, but checks the version in the gem5 binary
repository
+and downloads an updated version if it is needed.
+"""
+
+def _extract(self):
+import tarfile
+with tarfile.open(self.filename) as tf:
+tf.extractall(self.path)
+
+def _setup(self, testitem):
+# Check to see if there is a file downloaded
+if not os.path.exists(self.filename):
+self._download()
+self._extract()
+else:
+try:
+t = self._getremotetime()
+except urllib2.URLError:
+# Problem checking the server, use the old files.
+log.test_log.debug("Could not contact server. Binaries may
be old.")
+return
+# If the server version is more recent, download it
+if t > os.path.getmtime(self.filename):
+self._download()
+self._extract()
diff --git a/tests/gem5/hello_se/test_hello_se.py
b/tests/gem5/hello_se/test_hello_se.py
index 5017962..cc62efb 100644
--- a/tests/gem5/hello_se/test_hello_se.py
+++ b/tests/gem5/hello_se/test_hello_se.py
@@ -36,11 +36,14 @@
'arm': ('hello64-static', 'hello32-static'),
}
+urlbase = 'http://gem5.org/dist/current/test-progs/hello/bin/'
for isa in test_progs:
for binary in test_progs[isa]:
import os
-path = os.path.join('test-progs', 'hello', 'bin', isa, 'linux')
-hello_program = DownloadedProgram(path, binary)
+url = urlbase + isa + '/linux/' + binary
+path = joinpath(absdirpath(__file__), '..', 'test-progs', 'hello',
+'bin', isa, 'linux')
+hello_program = DownloadedProgram(url, path, binary)
ref_path = joinpath(getcwd(), 'ref')
@@ -53,6 +56,6 @@
fixtures=(hello_program,),
verifiers=verifiers,
config=joinpath(config.base_dir, 'configs', 'example','se.py'),
-config_args=['--cmd', hello_program.path],
+config_args=['--cmd', joinpath(path, binary)],
valid_isas=(isa.upper(),),
)
diff --git a/tests/gem5/m5_util/test_exit.py
b/tests/gem5/m5_util/test_exit.py
index a766db4..3c99512 100644
--- a/tests/gem5/m5_util/test_exit.py
+++ b/tests/gem5/m5_util/test_exit.py
@@ -37,8 +37,11 @@
r'Exiting @ tick \d* because m5_exit instruction encountered'
)
-test_program = DownloadedProgram('test-progs/m5-exit/bin/x86/linux/',\
-'m5_exit')
+path = joinpath(absdirpath(__file__), '..',
+'test-progs', 'hello', 'bin', 'x86', 'linux')
+filename = 'm5_exit'
+url
= 'http://gem5.org/dist/current/test-progs/m5-exit/bin/x86/linux/m5_exit'
+test_program = DownloadedProgram(url, path, filename)
a = verifier.MatchRegex(m5_exit_regex)
gem5_verify_config(
@@ -46,6 +49,6 @@
verifiers=[a],
fixtures=(test_program,),
config=os.path.join(config.base_dir, 'configs', 'example','se.py'),
-config_args=['--cmd', test_program.path],
+config_args=['--cmd', joinpath(test_program.path, filename)],
valid_isas=('X86',)
)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib3f6ee111b8d6130200507cbd170ecaf9fb39445
Gerrit-Change-Number: 18988
Gerrit-PatchSet: 15
Gerrit-Owner: Nikos Nikoleris
