* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
passed.
*
On 2010-08-11 19:43:23, Nathan Binkert wrote:
It looks like you removed a whole lot of features in this diff. Why did
you do this? Can you explain it in the commit message?
Ruby doesn't work in atomic mode. Therefore it doesn't make sense to have
atomic mode options in this file.
On 2010-08-11 19:47:25, Nathan Binkert wrote:
Not sure what you did here, but I still think you should fix the commit
message.
I fixed the commit message, but hg postreview did not update the description.
Basically this patch is needed to checkpoint in timing mode. Otherwise under
On 2010-08-08 20:53:56, Nathan Binkert wrote:
The commit message is somewhat cryptic.
Nathan Binkert wrote:
Still think it's cryptic.
Again, this is just a problem with hg postreview. Here is what the patch
currently says:
MOESI_hammer: break down miss latency stalled cycles
This
Yep...that is the issue.
BTW, I did use hg mv for this patch.
Brad
-Original Message-
From: Nathan Binkert [mailto:n...@binkert.org]
Sent: Wednesday, August 11, 2010 7:54 PM
To: Default; Beckmann, Brad; Nathan Binkert
Subject: Re: Review Request: ruby: moved python protocol files
Again, this is just a problem with hg postreview. Here is what the patch
currently says:
Understood. It took me a few reviews to realize that the system must
be messed up. (I thought you might ignore some of my suggestions, but
not most of them :)
Nate
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This works, so I hate to complain, but it would be a lot more pythonic to
On 2010-08-12 10:53:49, Steve Reinhardt wrote:
This works, so I hate to complain, but it would be a lot more pythonic to
turn topologies into a Python package (add an __init__.py file) and turn
all the makeTopology() methods into __init__ methods on the respective
Topology
changeset cfbbc9178e7a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cfbbc9178e7a
description:
TimingSimpleCPU: fix NO_ACCESS memory op handling
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so
changeset b69cc0fd934d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b69cc0fd934d
description:
util/m5/m5.c: ensure readfile() buffer pages are in page table
(and marked dirty, in case that matters) by touching them beforehand
diffstat:
util/m5/m5.c | 5
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