Re: [m5-dev] Review Request: ARM: Support switchover with hardware table walkers

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/318/#review497 --- src/cpu/base.cc http://reviews.m5sim.org/r/318/#comment716 I like

Re: [m5-dev] Review Request: O3: Support SWAP and predicated loads/store in ARM.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/319/#review498 --- src/arch/arm/isa/insts/swap.isa

Re: [m5-dev] Review Request: O3: Support squashing all state after special instruction

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/320/#review499 --- Generally I like it. I'll trust that the actual mechanism in the commit

Re: [m5-dev] Review Request: O3: Make the DTLB translateTiming() a split transaction.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/321/#review500 --- src/cpu/base_dyn_inst.hh http://reviews.m5sim.org/r/321/#comment722

Re: [m5-dev] Review Request: O3: Change when the memory ordering violation is checked to after dtlb lookup.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/322/#review501 --- I think this was supposed to go before the dtlb timing one. - Gabe On

[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression --scratch all

* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. *

Re: [m5-dev] Review Request: ARM: Add support for a dumb IDE controller

As feared, this change does break x86 boot. I'll see if I can fix it. Ironically I found this out while adding an X86 FS regression. We really do need to figure out what's going on with those values and how that maps to other ISAs. Gabe Gabe Black wrote: On 2010-11-08 17:56:14, Nathan

Re: [m5-dev] Review Request: ARM: Add support for a dumb IDE controller

It's not an isa thing, it's hard-coded in the struct that is passed to the ide driver. Either way, it-s not those values that is breaking it. They do nothing when they're 0. Ali On Nov 21, 2010, at 11:58 PM, Gabe Black wrote: As feared, this change does break x86 boot. I'll see if I can

Re: [m5-dev] Review Request: ARM: Add support for a dumb IDE controller

Yeah, I figured it out, and a fix will be coming soon. If we're keeping score I'm sure I've accidentally broken more things than you, so no sweat. There will be a regression soon so this will be less likely to happen again. Gabe Ali Saidi wrote: It's not an isa thing, it's hard-coded in the

[m5-dev] changeset in m5: IDE, X86: Fix IDE controller BAR configuration f...

changeset f2ac8da7896e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f2ac8da7896e description: IDE,X86: Fix IDE controller BAR configuration for x86. diffstat: src/dev/ide_ctrl.cc | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diffs (17 lines): diff