*
build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
passed.
*
build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
passed.
*
Did this ever get committed? I'm running into this bug with 20.parser.
Nate
On Wed, Mar 30, 2011 at 8:46 AM, Ali Saidi sa...@umich.edu wrote:
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I think the updated patch addresses all of your
It looks like this patch was committed, but it didn't have anything to
do with the assert. It just happened to change whether or not that
assert was hit. I'll take a look at it sometime soon.
Gabe
On 04/22/11 10:04, nathan binkert wrote:
Did this ever get committed? I'm running into this bug
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of nathan binkert
Sent: Thursday, April 21, 2011 5:53 PM
To: M5 Developer List
Subject: Re: [m5-dev] what scons can do
Maybe so... I think there's a subconscious impression that it
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
Is that 1%/99% a statement of a clean build for m5.fast? I think the much
more common case is you edit one .cc file and rebuild. In that situation, it
sure seems like a lot more than 1% of the time is spent by scons regenerating
and reanalyzing SLICC files.
Whatever it may be, it sure
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src/mem/cache/base.hh
http://reviews.m5sim.org/r/654/#comment1564
On 2011-04-22 18:51:32, Nathan Binkert wrote:
src/mem/cache/base.hh, line 505
http://reviews.m5sim.org/r/654/diff/1/?file=11759#file11759line505
_numSharingContexts has the + 1 in it for devices. Is that a problem?
Seems like you need a parameter to know that.
I have a comment
On 2011-04-22 18:51:32, Nathan Binkert wrote:
src/mem/cache/base.hh, line 503
http://reviews.m5sim.org/r/654/diff/1/?file=11759#file11759line503
This can pretty easily be done with a template:
template class STAT
void
incThreadVectorStat(PacketPtr pkt, STAT
changeset acf4b902c02e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=acf4b902c02e
description:
stats: one more name violation
diffstat:
src/cpu/o3/lsq_unit_impl.hh | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r 914389024c33 -r
changeset d69720504203 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d69720504203
description:
stats: ensure that stat names are valid
diffstat:
src/base/statistics.cc | 34 ++
1 files changed, 34 insertions(+), 0 deletions(-)
diffs
changeset 6e368a935ac0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6e368a935ac0
description:
tests: updates for stat name change
diffstat:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |
4 +-
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