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[m5-dev] changeset in inorder-patches: organize patches
changeset d33c963656cb in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d33c963656cb
description:
organize patches
diffstat:
10 files changed, 3446 insertions(+), 10152 deletions(-)
fix_compile.diff| 94
fix_mdu_latency_bug | 533 ---
fix_mixie_per_stage_tracing | 205 -
import_mixie| 5782
make_mixie_cmdline_runnable | 37
mixie_hello_world | 6729 ---
prepare_cpus.diff | 65
prepare_exetrace.diff | 34
prepare_mips.diff | 110
series |9
diffs (truncated from 15803 to 300 lines):
diff -r d8514fbac071 -r d33c963656cb fix_compile.diff
--- a/fix_compile.diff Fri Feb 06 16:28:10 2009 -0800
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,94 +0,0 @@
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
a/src/cpu/mixie/cpu.cc
-+++ b/src/cpu/mixie/cpu.cc
-@@ -152,7 +152,7 @@
- miscRegFile(this),
- timeBuffer(2 , 2),
- removeInstsThisCycle(false),
-- activityRec(NumStages, 10, params-activity),
-+ activityRec(params-name, NumStages, 10, params-activity),
- switchCount(0),
- deferRegistration(false/*params-deferRegistration*/),
- stageTracing(params-stageTracing),
-@@ -250,10 +250,10 @@
- pipelineStage[stNum]-setTimeBuffer(timeBuffer);
-
- // Take Care of 1st/Nth stages
--if (stNum != 0)
-+if (stNum 0)
- pipelineStage[stNum]-setPrevStageQueue(stageQueue[stNum - 1]);
--if (stNum != NumStages - 1)
--pipelineStage[stNum]-setNextStageQueue(stageQueue[stNum]);
-+if (stNum NumStages - 2)
-+pipelineStage[stNum]-setNextStageQueue(stageQueue[stNum + 1]);
- }
-
- // Initialize thread specific variables
-diff --git a/src/cpu/mixie/first_stage.cc b/src/cpu/mixie/first_stage.cc
a/src/cpu/mixie/first_stage.cc
-+++ b/src/cpu/mixie/first_stage.cc
-@@ -144,7 +144,10 @@
-
- #if TRACING_ON
- inst-traceData =
--tracer-getInstRecord(ThePipeline::NumStages,
cpu-stageTracing);
-+tracer-getInstRecord(ThePipeline::NumStages,
-+ cpu-stageTracing,
-+ cpu-thread[tid]-getTC());
-+
- #endif // TRACING_ON
-
- DPRINTF(RefCount, creation: [tid:%i]: [sn:%i]: Refcount = %i.\n,
-diff --git a/src/cpu/mixie/mixie_trace.cc b/src/cpu/mixie/mixie_trace.cc
a/src/cpu/mixie/mixie_trace.cc
-+++ b/src/cpu/mixie/mixie_trace.cc
-@@ -74,7 +74,8 @@
-
- MixieTraceRecord *
- MixieTrace::getInstRecord(Tick when, ThreadContext *tc,
-- const StaticInstPtr staticInst, Addr pc)
-+const StaticInstPtr staticInst, Addr pc,
-+const StaticInstPtr macroStaticInst, MicroPC upc)
- {
- return new MixieTraceRecord(ThePipeline::NumStages, true, tc);
- }
-diff --git a/src/cpu/mixie/mixie_trace.hh b/src/cpu/mixie/mixie_trace.hh
a/src/cpu/mixie/mixie_trace.hh
-+++ b/src/cpu/mixie/mixie_trace.hh
-@@ -89,7 +89,8 @@
- getInstRecord(unsigned num_stages, bool stage_tracing, ThreadContext *tc);
-
- virtual MixieTraceRecord *getInstRecord(Tick when, ThreadContext *tc,
--const StaticInstPtr staticInst, Addr pc);
-+const StaticInstPtr staticInst, Addr pc,
-+const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0);
- };
-
- /* namespace Trace */ }
-diff --git a/src/cpu/mixie/resources/cache_unit.cc
b/src/cpu/mixie/resources/cache_unit.cc
a/src/cpu/mixie/resources/cache_unit.cc
-+++ b/src/cpu/mixie/resources/cache_unit.cc
-@@ -450,8 +450,11 @@
- findRequest(cache_pkt-cacheReq-getInst()));
- assert(cache_req);
-
-+#if TRACING_ON
- // Get resource request info
- unsigned tid = 0;
-+#endif
-+
- //tid = pkt-req-getThreadNum();
- unsigned stage_num = cache_req-getStageNum();
- DynInstPtr inst = cache_req-inst;
-diff --git a/src/cpu/mixie/thread_context.hh b/src/cpu/mixie/thread_context.hh
a/src/cpu/mixie/thread_context.hh
-+++ b/src/cpu/mixie/thread_context.hh
-@@ -69,6 +69,8 @@
-
- /** Returns a pointer to the DTB. */
- TheISA::DTB *getDTBPtr() { return cpu-dtb; }
-+
-+System *getSystemPtr() { return cpu-system; }
-
- /** Returns a pointer to this CPU. */
- virtual BaseCPU *getCpuPtr() { return cpu; }
diff -r d8514fbac071 -r d33c963656cb fix_mdu_latency_bug
--- a/fix_mdu_latency_bug Fri Feb 06 16:28:10 2009 -0800
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,533 +0,0 @@
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
a/src/cpu/mixie/cpu.cc
-+++ b/src/cpu/mixie/cpu.cc
-@@ -162,6 +162,7 @@
- cpu_params = params;
-
- resPool = new ResourcePool(this, params);
-+//resPool-init();
-
- coreType = default; // eventually get this from params
-
-diff --git a/src/cpu/mixie/pipeline_traits.cc
[m5-dev] changeset in inorder-patches: Make sure everything compiles just...
changeset 40721d032036 in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=40721d032036
description:
Make sure everything compiles just fine
diffstat:
2 files changed, 15 insertions(+), 11 deletions(-)
import_mixie |4 +---
prepare_cpus.diff | 22 ++
diffs (66 lines):
diff -r 71012a6974ed -r 40721d032036 import_mixie
--- a/import_mixie Fri Feb 06 17:32:54 2009 -0800
+++ b/import_mixie Fri Feb 06 17:53:25 2009 -0800
@@ -231,11 +231,10 @@
new file mode 100644
--- /dev/null
+++ b/src/cpu/mixie/SConsopts
-@@ -0,0 +1,35 @@
+@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007 MIPS Technologies, Inc.
-+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
@@ -266,7 +265,6 @@
+Import('*')
+
+all_cpu_list.append('MixieCPU')
-+default_cpus.append('MixieCPU')
diff --git a/src/cpu/mixie/comm.hh b/src/cpu/mixie/comm.hh
new file mode 100644
--- /dev/null
diff -r 71012a6974ed -r 40721d032036 prepare_cpus.diff
--- a/prepare_cpus.diff Fri Feb 06 17:32:54 2009 -0800
+++ b/prepare_cpus.diff Fri Feb 06 17:53:25 2009 -0800
@@ -6,24 +6,30 @@
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
-@@ -54,6 +54,8 @@
- virtual Fault completeAcc(Packet *pkt, %s *xc,
+@@ -48,12 +48,14 @@
+
+ # Template for execute() signature.
+ exec_sig_template = '''
+-virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
+-virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
++virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
++virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
+ { panic(initiateAcc not defined!); M5_DUMMY_RETURN };
+-virtual Fault completeAcc(Packet *pkt, %s *xc,
++virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
Trace::InstRecord *traceData) const
{ panic(completeAcc not defined!); M5_DUMMY_RETURN };
-+virtual int memAccSize(%s *xc)
++virtual int memAccSize(%(type)s *xc)
+{ panic(memAccSize not defined!); M5_DUMMY_RETURN };
'''
mem_ini_sig_template = '''
-@@ -82,7 +84,10 @@
+@@ -82,7 +84,7 @@
'''
for cpu in temp_cpu_list:
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
-print f, exec_sig_template % (xc_type, xc_type, xc_type)
-+#print f, exec_sig_template % (xc_type, xc_type, xc_type)
-+
-+# Needed for Mixie CPU Model
-+print f, exec_sig_template % (xc_type, xc_type, xc_type, xc_type)
++print f, exec_sig_template % { 'type' : xc_type }
print f, '''
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
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[m5-dev] changeset in inorder-patches: Rename mixie to inorder
changeset d3fea0b4646c in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d3fea0b4646c
description:
Rename mixie to inorder
diffstat:
3 files changed, 1185 insertions(+), 1185 deletions(-)
import_mixie| 2364 +--
make_mixie_cmdline_runnable |4
prepare_cpus.diff |2
diffs (truncated from 5891 to 300 lines):
diff -r 40721d032036 -r d3fea0b4646c import_mixie
--- a/import_mixie Fri Feb 06 17:53:25 2009 -0800
+++ b/import_mixie Fri Feb 06 17:58:45 2009 -0800
@@ -12,13 +12,13 @@
CpuModel('O3CPU', 'o3_cpu_exec.cc',
'#include cpu/o3/isa_specific.hh',
{ 'CPU_exec_context': 'O3DynInst' })
-+CpuModel('MixieCPU', 'mixie_cpu_exec.cc',
-+ '#include cpu/mixie/mixie_dyn_inst.hh',
-+ { 'CPU_exec_context': 'MixieDynInst' })
-diff --git a/src/cpu/mixie/MixieCPU.py b/src/cpu/mixie/MixieCPU.py
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/MixieCPU.py
++CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
++ '#include cpu/inorder/inorder_dyn_inst.hh',
++ { 'CPU_exec_context': 'InOrderDynInst' })
+diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/InOrderCPU.py
@@ -0,0 +1,80 @@
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
@@ -53,8 +53,8 @@
+from m5 import build_env
+from BaseCPU import BaseCPU
+
-+class MixieCPU(BaseCPU):
-+type = 'MixieCPU'
++class InOrderCPU(BaseCPU):
++type = 'InOrderCPU'
+activity = Param.Unsigned(0, Initial count)
+numThreads = Param.Unsigned(1, number of HW thread contexts)
+
@@ -100,10 +100,10 @@
+div24RepeatRate = Param.Unsigned(1, Repeat Rate for 24-bit Divide
Operations)
+div32Latency = Param.Unsigned(1, Latency for 32-bit Divide Operations)
+div32RepeatRate = Param.Unsigned(1, Repeat Rate for 32-bit Divide
Operations)
-diff --git a/src/cpu/mixie/MixieTrace.py b/src/cpu/mixie/MixieTrace.py
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/MixieTrace.py
+diff --git a/src/cpu/inorder/InOrderTrace.py b/src/cpu/inorder/InOrderTrace.py
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/InOrderTrace.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
@@ -137,13 +137,13 @@
+from m5.params import *
+from InstTracer import InstTracer
+
-+class MixieTrace(InstTracer):
-+type = 'MixieTrace'
-+cxx_class = 'Trace::MixieTrace'
-diff --git a/src/cpu/mixie/SConscript b/src/cpu/mixie/SConscript
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/SConscript
++class InOrderTrace(InstTracer):
++type = 'InOrderTrace'
++cxx_class = 'Trace::InOrderTrace'
+diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/SConscript
@@ -0,0 +1,82 @@
+# -*- mode:python -*-
+
@@ -177,30 +177,30 @@
+
+Import('*')
+
-+if 'MixieCPU' in env['CPU_MODELS']:
-+ SimObject('MixieCPU.py')
-+ SimObject('MixieTrace.py')
++if 'InOrderCPU' in env['CPU_MODELS']:
++ SimObject('InOrderCPU.py')
++ SimObject('InOrderTrace.py')
+
+ TraceFlag('ResReqCount')
+ TraceFlag('FreeList')
-+ TraceFlag('MixieCachePort')
-+ TraceFlag('MixieStage')
-+ TraceFlag('MixieStall')
-+ TraceFlag('MixieCPU')
-+ TraceFlag('MixieMDU')
++ TraceFlag('InOrderCachePort')
++ TraceFlag('InOrderStage')
++ TraceFlag('InOrderStall')
++ TraceFlag('InOrderCPU')
++ TraceFlag('InOrderMDU')
+ TraceFlag('RegDepMap')
+ TraceFlag('Rename')
-+ TraceFlag('MixieDynInst')
++ TraceFlag('InOrderDynInst')
+ TraceFlag('Resource')
+ TraceFlag('RefCount')
+
-+ CompoundFlag('MixieCPUAll', [ 'MixieStage', 'MixieStall', 'MixieCPU',
-+ 'MixieMDU', 'RegDepMap', 'Resource', 'Rename'])
++ CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
'InOrderCPU',
++ 'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
+
+ Source('pipeline_traits.cc')
-+ Source('mixie_dyn_inst.cc')
-+ Source('mixie_cpu_builder.cc')
-+ Source('mixie_trace.cc')
++ Source('inorder_dyn_inst.cc')
++ Source('inorder_cpu_builder.cc')
++ Source('inorder_trace.cc')
+ Source('pipeline_stage.cc')
+ Source('first_stage.cc')
+ Source('resource.cc')
@@ -227,10 +227,10 @@
+ Source('thread_context.cc')
+ Source('cpu.cc')
+
-diff --git a/src/cpu/mixie/SConsopts b/src/cpu/mixie/SConsopts
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/SConsopts
+diff --git a/src/cpu/inorder/SConsopts b/src/cpu/inorder/SConsopts
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/SConsopts
@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
@@ -264,11 +264,11 @@
+
+Import('*')
+
-+all_cpu_list.append('MixieCPU')
-diff --git a/src/cpu/mixie/comm.hh
[m5-dev] changeset in m5: Quell g++ 4.3 warning about operator ambiguity
changeset 8c1aa74572e4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8c1aa74572e4
description:
Quell g++ 4.3 warning about operator ambiguity
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |2 +-
diffs (12 lines):
diff -r 68c52fee5a53 -r 8c1aa74572e4 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Feb 04 16:26:15 2009 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Fri Feb 06 20:55:50 2009 -0800
@@ -1074,7 +1074,7 @@
// Fall through on purpose
case SegIntGateCheck:
// Make sure the gate's the right type.
-if (m5reg.mode == LongMode ((desc.type 0xe) != 0xe) ||
+if ((m5reg.mode == LongMode (desc.type 0xe) != 0xe) ||
((desc.type 0x6) != 0x6)) {
fault = new GeneralProtection(0);
}
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[m5-dev] IsReadBarrier instruction flag
I notice that we have static inst flags called IsMemBarrier and IsWriteBarrier, but no IsReadBarrier or equivalent. Should we? I need something like that to implement the lfence instruction. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] IsReadBarrier instruction flag
We don't have it because we haven't implemented an ISA that supports it, so I see no reason not to add it. (It's pretty odd to put a fence in for reads and not want writes to be fenced too.) Nate On Fri, Feb 6, 2009 at 9:06 PM, Gabe Black gbl...@eecs.umich.edu wrote: I notice that we have static inst flags called IsMemBarrier and IsWriteBarrier, but no IsReadBarrier or equivalent. Should we? I need something like that to implement the lfence instruction. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] IsReadBarrier instruction flag
Yeah, well, x86 cornered the market on odd. Gabe nathan binkert wrote: We don't have it because we haven't implemented an ISA that supports it, so I see no reason not to add it. (It's pretty odd to put a fence in for reads and not want writes to be fenced too.) Nate On Fri, Feb 6, 2009 at 9:06 PM, Gabe Black gbl...@eecs.umich.edu wrote: I notice that we have static inst flags called IsMemBarrier and IsWriteBarrier, but no IsReadBarrier or equivalent. Should we? I need something like that to implement the lfence instruction. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
scons: *** [build/ALPHA_SE/python/m5/defines.py.fo] Error 1 scons: *** [build/ALPHA_FS/python/m5/defines.py.fo] Error 1 scons: *** [build/MIPS_SE/python/m5/defines.py.fo] Error 1 scons: *** [build/SPARC_SE/python/m5/defines.py.fo] Error 1 scons: *** [build/X86_SE/python/m5/defines.py.fo] Error 1 scons: *** [build/X86_SE/python/swig/core_wrap.fo] Error 1 scons: *** [build/X86_SE/params/params_wrap.fo] Error 1 scons: *** [build/X86_SE/arch/x86/atomic_simple_cpu_exec.fo] Error 1 scons: *** [build/X86_SE/arch/x86/timing_simple_cpu_exec.fo] Error 1 See /z/m5/regression/regress-2009-02-07-03:00:01 for details. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
