I think that's been going on for quite some time and it must be my
fault. While a new params_wrap.cc is generated, it doesn't trigger
params_wrap.cc to be recompiled and the simulator to be relinked, so
the effect is minimal. That said, I'll try to fix it after HPCA.
Nate
> Some recent change
Some recent change causes the params_wrap.cc file to be constantly
rebuilt. Every time I build M5 (even if there have been no changes) I
see the following swig line:
swig -c++ -python -modern -templatereduce -Iext/dnet -I/usr/include/
python2.5 -Ibuild/libelf -Ibuild/ALPHA_FS -outdir build/ALP
changeset 24d9f0941095 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=24d9f0941095
description:
Add the ability to specify a think time before descriptor
fetch/writeback starts/ends as well as after read/write dmas
diffstat:
3 files changed, 7 insertions(+), 1 deletio
changeset d8ab33f5ff9a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d8ab33f5ff9a
description:
Return an UnimpFault for an ITB translation of an uncachable address.
We don't support fetching from uncached addresses in Alpha and it means that a
speculative fetch can cl
changeset 92b89377be48 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=92b89377be48
description:
More subtle fixes to how interrupts are supposed to work in the device.
Fix postedInterrupts statistics.
diffstat:
0 files changed
diffs (59 lines):
diff -r d8ab33f5ff9a
changeset 9eaf72819836 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9eaf72819836
description:
Add the ability for a DMA to tack on an extra delay after the DMA is
actually finished.
diffstat:
2 files changed, 3 insertions(+), 3 deletions(-)
src/dev/io_device.cc |
Well, with things like PCI Message-Signaled Interrupts (MSI) you do end up
carrying interrupt notifications etc. across the same interconnect that
supports memory traffic, so to some extent it's a general issue with real
platforms and not an x86-ism. Of course the complexity of figuring out who
to
I actually think trying to make the memory system support the broadcast would
probably be too much of a burden for what it gets you in x86. I can't point to
anything immediate that fundamentally wouldn't work without broadcast, so I'll
think about this more and see if I can come up with something t
Well, if these are going out over the memory system, then there would be
unrealistic traffic and contention from all the messages. It's likely it
would be small and infrequent so that's likely not a big problem. One
thing that would be harder to work out logistically is that means the
sender ha
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed.
* build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru
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