changeset 9af8736c26be in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9af8736c26be
description:
X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was
intended.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
changeset e61df5581723 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e61df5581723
description:
ARM: Add operands for the load/store double instructions.
diffstat:
1 file changed, 16 insertions(+), 12 deletions(-)
src/arch/arm/isa/operands.isa | 28
changeset 987a9082b354 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=987a9082b354
description:
ARM: Add load/store double instructions.
diffstat:
1 file changed, 90 insertions(+)
src/arch/arm/isa/decoder.isa | 90 ++
diffs
changeset cc0c9db8ca55 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cc0c9db8ca55
description:
ARM: Don't always update CPSR.
diffstat:
2 files changed, 2 insertions(+), 2 deletions(-)
src/arch/arm/isa/formats/mem.isa |3 ++-
src/arch/arm/isa/formats/util.isa |
changeset a2af27fbc06c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a2af27fbc06c
description:
ARM: Get rid of end_addr in the ArmMacroStore constructor.
diffstat:
1 file changed, 2 insertions(+), 18 deletions(-)
src/arch/arm/isa/formats/macromem.isa | 20
changeset e518d78b2ed1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e518d78b2ed1
description:
ARM: Get rid of the MemAcc and EAComp static insts.
diffstat:
4 files changed, 9 insertions(+), 251 deletions(-)
src/arch/arm/insts/macromem.hh|9 -
changeset 7f10d636910b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7f10d636910b
description:
ARM: Move the memory microops out of the decoder and into the ISA desc.
diffstat:
4 files changed, 97 insertions(+), 89 deletions(-)
src/arch/arm/insts/macromem.hh|
changeset be6658746087 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=be6658746087
description:
ARM: Move the remaining microops out of the decoder and into the ISA
desc.
diffstat:
3 files changed, 31 insertions(+), 18 deletions(-)
src/arch/arm/isa/decoder.isa
changeset 30d1e27daf68 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=30d1e27daf68
description:
ISA parser: Allow alternative read/write code for operands.
diffstat:
1 file changed, 92 insertions(+), 3 deletions(-)
src/arch/isa_parser.py | 95
changeset 95f69a436c82 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=95f69a436c82
description:
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and
characteristics
of the ISA in the
changeset 781969fbeca9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=781969fbeca9
description:
Registers: Get rid of the float register width parameter.
diffstat:
46 files changed, 154 insertions(+), 1181 deletions(-)
src/arch/alpha/floatregfile.hh |
changeset c7295a4826d5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c7295a4826d5
description:
Registers: Eliminate the ISA defined floating point register file.
diffstat:
30 files changed, 83 insertions(+), 1082 deletions(-)
src/arch/alpha/SConscript |
changeset 51f3026d4cbb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=51f3026d4cbb
description:
Registers: Eliminate the ISA defined integer register file.
diffstat:
28 files changed, 27 insertions(+), 628 deletions(-)
src/arch/alpha/intregfile.cc | 22 -
changeset f2d04014f531 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f2d04014f531
description:
MIPS: Phase out MIPS's int_regfile.hh.
diffstat:
3 files changed, 24 insertions(+), 72 deletions(-)
src/arch/mips/regfile.cc |1
changeset 906b993e799e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=906b993e799e
description:
X86: Phase out x86's intregfile.hh.
diffstat:
2 files changed, 6 insertions(+), 103 deletions(-)
src/arch/x86/intregfile.hh | 102
changeset f983bb952b0a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f983bb952b0a
description:
ARM: Flush out the ARM's int_regfile.hh.
diffstat:
3 files changed, 30 insertions(+), 78 deletions(-)
src/arch/arm/regfile/int_regfile.hh | 77
changeset c14676e17110 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c14676e17110
description:
Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
diffstat:
5 files changed, 17 insertions(+), 98 deletions(-)
src/arch/alpha/SConscript|1
changeset 611bb0263b9a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=611bb0263b9a
description:
MIPS: Get rid of an orphaned MIPS .cc file.
diffstat:
1 file changed, 146 deletions(-)
src/arch/mips/regfile.cc | 146 --
diffs
changeset fd0f91f067d2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fd0f91f067d2
description:
ARM, Simple CPU: Fix an index and add assert checks.
diffstat:
3 files changed, 16 insertions(+), 10 deletions(-)
src/arch/arm/isa_traits.hh | 13 +++--
changeset a535b2232c08 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a535b2232c08
description:
Registers: Move the PCs out of the ISAs and into the CPUs.
diffstat:
15 files changed, 76 insertions(+), 388 deletions(-)
src/arch/alpha/regfile.cc|4 -
changeset 008930a4ace5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=008930a4ace5
description:
Registers: Eliminate the ISA defined RegFile class.
diffstat:
17 files changed, 115 deletions(-)
src/arch/alpha/miscregfile.hh |1 -
src/arch/alpha/regfile.cc
changeset f6148086f997 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f6148086f997
description:
Alpha: Move reg_redir into its own files, and move some constants into
regfile.hh.
diffstat:
8 files changed, 65 insertions(+), 39 deletions(-)
src/arch/alpha/SConscript
changeset 67dbc192f692 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=67dbc192f692
description:
Registers: Collapse ARM and MIPS regfile directories.
diffstat:
17 files changed, 1081 insertions(+), 1153 deletions(-)
src/arch/arm/SConscript |2
changeset 5d8b91875859 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5d8b91875859
description:
Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs
changeset 786136379872 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=786136379872
description:
Alpha: Pull the MiscRegFile fully into the ISA object.
diffstat:
13 files changed, 169 insertions(+), 345 deletions(-)
src/arch/alpha/SConscript |1
changeset d947798df4a1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d947798df4a1
description:
Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
diffstat:
22 files changed, 19 insertions(+), 148 deletions(-)
src/arch/alpha/ev5.cc |
scons: *** Source `build/ALPHA_SE/arch/alpha/regredir.cc' not found, needed by
target `build/ALPHA_SE/arch/alpha/regredir.fo'.
scons: *** Source `build/ALPHA_FS/arch/alpha/regredir.cc' not found, needed by
target `build/ALPHA_FS/arch/alpha/regredir.fo'.
*
I'm sorta just dreaming here, but I'm getting used to occasionally browsing
the code through repo.m5sim.org, and it would be really nice if:
1. We had a web-based cross-reference (like lxr), so I don't have to switch
from firefox to an ssh session running cscope.
2a. Better yet, if there was a
(moving this over to m5-dev)
M5 has a multi-phase startup process too for dealing with these
dependencies. I don't see it documented explicitly anywhere unfortunately.
Here's the gist of it though (based on a combination of memory and quick
code browsing, so it may not be authoritative):
- As
- You're guaranteed that any SimObject that is passed to you as a parameter
has been constructed before your constructor is called, so that the pointer
in the params struct is valid. Since init() hasn't been called yet you
can't assume too much about what that other object is prepared to do
On Thu, Jul 9, 2009 at 1:24 PM, nathan binkert n...@binkert.org wrote:
- You're guaranteed that any SimObject that is passed to you as a
parameter
has been constructed before your constructor is called, so that the
pointer
in the params struct is valid. Since init() hasn't been called
Quoting nathan binkert n...@binkert.org:
- You're guaranteed that any SimObject that is passed to you as a parameter
has been constructed before your constructor is called, so that the pointer
in the params struct is valid. Since init() hasn't been called yet you
can't assume too much about
changeset 9425c8a86e5c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9425c8a86e5c
description:
ARM: Fold the MiscRegFile all the way into the ISA object.
diffstat:
4 files changed, 37 insertions(+), 178 deletions(-)
src/arch/arm/SConscript |1
changeset a08470cb53e5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a08470cb53e5
description:
SPARC: Fold the MiscRegFile all the way into the ISA object.
diffstat:
11 files changed, 816 insertions(+), 964 deletions(-)
src/arch/sparc/SConscript |1
changeset 25635830e33c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=25635830e33c
description:
X86: Fold the MiscRegFile all the way into the ISA object.
diffstat:
6 files changed, 318 insertions(+), 569 deletions(-)
src/arch/x86/SConscript |1
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