Re: [m5-dev] Review Request: Remove CacheMsg class from SLICC

On Fri, 18 Mar 2011, Lisa Hsu wrote: What's going on with this patch? I don't believe it's been committed but it seems like it should. I've also got some patches waiting behind this because they used to touch CacheMsg and I don't want to mess Nilay up, so I've been waiting to serialize behind

[m5-dev] Review Request: Ruby: Convert CacheRequestType to RubyRequestType

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/602/ --- Review request for Default. Summary --- Ruby: Convert CacheRequestType to Ruby

[m5-dev] Review Request: Ruby: Convert AccessModeType to RubyAccessMode

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/601/ --- Review request for Default. Summary --- Ruby: Convert AccessModeType to RubyAc

Re: [m5-dev] Review Request: cpu: split o3-specific parts out of BaseDynInst

> On 2011-03-03 20:41:09, Ali Saidi wrote: > > Please don't ship this until I have a chance to try it, I just want to make > > sure it doesn't break ARM_FS/O3. > > Korey Sewell wrote: > Sure, I'd welcome a go of things from some other folks to test if I > haven't introduced something quirk

Re: [m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/598/#review993 --- configs/example/se.py

Re: [m5-dev] Review Request: configs: combine ruby_se.py and se.py to avoid all that code duplication

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/600/#review992 --- configs/example/se.py

Re: [m5-dev] Review Request: enable x86 workloads on se.py

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/599/#review991 --- configs/example/se.py

Re: [m5-dev] Review Request: cpu: split o3-specific parts out of BaseDynInst

> On 2011-03-03 20:41:09, Ali Saidi wrote: > > Please don't ship this until I have a chance to try it, I just want to make > > sure it doesn't break ARM_FS/O3. > > Korey Sewell wrote: > Sure, I'd welcome a go of things from some other folks to test if I > haven't introduced something quirk

Re: [m5-dev] Review Request: Remove CacheMsg class from SLICC

What's going on with this patch? I don't believe it's been committed but it seems like it should. I've also got some patches waiting behind this because they used to touch CacheMsg and I don't want to mess Nilay up, so I've been waiting to serialize behind this. Lisa On Wed, Feb 9, 2011 at 1:28

[m5-dev] Review Request: configs: combine ruby_se.py and se.py to avoid all that code duplication

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/600/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: enable x86 workloads on se.py

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/599/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/598/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

> On 2011-03-18 13:57:35, Gabe Black wrote: > > src/sim/syscall_emul.hh, line 503 > > > > > > Why is this change necessary? I'm not 100% sure why it was the way it > > was before, but I see no reason to change it either. Ch

Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

> On 2011-03-18 13:57:35, Gabe Black wrote: > > src/sim/syscall_emul.hh, line 503 > > > > > > Why is this change necessary? I'm not 100% sure why it was the way it > > was before, but I see no reason to change it either. Ch

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

> On 2011-02-27 21:41:48, Gabe Black wrote: > > Should we put an assert in there to make sure no access is bigger than 16 > > bytes? Also what about unaligned accesses? I think those will be split on > > cache block boundaries which may be bigger or smaller than 16 bytes. We > > might have an

Re: [m5-dev] Review Request: sparc: compilation fixes for inorder

> On 2011-03-16 15:17:00, Gabe Black wrote: > > src/arch/sparc/registers.hh, line 80 > > > > > > This seems redundant. Can't the CPU model add them up just as easily? > > Korey Sewell wrote: > The CPU Model could calcula

Re: [m5-dev] Review Request: isa: get rid of expandForMT function

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/578/#review982 --- Ship it! Looks good. Thanks for fixing it up. - Gabe On 2011-03-17 20:

Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/589/#review981 --- src/sim/syscall_emul.hh

Re: [m5-dev] Review Request: patch from Vince Weaver for review

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/588/#review980 --- It seems like we should be able to emulate the access system call fairly

[m5-dev] Hung up for a bit

Hey folks. My computer decided to eat itself yesterday and my file system ended up mangled. I think the important stuff in my home directory survived, but I'm in a Starbucks right now trying to get it straightened out. Please give me a few days extra slack responding since I don't know when

Re: [m5-dev] Review Request: ISA parser: Set up op_src_decl and op_dest_decl for pc operands.

> On 2011-03-17 18:09:40, Korey Sewell wrote: > > src/arch/isa_parser.py, line 184 > > > > > > Hi Gabe, not to be nitpicky but what are you trying to accomplish with > > this change? > > > > I have no objection to

[m5-dev] changeset in m5: SLICC: Remove external_type for structures

changeset 9a6a02a235f1 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9a6a02a235f1 description: SLICC: Remove external_type for structures In SLICC, in order to define a type a data type for which it should not generate any code, the keyword external_type

[m5-dev] changeset in m5: SLICC: Remove the keyword wake_up_dependents

changeset 099771c7725d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=099771c7725d description: SLICC: Remove the keyword wake_up_dependents In order to add stall and wait facility for protocols, a keyword wake_up_dependents was introduced. This patch rem

[m5-dev] changeset in m5: SLICC: Remove the keyword wake_up_all_dependents

changeset f3d1493787d4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f3d1493787d4 description: SLICC: Remove the keyword wake_up_all_dependents In order to add stall and wait facility for protocols, a keyword wake_up_all_dependents was introduced. This p

[m5-dev] changeset in m5: base: disable FastAlloc in debug builds by default

changeset a6052f50deed in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=a6052f50deed description: base: disable FastAlloc in debug builds by default FastAlloc's reuse policies can mask allocation bugs, so we typically want it disabled when debugging. Set

[m5-dev] changeset in m5: swig: get rid of m5.internal.random module (swi...

changeset e641f702653a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e641f702653a description: swig: get rid of m5.internal.random module (swig/random.i) Thanks to swig this was interfering with the standard Python random module. The only function in th

Re: [m5-dev] Ruby FS - DMA Controller problem?

Hi Korey, I don't seem to have encountered that deadlock threshold when booting the old changeset. I tried both 16 + 20 core configurations just now and they seem to work. Although, they do take a really really long time compared to ~1-4 cores. I have also tried previously booting 64 cores, some

Re: [m5-dev] Ruby FS - DMA Controller problem?

Why did it work before the block size patch? > - When the ChuckGenerator sees the block size is 0, it doesn't split up the > request into multiple patches and sends the whole dma request at once. That > is fine because the DMASequencer splits the request into multiple requests > and only respond

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

> On 2011-02-27 21:41:48, Gabe Black wrote: > > Should we put an assert in there to make sure no access is bigger than 16 > > bytes? Also what about unaligned accesses? I think those will be split on > > cache block boundaries which may be bigger or smaller than 16 bytes. We > > might have an

[m5-dev] Cron /z/m5/regression/do-regression quick

scons: *** Source `tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt' not found, needed by target `build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/status'. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-ti