[m5-dev] Linux Kernel/Boot Time for X86_FS

wondering if anyone is currently working on this, or if I could get some pointers on where to dig in. Thank you, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness

Re: [m5-dev] Linux Kernel/Boot Time for X86_FS

PM, Joel Hestness wrote: Hi everyone, I am interested in helping develop X86_FS boot up and testing. Under X86_FS, I have been able to boot a couple different versions of the Linux kernel (v2.6.22.9 and v2.6.28.4), but the bring up requires more than 12 hours of simulation time. I am

[m5-dev] Configuration file for building Linux x86

wondering if there are any critical options that I need to look for in the .config file, or if anyone has a .config specifically for building X86_FS kernel binaries. Also, any tips for debugging M5 Linux boot? Thank you, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer

[m5-dev] M5 X86_FS pseudo instruction: readfile

? Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] X86_FS vtophys implementation

that to find out if there is something else wrong before you dig through the memory system. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer

Re: [m5-dev] X86_FS vtophys implementation

for this job. Gabe Joel Hestness wrote: Hi, It turns out that the readfile bug I posted previously (see below) is a result of an unimplemented vtophys function: CopyIn reads the file in, but the virtual address where it should be placed is not translated to a physical address before

[m5-dev] Booting Linux, X86_FS Timing CPU

test for when the Request::NO_ACCESS flag is set. I wonder if the same should occur in TimingSimpleCPU::write? Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness Starting program

Re: [m5-dev] Review Request: util/m5/m5.c: in readfile(), added memset to touch all pages - ensure they are in the page table

m5op_x86.S (eliminate it completely from the m5 utility codebase). - Gabe -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5

[m5-dev] Review Request: SIMPLE TIMING: when a request is NO_ACCESS (x86 CDA microinstruction), TimingSimpleCPU::completeDataAccess must still complete

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/65/ --- Review request for Default. Summary --- SIMPLE TIMING: when a request is

[m5-dev] Review Request: TimingCPU: REPOST: Request::NO_ACCESS bypass in completeDataAccess

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/66/ --- Review request for Default. Summary --- TimingCPU: REPOST: Request::NO_ACCESS

Re: [m5-dev] Review Request: util/m5/m5.c: in readfile(), added memset to touch all pages - ensure they are in the page table

Reserved for user, but it's not if it ends up being assigned an official use. Why would we want to have reserved2_func but not reserved1_func? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel

[m5-dev] Checkpointing x86

and PS2Mouse have state that might need to be checkpointed (e.g. mouse status in the case that Linux enables/disables it). Should PS2Device descend from SimObject? (if so, through a particular subclass of SimObject?) Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept

Re: [m5-dev] Review Request: TimingCPU: REPOST: Request::NO_ACCESS bypass in completeDataAccess

, visit: http://reviews.m5sim.org/r/66/#review111 --- Ship it! - Steve On 2010-07-28 16:05:00, Joel Hestness wrote: --- This is an automatically generated e-mail. To reply

[m5-dev] Review Request: M5 utility: remove reserve1_func to build for x86

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/120/ --- Review request for Default. Summary --- ./util/m5/m5op_x86.S: To get the m5

Re: [m5-dev] Review Request: M5 utility: Touch all pages in readfile buffer

size. - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/121/#review154 --- On 2010-08-09 10:35:49, Joel Hestness wrote

[m5-dev] IntDev and intmessage question

? Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] IntDev and intmessage question

*MessagePort (mem/mport.hh) not MemPort... sorry for any confusion Joel On Tue, Aug 10, 2010 at 3:46 PM, Joel Hestness hestn...@cs.utexas.eduwrote: Hi, I'm looking at the interrupt device interface (dev/x86/IntDev.hh) and intmessage (arch/x86/intmessage.hh) code, and I have a question

Re: [m5-dev] Regression tests for X86

for SPEC2000/2006 benchmarks, I want that to pass the regression tests first. Thanks and Regards, Dibakar Gope Texas AM University ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD

[m5-dev] changeset in m5: TimingSimpleCPU: fix NO_ACCESS memory op handling

changeset cfbbc9178e7a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=cfbbc9178e7a description: TimingSimpleCPU: fix NO_ACCESS memory op handling When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so

[m5-dev] changeset in m5: util/m5/m5.c: ensure readfile() buffer pages ar...

changeset b69cc0fd934d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=b69cc0fd934d description: util/m5/m5.c: ensure readfile() buffer pages are in page table (and marked dirty, in case that matters) by touching them beforehand diffstat: util/m5/m5.c | 5

[m5-dev] TimingSimpleCPU, x86: sendSplitData packet sender states

(pkt2), it looks like there is a bug with the dynamic_cast and clearFromParent since the cast is called on pkt1-senderState. This doesn't affect correctness, but it does leave references that affect deletion of the packets. Is that correct? -- Joel Hestness PhD Student, Computer Architecture

Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData packet sender states

in sendSplitData to the senderState that may eventually call clearFromParent rather than trying to get the senderState back out after the call to handleReadPacket. Does sound reasonable? Thanks, Joel On Tue, Aug 17, 2010 at 3:11 PM, Joel Hestness hestn...@cs.utexas.eduwrote: Hi, I am currently looking

[m5-dev] TimingSimpleCPU, x86: sendSplitData + TLB miss

are in flight :\). Would it make sense to have similar state queuing in the x86 page table walker? Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness

[m5-dev] Unable to checkpoint restore into detailed/timing CPU

if system.getMemoryMode() != objects.params.timing: AttributeError: 'module' object has no attribute 'timing' ---OUTPUT Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness

Re: [m5-dev] Unable to checkpoint restore into detailed/timing CPU

, Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness

Re: [m5-dev] Unable to checkpoint restore into detailed/timing CPU

/sim/init.cc:248 #26 0x004097fb in main (argc=9, argv=0x7fffe108) at build/ALPHA_FS/sim/main.cc:57 --OUTPUT Is it possible that these issues are related? Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept

Re: [m5-dev] Unable to checkpoint restore into detailed/timing CPU

are the cause of the seg fault (see attached). Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness valgrind.out Description: Binary data ___ m5-dev

[m5-dev] Statistics Output Conventions

are mixed, either lowerCamelCase or lower_case_with_underscores. I'm wondering if there is a convention for statistic names that are output to the stats.txt that I (we) can be aiming for. Thanks, Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science

Re: [m5-dev] Review Request: IntDev: latency fix

On 2011-01-07 04:34:28, Gabe Black wrote: See review of the earlier IntDev patch. Basically this is displacing the latency value from the base class that uses it into the subclass that gets it from the config. I don't think it's necessary as described previously, but also that

Re: [m5-dev] Review Request: MessagePort: implemented virtual recvTiming avoiding double delete

On 2011-01-07 04:21:05, Gabe Black wrote: I think there are two problems with this patch. First, if at all possible we should avoid the code duplication we'd now have for the recvTiming function. Second, while this probably does fix the legitimate problem of deleting packets twice, I

Re: [m5-dev] Review Request: x86: page table walker functional support

On 2011-01-07 04:45:16, Gabe Black wrote: src/arch/x86/vtophys.cc, line 58 http://reviews.m5sim.org/r/385/diff/1/?file=9054#file9054line58 Better wording might be Need access to page tables. I like that change On 2011-01-07 04:45:16, Gabe Black wrote: src/arch/x86/vtophys.cc,

Re: [m5-dev] Review Request: x86: Timing support for pagetable walker

On 2011-01-07 05:51:30, Gabe Black wrote: The code seems ok, but why do we need to have multiple outstanding page walks in timing mode again? Gabe Black wrote: Actually, I wrote the above before I'd read it carefully. My question still stands, but there are some areas that need

Re: [m5-dev] Error in Simulating Mesh Network

, line 198] Do you think that the options I have specified should work correctly? Thanks Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept

Re: [m5-dev] changeset in m5: checkpointing: fix bug from curTick accessor co...

-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas

[m5-dev] changeset in m5: IntDev: packet latency fix

changeset 8b05ff5ef958 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=8b05ff5ef958 description: IntDev: packet latency fix The x86 local apic now includes a separate latency parameter for interrupts. diffstat: src/arch/x86/X86LocalApic.py | 2 ++

[m5-dev] changeset in m5: x86: implements vtophys

changeset f9b675da608a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f9b675da608a description: x86: implements vtophys Calls walker to look up virt. to phys. page mapping diffstat: src/arch/x86/pagetable_walker.hh | 1 + src/arch/x86/system.cc |

[m5-dev] changeset in m5: Ruby: Add support for locked memory accesses in...

changeset 4e83ebb67794 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=4e83ebb67794 description: Ruby: Add support for locked memory accesses in X86_FS diffstat: src/mem/ruby/libruby.cc | 8 ++ src/mem/ruby/libruby.hh | 2 +

[m5-dev] changeset in m5: Ruby: Fix to return cache block size to CPU for...

changeset eee578ed2130 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=eee578ed2130 description: Ruby: Fix to return cache block size to CPU for split data transfers diffstat: src/mem/ruby/system/RubyPort.cc | 6 ++ src/mem/ruby/system/RubyPort.hh | 2 ++ 2

[m5-dev] changeset in m5: x86: Add checkpointing capability to devices

changeset 7fcfb515d7bf in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7fcfb515d7bf description: x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237,

[m5-dev] changeset in m5: x86: Timing support for pagetable walker

changeset a9f05ab40763 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=a9f05ab40763 description: x86: Timing support for pagetable walker Move page table walker state to its own object type, and make the walker instantiate state for each outstanding

[m5-dev] changeset in m5: TimingSimpleCPU: split data sender state fix

changeset 267e1e16e51b in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=267e1e16e51b description: TimingSimpleCPU: split data sender state fix In sendSplitData, keep a pointer to the senderState that may be updated after the call to handle*Packet. This

[m5-dev] changeset in m5: garnet: Split network power in ruby.stats

changeset 3a02353d6e43 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3a02353d6e43 description: garnet: Split network power in ruby.stats Split out dynamic and static power numbers for printing to ruby.stats diffstat:

Re: [m5-dev] Testing Functional Access

: How can I test whether or not functional accesses to the memory are working correctly? Do we have some regression test for this? Thanks Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness

Re: [m5-dev] changeset in m5: garnet: removed flit_width from Routers

m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev

Re: [m5-dev] [m5-users] Tracing does not work

facility it self that Nate corrected yesterday. Nilay ___ m5-users mailing list m5-us...@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science

Re: [m5-dev] [m5-users] Tracing does not work

, but I'm not sure why that would have changed at all. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas