Hello,
Is there any way to enable the compilation of unit tests? They don't seem to
compile by default.
thx
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Nevermind I figured it out.
scons build/ALPHA_SE/unittest/TESTNAME.label
(e.g. scons -j 4 build/ALPHA_SE/unittest/test1.debug)
On Friday 10 September 2010 11:07:12 am Stijn wrote:
Hello,
Is there any way to enable the compilation of unit tests? They don't seem
to compile by default.
On Tuesday 09 March 2010 06:12:04 am Steve wrote:
Actually the writeback buffers are only snooped in timing mode (the
code is in snoopTiming() and not in the handleSnoop() code that's
common to both atomic and timing modes). Just moving that code into
snoopAtomic() wouldn't work, since it
On Sunday 07 March 2010 01:32:09 am Ali wrote:
Hi Stijn,
They are just snoop requests from the access filtering through the
system. You might be able to stop them by having the CPU return
snoop=false to getDeviceAddressRanges(), but I'm not sure that the
caches have code to do that
Hi,
So I've written a fancy deadlock-detection algorithm hoping that it would
detect deadlocks caused the l2-bus trying to access a private cache while that
same private cache tried to access the l2-bus, so that I could roll back one
of the calls. However I found an additional problem. It
On Saturday 06 March 2010 11:53:55 pm Ali wrote:
If you provide us with a back trace of the call we could tell you for
sure, but I imagine it's either a response coming back from the cache,
or it could be one of the status change messages (I think the only one
we support is the range change)
Quoting Steve Reinhardt ste...@gmail.com:
For timing mode, our vision has always been that the interaction
between threads would happen inside of certain specially written
SimObjects and not at the port interface. As it looks like you're
finding out, parallelization has enough complications
On Friday 26 February 2010 04:59:52 pm Steve wrote:
I'm not sure I'm understanding your concern. In the method I'm
proposing, the cache (or more precisely the thread that the cache
event is running on) would not block when it sent a request to the
bus. The call through the port into the bus
html links aren't getting through:
SlackSim:
http://ceng.usc.edu/assets/001/60870.pdf
Graphite:
http://dspace.mit.edu/bitstream/handle/1721.1/49809/MIT-CSAIL-
TR-2009-056.pdf?sequence=1
___
m5-dev mailing list
m5-dev@m5sim.org
Hello again,
It's been a while since my last email and I've made some progress in getting
parts of m5 to run in parallel but I've reached a critical phase and have some
questions of which I'm sure some of the people reading will be able to help me
with.
My main objective has always been to get
Hi again,
I'm currently testing my code with eio traces. I'm going tot need these
for benchmarking later as well. The problem is that my code fails
completely when running more then one eio workload concurrently leading
me to think that this code is not thread-safe. I looked at the code but
it's
AM, Stijn Souffriau
stijn.souffr...@elis.ugent.be wrote:
Hi again,
I'm currently testing my code with eio traces. I'm going tot need these
for benchmarking later as well. The problem is that my code fails
completely when running more then one eio workload concurrently leading
me
I don't think you really need to be able to cancel those events if
every distinct hardware-event was simulated. In case of a mispredicted
instruction the immediately following events don't necessarily need to
commit any lasting cpu state changes just like in a real out of order
cpu. So I'm
Hi,
I was wondering why there are re- and descheduling methods. It seems to
me that they are a sort of error correcting mechanism for cases where
the occurrence of an event is not yet determined. However I can't think
of any reason why you would want to schedule an event if you're no
completely
I was wondering if I can somehow specify in an EXTRAS directory
SConsopts file that I want scons to build the sim/eventq.cc and
sim/eventq.hh files in my EXTRAS directory instead of the ones in the m5
source tree without adding a whole bunch of conditional clauses in the
SConscript files in the
Yeah, that's a better way of doing things since managing duplicates
somewhat defeats the purpose of revision control. Silly me.
nathan binkert wrote:
I was wondering if I can somehow specify in an EXTRAS directory
SConsopts file that I want scons to build the sim/eventq.cc and
sim/eventq.hh
nathan binkert wrote:
Well, it's a question of which objects can have references in multiple
threads simultaneously. We could also be more careful to not just
blindly use the reference counting pointer unless we really are
hanging onto a reference.
If you want a system where concurrently
Nate,
Sorry I didn't reply sooner. I just saw your email today when I was
searching through this thread. I must have missed it.
Since this isn't likely to be the case any time soon, I don't think we
should spend time trying to optimize for this. For the next several
years, I'm pretty sure
form a
process. Just so you have an idea of what I mean with my terminology.
Stijn Souffriau wrote:
Nate,
Sorry I didn't reply sooner. I just saw your email today when I was
searching through this thread. I must have missed it.
Since this isn't likely to be the case any time soon, I
nathan binkert wrote:
I'm not clear on what you're getting at here by using types in C++.
The way things currently work right now is that everything that want's
to schedule an event needs to schedule it through an event manager
(all SimObjects are EventManagers). An event manager is bound to
Thanks for bringing up these issues. These are issues I would never
think of and that will probably cause problems at some point. I'm hoping
you guys will fix most of them ;-) so I can focus my efforts on parallel
event execution.
Ali Saidi wrote:
Well, we don't actually have no data. Remember,
nathan binkert wrote:
Hi Stijn,
I finally got around to reading this thread on parallelizing M5. It
seems that you have a reasonably good handle on the issues involved.
Just so we're clear, the plan all along has been to parallelize M5.
Ali mentioned the change I made about a year ago,
functionality and it's effectiveness is doubtful.
Are there events that can schedule new events in the same cycle in m5.
If so, a PDES system can deadlock! This can generically be overcome but
will require more work.
Ali Saidi wrote:
On Oct 4, 2009, at 8:11 AM, Stijn Souffriau wrote:
Dear
think you missed some of my questions I wrote in
between the lines of your first reply.
Thanks for the help!
Ali Saidi wrote:
On Fri, 09 Oct 2009 18:56:13 +0200, Stijn Souffriau
stijn.souffr...@elis.ugent.be wrote:
Sorry it took so long for me to reply, Ali Saidi, but I've been busy and
I
that we aren't confined to the
parallel simulation of one configuration.
Eagerly awaiting your reply,
Stijn Souffriau
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
25 matches
Mail list logo