Re: [m5-dev] [PATCH] imported patch inorder-alpha-port
I'm a little unsure of what you are saying here Nate. I am trying to add a mt.hh for ALPHA (so it can use the InOrder model) but through some fault of mines the alpha version of the mt.hh file got omitted. Eventually, any ISA wanting to use InOrder would need to at the very least have some bare MT functions since there is no base or generic ISA subdirectory that contains bare-bone implementations of ISA functions needed by the CPUs. On Sat, Feb 21, 2009 at 11:22 PM, nathan binkert n...@binkert.org wrote: 1) not sure why the mt.hh file didnt get added to the patch, but it should be there I think the real problem is that you're adding an mt.hh, but only for mips. That doesn't work so well with the switching directory code. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] [PATCH] imported patch inorder-alpha-port
1) not sure why the mt.hh file didnt get added to the patch, but it should be there I think the real problem is that you're adding an mt.hh, but only for mips. That doesn't work so well with the switching directory code. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] [PATCH] imported patch inorder-alpha-port
oooph...32/4 =8...8 bits in a byte...I plead the 5th!
Originally, that code came from trying to align with some of the SPARC
generic constants (SingleWidth) and I got a little too cute trying to
define a SingleBytes.
And since no ALPHA or MIPS code depends on SingleBytes that's probably
why that bug hasnt surfaced...
On Sat, Feb 21, 2009 at 11:20 PM, nathan binkert n...@binkert.org wrote:
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh
--- a/src/arch/alpha/floatregfile.hhSun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/floatregfile.hhFri Feb 20 09:06:11 2009 -0500
@@ -48,6 +48,13 @@ getFloatRegName(RegIndex)
return ;
}
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
class FloatRegFile
{
public:
I don't really know anything about this code, but if looks like you're
converting bits to bytes but dividing by 4 and not 8. Is this code
correct?
Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH] imported patch inorder-alpha-port
# HG changeset patch
# User Korey Sewell ksew...@umich.edu
# Date 1235138771 18000
# Node ID b6e4240c46e429bf99fefd0d61fef1465de86e49
# Parent 7a74edaa8741dd7fb541ef6d404dac3a9ebc86f9
imported patch inorder-alpha-port
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/SConscript
--- a/src/arch/SConscript Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/SConscript Fri Feb 20 09:06:11 2009 -0500
@@ -51,6 +51,7 @@ isa_switch_hdrs = Split('''
locked_mem.hh
microcode_rom.hh
mmaped_ipr.hh
+mt.hh
process.hh
predecoder.hh
regfile.hh
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh
--- a/src/arch/alpha/floatregfile.hhSun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/floatregfile.hhFri Feb 20 09:06:11 2009 -0500
@@ -48,6 +48,13 @@ getFloatRegName(RegIndex)
return ;
}
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
class FloatRegFile
{
public:
@@ -60,6 +67,55 @@ class FloatRegFile
void serialize(std::ostream os);
void unserialize(Checkpoint *cp, const std::string section);
+
+FloatReg
+readReg(int floatReg)
+{
+return d[floatReg];
+}
+
+FloatReg
+readReg(int floatReg, int width)
+{
+return readReg(floatReg);
+}
+
+FloatRegBits
+readRegBits(int floatReg)
+{
+return q[floatReg];
+}
+
+FloatRegBits
+readRegBits(int floatReg, int width)
+{
+return readRegBits(floatReg);
+}
+
+void
+setReg(int floatReg, const FloatReg val)
+{
+d[floatReg] = val;
+}
+
+void
+setReg(int floatReg, const FloatReg val, int width)
+{
+setReg(floatReg, val);
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val)
+{
+q[floatReg] = val;
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val, int width)
+{
+setRegBits(floatReg, val);
+}
+
};
} // namespace AlphaISA
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.cc
--- a/src/arch/alpha/miscregfile.cc Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/miscregfile.cc Fri Feb 20 09:06:11 2009 -0500
@@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp,
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
}
+MiscRegFile::MiscRegFile(BaseCPU *_cpu)
+{
+cpu = _cpu;
+initializeIprTable();
+}
+
+
MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg)
+MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re
}
MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
+MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, Threa
}
void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val)
+MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val, unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg
}
void
-MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc)
+MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc,
+unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.hh
--- a/src/arch/alpha/miscregfile.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/miscregfile.hh Fri Feb 20 09:06:11 2009 -0500
@@ -41,6 +41,7 @@
class Checkpoint;
class ThreadContext;
+class BaseCPU;
namespace AlphaISA {
@@ -74,6 +75,8 @@ class MiscRegFile
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+BaseCPU *cpu;
+
protected:
InternalProcReg readIpr(int idx, ThreadContext *tc);
void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
@@ -84,16 +87,18 @@ class MiscRegFile
initializeIprTable();
}
+MiscRegFile(BaseCPU *cpu);
+
// These functions should be removed once the simplescalar cpu
// model has been replaced.
int getInstAsid();
int getDataAsid();
-MiscReg readRegNoEffect(int misc_reg);
-MiscReg readReg(int misc_reg, ThreadContext *tc);
+MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0);
-void setRegNoEffect(int misc_reg, const MiscReg val);
-void setReg(int misc_reg, const MiscReg val, ThreadContext *tc);
+void setRegNoEffect(int misc_reg, const MiscReg val, unsigned tid = 0);
+void setReg(int misc_reg, const MiscReg val, ThreadContext *tc, unsigned
tid = 0);
void
clear()
@@ -107,6 +112,16 @@ class MiscRegFile
Re: [m5-dev] [PATCH] imported patch inorder-alpha-port
Before this ALPHA port for the InOrder model can make it to a
changeset, there are few issues that need to be resolved in this
patch:
- Adding member get/setReg functions to FloatRegFile:
The inorder model would like to instantiate multiple int/float
register files and just one miscellaneous register file. The MIPS
misc. regfile has register banks where some are per-core, some are
per-thread, and some are per vpe (virtual processing element). Thus,
it would be undesirable to have one misc. regfile per thread, when
that system state is so closely tied to each other and varies
depending on which register bank you're accesssing.
The ALPHA register file defines the float register file as just an
array of registers without any member functions and then lets the
bigger 'regfile' object have public access to it's data. To allow the
inorder model to use the float-register file independently of the
other register files I gave that object it's member functions back
Is that reverting someone's previous change or an OK addition?
- Misc. RegFile takes a CPU object to assist in MT execution:
If you are running a multithreaded CPU, then potentially two threads
can make changes to the misc. register file on the same cycle. In that
case, you don't want to immediately take action on the effects of your
system changes as soon as the instruction is executed. Instead,you
want to save that there has been changes to the system file and then
re-evaluate those changes at the end of the cycle. Adding the CPU
object, allows the regfile to create an event for itself at the end of
the cycle and then make system changes once all values have been
settled.
- Add thread identifer to misc. regfile functions
To identify the correct misc. register, you need to identify if that
register index is per-Thread and if so, use that thread ID to access
the right register.
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
On Fri, Feb 20, 2009 at 9:27 AM, Korey Sewell ksew...@eecs.umich.edu wrote:
# HG changeset patch
# User Korey Sewell ksew...@umich.edu
# Date 1235138771 18000
# Node ID b6e4240c46e429bf99fefd0d61fef1465de86e49
# Parent 7a74edaa8741dd7fb541ef6d404dac3a9ebc86f9
imported patch inorder-alpha-port
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/SConscript
--- a/src/arch/SConscript Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/SConscript Fri Feb 20 09:06:11 2009 -0500
@@ -51,6 +51,7 @@ isa_switch_hdrs = Split('''
locked_mem.hh
microcode_rom.hh
mmaped_ipr.hh
+mt.hh
process.hh
predecoder.hh
regfile.hh
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh
--- a/src/arch/alpha/floatregfile.hhSun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/floatregfile.hhFri Feb 20 09:06:11 2009 -0500
@@ -48,6 +48,13 @@ getFloatRegName(RegIndex)
return ;
}
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
class FloatRegFile
{
public:
@@ -60,6 +67,55 @@ class FloatRegFile
void serialize(std::ostream os);
void unserialize(Checkpoint *cp, const std::string section);
+
+FloatReg
+readReg(int floatReg)
+{
+return d[floatReg];
+}
+
+FloatReg
+readReg(int floatReg, int width)
+{
+return readReg(floatReg);
+}
+
+FloatRegBits
+readRegBits(int floatReg)
+{
+return q[floatReg];
+}
+
+FloatRegBits
+readRegBits(int floatReg, int width)
+{
+return readRegBits(floatReg);
+}
+
+void
+setReg(int floatReg, const FloatReg val)
+{
+d[floatReg] = val;
+}
+
+void
+setReg(int floatReg, const FloatReg val, int width)
+{
+setReg(floatReg, val);
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val)
+{
+q[floatReg] = val;
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val, int width)
+{
+setRegBits(floatReg, val);
+}
+
};
} // namespace AlphaISA
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.cc
--- a/src/arch/alpha/miscregfile.cc Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/miscregfile.cc Fri Feb 20 09:06:11 2009 -0500
@@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp,
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
}
+MiscRegFile::MiscRegFile(BaseCPU *_cpu)
+{
+cpu = _cpu;
+initializeIprTable();
+}
+
+
MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg)
+MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re
}
MiscReg
-MiscRegFile::readReg(int misc_reg,
Re: [m5-dev] [PATCH] imported patch inorder-alpha-port
I haven't looked at this incredibly closely yet, but I have a few
questions. First, what's this mt.hh file? You made it an ISA switched
header, but I don't see anything by that name being added. What does
it do?
Second, you shouldn't add a comment out include of cpu/inorder/cpu.hh.
Third, why did you add the SingleWidth, SingleBytes, etc values to
floatregfile.hh?
Fourth, have we actually decided how this threading thing is going to
work? I see an expandForMultithreading function which I'm guessing
sets the thread width, so to speak, for the misc reg file? The float
reg file also seems to be split out so it can be instantiated more
than the misc reg file. I'm not saying this stuff is right or wrong,
but I did't think we'd figured out what the big picture strategy was.
Gabe
Quoting Korey Sewell ksew...@eecs.umich.edu:
# HG changeset patch
# User Korey Sewell ksew...@umich.edu
# Date 1235138771 18000
# Node ID b6e4240c46e429bf99fefd0d61fef1465de86e49
# Parent 7a74edaa8741dd7fb541ef6d404dac3a9ebc86f9
imported patch inorder-alpha-port
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/SConscript
--- a/src/arch/SConscript Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/SConscript Fri Feb 20 09:06:11 2009 -0500
@@ -51,6 +51,7 @@ isa_switch_hdrs = Split('''
locked_mem.hh
microcode_rom.hh
mmaped_ipr.hh
+mt.hh
process.hh
predecoder.hh
regfile.hh
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh
--- a/src/arch/alpha/floatregfile.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/floatregfile.hh Fri Feb 20 09:06:11 2009 -0500
@@ -48,6 +48,13 @@ getFloatRegName(RegIndex)
return ;
}
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
class FloatRegFile
{
public:
@@ -60,6 +67,55 @@ class FloatRegFile
void serialize(std::ostream os);
void unserialize(Checkpoint *cp, const std::string section);
+
+FloatReg
+readReg(int floatReg)
+{
+return d[floatReg];
+}
+
+FloatReg
+readReg(int floatReg, int width)
+{
+return readReg(floatReg);
+}
+
+FloatRegBits
+readRegBits(int floatReg)
+{
+return q[floatReg];
+}
+
+FloatRegBits
+readRegBits(int floatReg, int width)
+{
+return readRegBits(floatReg);
+}
+
+void
+setReg(int floatReg, const FloatReg val)
+{
+d[floatReg] = val;
+}
+
+void
+setReg(int floatReg, const FloatReg val, int width)
+{
+setReg(floatReg, val);
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val)
+{
+q[floatReg] = val;
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val, int width)
+{
+setRegBits(floatReg, val);
+}
+
};
} // namespace AlphaISA
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.cc
--- a/src/arch/alpha/miscregfile.cc Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/miscregfile.cc Fri Feb 20 09:06:11 2009 -0500
@@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp,
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
}
+MiscRegFile::MiscRegFile(BaseCPU *_cpu)
+{
+cpu = _cpu;
+initializeIprTable();
+}
+
+
MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg)
+MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re
}
MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
+MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, Threa
}
void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val)
+MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val, unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg
}
void
-MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc)
+MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc,
+unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.hh
--- a/src/arch/alpha/miscregfile.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/miscregfile.hh Fri Feb 20 09:06:11 2009 -0500
@@ -41,6 +41,7 @@
class Checkpoint;
class ThreadContext;
+class BaseCPU;
namespace AlphaISA {
@@ -74,6 +75,8 @@ class MiscRegFile
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+BaseCPU *cpu;
+
protected:
