Hi Korey,
Several Ruby protocols already support shared banked caches. In particular, I
believe the token, MESI_dir, and MOES_dir protocols support a shared banked L2
cache. All you need to do is set num-l2caches to the desired value. The
python configuration files for those protocols then should automatically use
the low order bits to select the proper L2 cache. However, I just noticed that
the L2 index bits are not being properly set when you make that change so I'm
pushing a patch that fixes that.
Going forward, there are several ways we could improve the address to L2 cache
mapping support:
- Add hash functions to evenly spread the address range across
non-power-of-2 number of L2 caches.
- Support for multiple sockets
o Previously, these protocols did support multiple sockets when integrated
with GEMS, but that was deprecated in gem5 because of configuration changes and
no one has yet to add it back in.
o If you're interested to try this, let me know and I can give you more
information.
- Create a better methodology for matching the number of caches versus
the index bits.
o In general, this has been a Ruby pain point for a long while. People often
make this error and never realize it.
o If we create such a methodology, we should incorporate the numa bit
selection as well
Brad
> -Original Message-
> From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
> On Behalf Of Steve Reinhardt
> Sent: Friday, March 25, 2011 7:40 AM
> To: M5 Developer List
> Subject: Re: [m5-dev] Thoughts on Ruby Address Ranges for Memory
> Objects?
>
> Hi Korey,
>
> I'm not the Ruby expert, but I think adding support for banked caches would
> be great. However, I wouldn't do it via address ranges, since in many cases
> you'd want to use low-order rather than high-order bits to select the bank.
>
> I'll leave it to someone else to discuss how it *should* be done...
>
> Steve
>
> On Fri, Mar 25, 2011 at 7:11 AM, Korey Sewell
> mailto:ksew...@umich.edu>> wrote:
> > Hi all,
> > I'm looking into figuring out how to specify a particular address
> > range for caches and other memory objects. This would give you the
> > ability to do things like say have shared-banked-L2 implemented using
> > 4 L2 Cache banks.
> >
> > In the old M5 memory, I know you could actually give a particular
> > memory object a memory range but in Ruby I'm not seeing the same type
> > of interface or support(not to say there isn't, its just not clear to
> > me yet).
> >
> > Does anyone have any knowledge of how to enable this same type of
> > behavior (banked caches or address range specification) OR does anyone
> > have any suggested areas in Ruby to where I should start implementing
> > this? I'm tentatively thinking that if this isnt already in Ruby it
> > can be implemented into the L1 cache controllers but I have
> > reservations on how the network routing will work once those changes
> > are made.
> >
> > Again, if anybody has any thoughts or suggestions please share!
> >
> > --
> > - Korey
> > ___
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> >
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