*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic:
FAILED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing:
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing:
FAILED!
*
build/RISCV/tests/opt
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/9461
Change subject: base: Add a default output function for bitunion types.
..
base: Add a default output function for bitunion types.
T
Hello Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/8883
to look at the new patch set (#2).
Change subject: mem-cache: Make getPossibleLocations a const function
..
Daniel Carvalho has uploaded a new patch set (#2). (
https://gem5-review.googlesource.com/8884 )
Change subject: mem-cache: Use replacement candidates to find block
..
mem-cache: Use replacement candidates to find block
Use r
Pau Cabre has uploaded this change for review. (
https://gem5-review.googlesource.com/9481
Change subject: util,arch-arm: Update gen_arm_fs_files.py to use new kernel
repos
..
util,arch-arm: Update gen_arm_fs_files.py to u
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/9501
to review the following change.
Change subject: arch-arm: Correct mcrr,mrrc disassemble
..
arch-arm: Correc
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/9503
to review the following change.
Change subject: arch-arm: Fix AArch32 branch instructions disassemble
..
ar
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/9502
to review the following change.
Change subject: arch-arm: Fix secure write of SCTLR when EL3 is AArch64
..
Hello!
FALRU (src/mem/cache/tags/fa_lru.*) has segmentation faults in the current
simulator state. In an attempt to solve them, I've made two patches. The second
one (https://gem5-review.googlesource.com/c/public/gem5/+/8882), however,
evidences a symbol lookup error on my machine (gcc version 5
Hello Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/9302
to look at the new patch set (#2).
Change subject: mem-cache: Fix FALRU data block seg fault
..
mem-cache:
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/9461 )
Change subject: base: Add a default output function for bitunion types.
..
base: Add a default output function for bitunion
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/9521
Change subject: dev: Make sure the EtherTap device uses the right event
queue.
..
dev: Make sure the EtherTap device uses the righ
Ok, I think I figured it out, and it all has to do with the simulation
quantum. If the quantum is too big, the kernel might poke hardware and
expect to get an interrupt within a certain period of time. It could be
that the CPU gets to the end of its timeout before the simulated hardware
has had a c
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