[gem5-dev] Bug in O3 CPU when executing "1: jmp 1b"

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi everyone, I was playing around a bit with gem5 and noticed by accident that the O3 CPU model seems to be unable to handle jumps to the same location (at least, that's what it looks like). I have the following piece of x86 assembly code:

Re: [gem5-dev] RISC-V full system support and bug fixes

eate an Epic about this on the Jira instance: > https://gem5.atlassian.net/projects/GEM5/issues. This will make it > easier to track the progress, etc. > > Cheers, > Jason > > On Mon, Feb 24, 2020 at 4:57 AM Nils Asmussen > wrote: > >> Hi all, >> >> I've just pushe

[gem5-dev] RISC-V full system support and bug fixes

Hi all, I've just pushed a couple of patches that add full system support to RISC-V and a also few bug fixes. We cannot run Linux yet (I didn't try), but we can run software that uses virtual memory :) The status is that all tests of the RISC-V test suite work in the p, ps and v environment,

[gem5-dev] ARM: rfe instruction broken on O3 CPU

Hi all, I've stumbled upon an issue with ARM's return from exception (rfe) instruction in combination with the O3 CPU. With the TimingSimpleCPU everything works fine. But with the DerivO3CPU it seems that the restoration of the userspace SP register does not happen immediately. For example,

Re: [gem5-dev] ARM: rfe instruction broken on O3 CPU

On 1/29/20 8:30 AM, Ciro Santilli wrote: > I would also recommend opening a bug report for this at: > https://gem5.atlassian.net/projects/GEM5/issues with the arch-arm > component to make it easier to keep track of. Sure, I can do that. Nils ___

Re: [gem5-dev] ARM: rfe instruction broken on O3 CPU

On 1/29/20 3:26 AM, Gabe Black wrote: > It looks to me like this is because the MicroUopSetPCCPSR microop > (uopSet_uop, the one actually setting the CPSR) is not marked as > IsSerializeAfter. The macroop it's a part of is, but the flags on macroops, > other than the one that says it's a macroop,

Re: [gem5-dev] Removing kokoro runs

Hi, same for me. Google says the permission "cloudbuild.builds.get" is missing. Best regards, Nils On 3/31/20 4:23 PM, Ciro Santilli wrote: > Since Giacomo started this thread, I would also want to chime in a related > question: are you able to see GCB run logs? > > E.g. at:

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault on mstatus accesses from lower privilege modes.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25652 ) Change subject: arch-riscv: fault on mstatus accesses from lower privilege modes. .. arch-riscv: fault

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added fullsystem support.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25647 ) Change subject: arch-riscv: added fullsystem support. .. arch-riscv: added fullsystem support. That is, RISC

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added (un)serialization of miscRegFile.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25650 ) Change subject: arch-riscv: added (un)serialization of miscRegFile. .. arch-riscv: added (un)serialization

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: merged changes from RISCV-test upstream repo.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25705 ) Change subject: arch-riscv,tests: merged changes from RISCV-test upstream repo. .. arch-riscv,tests: merged

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make accesses to CSRs SerializeAfter.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25655 ) Change subject: arch-riscv: make accesses to CSRs SerializeAfter. .. arch-riscv: make accesses to CSRs

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: added .gitignore.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25704 ) Change subject: arch-riscv,tests: added .gitignore. .. arch-riscv,tests: added .gitignore. Change-Id

[gem5-dev] Change in gem5/gem5[develop]: tests: call sys.exit() on failure in Simulation::run.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25662 ) Change subject: tests: call sys.exit() on failure in Simulation::run. .. tests: call sys.exit() on failure

[gem5-dev] Change in gem5/gem5[develop]: base, sim: allow m5writeFile with stdout/stderr.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25661 ) Change subject: base,sim: allow m5writeFile with stdout/stderr. .. base,sim: allow m5writeFile with stdout

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: run p tests.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25706 ) Change subject: arch-riscv,tests: run p tests. .. arch-riscv,tests: run p tests. This commit enables the p

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: report that we don't have debugging support.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25659 ) Change subject: arch-riscv: report that we don't have debugging support. .. arch-riscv: report that we don't

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25645 ) Change subject: arch-riscv: added support for pseudo instructions. .. arch-riscv: added support for pseudo

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault according to status.{TVM, TSK, TW}.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25654 ) Change subject: arch-riscv: fault according to status.{TVM,TSK,TW}. .. arch-riscv: fault according to status

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25649 ) Change subject: arch-riscv: show names of MiscRegs on accesses. .. arch-riscv: show names of MiscRegs

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed read of {M, S, U}TVEC.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25648 ) Change subject: arch-riscv: fixed read of {M,S,U}TVEC. .. arch-riscv: fixed read of {M,S,U}TVEC. As stated

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: ignore writes to SXL/UXL fields in status register.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25651 ) Change subject: arch-riscv: ignore writes to SXL/UXL fields in status register. .. arch-riscv: ignore

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: print information about faults.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25646 ) Change subject: arch-riscv: print information about faults. .. arch-riscv: print information about faults

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added dummy implementation of wfi instruction.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25653 ) Change subject: arch-riscv: added dummy implementation of wfi instruction. .. arch-riscv: added dummy

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25658 ) Change subject: arch-riscv: respect IALIGN, influenced by toggling 'c' extension. .. arch-riscv: respect

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make uret, sret, mret SerializeAfter, NonSpeculative.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25656 ) Change subject: arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative. .. arch-riscv: make uret

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, arch-x86: moved common code into generic walker class.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25660 ) Change subject: arch-riscv,arch-x86: moved common code into generic walker class. .. arch-riscv,arch-x86

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: run v tests.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25707 ) Change subject: arch-riscv,tests: run v tests. .. arch-riscv,tests: run v tests. This commit enables the v

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: improved run-tests.py.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25703 ) Change subject: arch-riscv,tests: improved run-tests.py. .. arch-riscv,tests: improved run-tests.py

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25657 ) Change subject: arch-riscv: let FPU instructions fault if status.FS = off. .. arch-riscv: let FPU instructions

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: make SetPCCPRS microop SerializeAfter

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24943 ) Change subject: arch-arm: make SetPCCPRS microop SerializeAfter .. arch-arm: make SetPCCPRS microop

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: make MicroUopSetPCCPSR SerializeAfter

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/24943 ) Change subject: arch-arm: make MicroUopSetPCCPSR SerializeAfter .. arch-arm: make MicroUopSetPCCPSR SerializeAfter

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: print information about faults.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25646 ) Change subject: arch-riscv: print information about faults. .. arch-riscv: print information about faults. Change-Id

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25645 ) Change subject: arch-riscv: added support for pseudo instructions. .. arch-riscv: added support for pseudo instructions

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement RemoteGDB::acc for FS mode.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/26985 ) Change subject: arch-riscv: implement RemoteGDB::acc for FS mode. .. arch-riscv: implement RemoteGDB::acc

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make sure only supported modes can be set in SATP.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/26983 ) Change subject: arch-riscv: make sure only supported modes can be set in SATP. .. arch-riscv: make sure

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: add support for the walker cache.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/26988 ) Change subject: arch-riscv,configs: add support for the walker cache. .. arch-riscv,configs: add support

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: removed unused files.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/26987 ) Change subject: arch-riscv: removed unused files. .. arch-riscv: removed unused files. Change-Id

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed formatting.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/26986 ) Change subject: arch-riscv: fixed formatting. .. arch-riscv: fixed formatting. Change-Id

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement sfence.vma to flush TLBs.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/26984 ) Change subject: arch-riscv: implement sfence.vma to flush TLBs. .. arch-riscv: implement sfence.vma to flush

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: added bare metal FS support.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/26989 ) Change subject: arch-riscv,configs: added bare metal FS support. .. arch-riscv,configs: added bare metal FS

[gem5-dev] Re: Question about O3 CPU

Hi Peter, I am not sure, but could the issue be this one: https://www.mail-archive.com/gem5-dev@gem5.org/msg16924.html At least as far as I know, the problem that the X86-O3-CPU cannot handle jumps to the same location still exists. Best regards, Nils On 3/25/24 14:29, Peter Wang via

[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28448 ) Change subject: misc: added news on RISC-V to RELEASE-NOTES.md. .. misc: added news on RISC-V to RELEASE

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28447 ) Change subject: arch-riscv: be prepared for CSR changes during PT walk. .. arch-riscv: be prepared for CSR

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28447 ) Change subject: arch-riscv: be prepared for CSR changes during PT walk. .. arch-riscv: be prepared for CSR changes during

[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28448 ) Change subject: misc: added news on RISC-V to RELEASE-NOTES.md. .. misc: added news on RISC-V to RELEASE-NOTES.md

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: report that we don't have debugging support.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25659 ) Change subject: arch-riscv: report that we don't have debugging support. .. arch-riscv: report that we don't have

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make accesses to CSRs SerializeAfter.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25655 ) Change subject: arch-riscv: make accesses to CSRs SerializeAfter. .. arch-riscv: make accesses to CSRs SerializeAfter

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25657 ) Change subject: arch-riscv: let FPU instructions fault if status.FS = off. .. arch-riscv: let FPU instructions fault

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25658 ) Change subject: arch-riscv: respect IALIGN, influenced by toggling 'c' extension. .. arch-riscv: respect IALIGN

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make sure only supported modes can be set in SATP.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/26983 ) Change subject: arch-riscv: make sure only supported modes can be set in SATP. .. arch-riscv: make sure only supported

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed formatting.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/26986 ) Change subject: arch-riscv: fixed formatting. .. arch-riscv: fixed formatting. Change-Id

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement sfence.vma to flush TLBs.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/26984 ) Change subject: arch-riscv: implement sfence.vma to flush TLBs. .. arch-riscv: implement sfence.vma to flush TLBs

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement RemoteGDB::acc for FS mode.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/26985 ) Change subject: arch-riscv: implement RemoteGDB::acc for FS mode. .. arch-riscv: implement RemoteGDB::acc for FS mode

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25649 ) Change subject: arch-riscv: show names of MiscRegs on accesses. .. arch-riscv: show names of MiscRegs on accesses

[gem5-dev] Change in gem5/gem5[develop]: configs: added bare metal FS support for RISC-V.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/26989 ) Change subject: configs: added bare metal FS support for RISC-V. .. configs: added bare metal FS support for RISC-V

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed read of {M,S,U}TVEC.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25648 ) Change subject: arch-riscv: fixed read of {M,S,U}TVEC. .. arch-riscv: fixed read of {M,S,U}TVEC. As stated in 4.1.4

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: ignore writes to SXL/UXL fields in status register.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25651 ) Change subject: arch-riscv: ignore writes to SXL/UXL fields in status register. .. arch-riscv: ignore writes to SXL

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added dummy implementation of wfi instruction.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25653 ) Change subject: arch-riscv: added dummy implementation of wfi instruction. .. arch-riscv: added dummy implementation

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault on mstatus accesses from lower privilege modes.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25652 ) Change subject: arch-riscv: fault on mstatus accesses from lower privilege modes. .. arch-riscv: fault on mstatus

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault according to status.{TVM,TSK,TW}.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25654 ) Change subject: arch-riscv: fault according to status.{TVM,TSK,TW}. .. arch-riscv: fault according to status.{TVM,TSK,TW

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added (un)serialization of miscRegFile.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25650 ) Change subject: arch-riscv: added (un)serialization of miscRegFile. .. arch-riscv: added (un)serialization of miscRegFile

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added TLB and page table walker.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25647 ) Change subject: arch-riscv: added TLB and page table walker. .. arch-riscv: added TLB and page table walker

[gem5-dev] Change in gem5/gem5[develop]: cpu,configs: let RISC-V use the PT walker cache.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/26988 ) Change subject: cpu,configs: let RISC-V use the PT walker cache. .. cpu,configs: let RISC-V use the PT walker cache

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25656 ) Change subject: arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative. .. arch-riscv: make uret,sret,mret

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: merged changes from RISCV-test upstream repo.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28729 ) Change subject: arch-riscv,tests: merged changes from RISCV-test upstream repo. .. arch-riscv,tests: merged

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: base,sim: allow m5writeFile with stdout/stderr.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28727 ) Change subject: base,sim: allow m5writeFile with stdout/stderr. .. base,sim: allow m5writeFile with stdout

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run p tests.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28730 ) Change subject: arch-riscv,tests: run p tests. .. arch-riscv,tests: run p tests. This commit enables the p

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run v tests.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28731 ) Change subject: arch-riscv,tests: run v tests. .. arch-riscv,tests: run v tests. This commit enables the v

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: added .gitignore.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28728 ) Change subject: arch-riscv,tests: added .gitignore. .. arch-riscv,tests: added .gitignore. Change-Id

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: base,sim: allow m5writeFile with stdout/stderr.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28727 ) Change subject: base,sim: allow m5writeFile with stdout/stderr. .. base,sim: allow m5writeFile with stdout/stderr