t the L2flag in response pkt.
> And if it is misses in L2, set main memory flag in response pkt, as you
> are sure you will get data from main memory.
> Here we are assuming it’s a single core simulation.
>
> On Fri, May 10, 2019 at 5:42 AM Muhammad Avais
> wrote:
>
>> Dear Al
Dear All,
1- For blocks loaded in the L1 cache, how can I distinguish that it was
loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
cache)?
Many thanks,
Best Regards,
Avais
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o take care of "clean victim" from dcache which is not a
> difficult modification.
>
> Best regards,
>
> Abhishek
>
>
> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais
> wrote:
>
>> Dear All,
>> Is 'mostly exclusive cache' supported in GEM5
quot; from dcache which is not a
> difficult modification.
>
> Best regards,
>
> Abhishek
>
>
> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais
> wrote:
>
>> Dear All,
>> Is 'mostly exclusive cache' supported in GEM5 classic model
>> strictly n
Dear All,
Is 'mostly exclusive cache' supported in GEM5 classic model strictly
non-exclusive cache? If it is not non-exclusive cache, how can I make it
non-exclusive cache?
The non-exclusive cache is shown in Fig. below.
[image: image.png]
Can anyone guide me?
Many thanks,
best
Dear All,
Is 'mostly exclusive cache' supported in GEM5 classic model strictly
non-exclusive cache? If it is not non-exclusive cache, how can I make it
non-exclusive cache?
Can anyone guide me?
Many thanks,
best regards,
Avais
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Dear all,
Can anyone guide how to implement bank model for caches in gem5?
Is there any patch to implement bank model
Many thanks,
Best Regards,
Avais
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Dear All,
I was tracking zero blocks (64B 0 value) written to cache.
During experiments, i found that cache block does not hold data sometimes.
To some cache lines non-zero block is written to cache line from lower
level memory but this data is read as Zero block during access by
.
> But I have used them in python and in the se.py and
> garnet_synth_traffic.py codes, although I have not done exactly what you
> are trying to do.
> Regards
> Parmida
>
> On Mon, Aug 13, 2018 at 11:40 AM, Muhammad Avais
> wrote:
>
>> Dear Parmida,
>>
d ifs in the
> code, there is also a sleep function but I don't know if that's what you
> want.
>
> On Mon, 13 Aug 2018, 09:43 Muhammad Avais, wrote:
>
>> Dear all,
>>
>>I want to adjust associativity of cache after fix
>> periods of time. Ca
Dear all,
I want to adjust associativity of cache after fix
periods of time. Can anyone suggest how can i decide time in gem5.
Best Regards,
Thanks,
Avais
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t; Best Regards,
> Haeyoon Cho.
>
> 2018-05-25 12:17 GMT+09:00 Muhammad Avais :
>
>> Dear Haeyoon Cho.,
>>
>> I am really thankful to you for this help. Actually, i am not very good
>> in modifying gem5 and this code will be very helpful for me.
>>
>> I
style is not good.
>
> If you can modify gem5 code better than me, please let me know.
>
> Best Regards,
> Haeyoon Cho.
>
>
> 2018-05-23 15:55 GMT+09:00 Muhammad Avais <avais.suh...@gmail.com>:
>
>> Dear All,
>>
>> I want to measure dynamic ene
Dear All,
I want to measure dynamic energy of L2 cache for multi-core
simulations. For this purpose, i measure stats from gem5 like # of hits, #
of misses and # of writebacks.
As, multi-core simulation in gem5 terminates, as soon as, any workload
reaches maximum count. Therefore, while
>
>
> *From: *gem5-users <gem5-users-boun...@gem5.org> on behalf of Muhammad
> Avais <avais.suh...@gmail.com>
> *Reply-To: *gem5 users mailing list <gem5-users@gem5.org>
> *Date: *Friday, 4 May 2018 at 11:16
> *To: *gem5 users mailing list <gem5-us
ay 4, 2018 at 2:28 PM, Muhammad Avais <avais.suh...@gmail.com>
wrote:
> Dear Nikos,
>
> Many thanks for your reply. Your suggestion are always helpful in
> solving issues in gem5. I will try to use writeclean packets.
>
> Many thanks,
> Kind Regards,
> Avais
&g
Dear All,
Can anyone suggest what this error message indicates
read error, exit
Exiting @ tick 104585181462 because exiting with last active thread context
And how can i do to debug it?
Many thanks,
Avais
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longer. If you are on a
> reasonably recent version of gem5, you could try using WriteClean packets
> which have the exact same property of carrying dirty data without the
> additional property of implying an eviction.
>
> Nikos
>
>
>
>
>
> *From: *gem5-users <gem5-
Dear All,
I am trying tom implement dynamic associative cache. I have found
that after decreasing the associativity, if i do not invalidate blocks then
following problem occurs.
Actually, i do not want to invaliate blocks that are out of associativity,
can anyone suggest some solution
#0
Dear All,
I found it was inheritance problem,
Many thanks,
Best Regards,
Avais
On Fri, Apr 27, 2018 at 8:45 PM, Muhammad Avais <avais.suh...@gmail.com>
wrote:
> Dear Eliot,
>
>Just after returning from this function, i am checking the way
> number
Moss <m...@cs.umass.edu> wrote:
> On 4/27/2018 7:36 AM, Muhammad Avais wrote:
>
>> Dear all,
>>
>> I implemented function findBlockBySetAndWay(int set, int
>> way_no) function in lru.cc file, as it's parent class ()base_set_assoc.hh)
>>
Dear all,
I implemented function findBlockBySetAndWay(int set, int
way_no) function in lru.cc file, as it's parent class ()base_set_assoc.hh)
function can not be applied to LRU class.
Code is simple but it gives block with wrong way_no.
CacheBlk* LRU::findBlockBySetAndWay(int set,
he source of the problem.
>
>
>
> Nikos
>
>
>
> *From: *gem5-users <gem5-users-boun...@gem5.org> on behalf of Muhammad
> Avais <avais.suh...@gmail.com>
> *Reply-To: *gem5 users mailing list <gem5-users@gem5.org>
> *Date: *Wednesday, 25 April 2018 at 12:25
>
t; the routeTo map and after some time, when a new packet reuse the same
> memory and therefore the pkt->req, it finds the old route in the map and
> crashes. It might be worth making sure that you are on the latest version
> of gem5.
>
>
>
> Nikos
>
>
>
>
>
&g
Dear all,
I want to implement write-non-allocate policy in gem5. Can any
one give some hint?
In "bool Cache::access(PacketPtr pkt, CacheBlk *, Cycles ,
PacketList writebacks) " function, inside cache.cc file, where blocks are
allocated, i have added following line
if(WR_NON_ALLOC{
e block.
>
> Nikos
>
>
> On 01/18/18 11:13, Muhammad Avais wrote:
>
>> Dear All,
>> Is there any way to know that block in L2 cache stores
>> data or instruction?
>>
>> Many Thanks
>> Best Regards
>> Avais
>>
>&g
Dear All,
Has anyone made some list of read intensive or data intensive
SPEC2006 benchmarks or some other benchmarks
Many Thanks
Best Regards
Avais
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Dear All,
Is there any way to know that block in L2 cache stores
data or instruction?
Many Thanks
Best Regards
Avais
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ialized in the memory system
> (e.g., writebacks, prefetches), it won't have a valid PC.
>
> Thanks,
>
> Nikos
>
> On 01/15/18 11:17, Muhammad Avais wrote:
>
>> Dear Nikos,
>>
>> Many thanks for your reply. Actually, I wanted to see
> On 01/12/18 11:44, hassan yamin wrote:
>
>> For the packets you are getting invalid program counter, can you check
>> is it read or write packet?
>>
>> On Jan 12, 2018 8:20 PM, "Muhammad Avais" <avais.suh...@gmail.com
>> <mailto:avais.suh...@gma
Dear All,
I want to get the Program counter value of packets at some points
in gem5.
For some packets, i am getting invalid program counter value(in
cache::handlefill() function mostly)
Can anyone suggest, how can i get valid program counter.
Many Thanks
Best Regards
Avais
; Published by Morgan and Claypool.
>
> Boris
>
> -"gem5-users" <gem5-users-boun...@gem5.org> wrote: -
> To: gem5 users mailing list <gem5-users@gem5.org>
> From: Muhammad Avais
> Sent by: "gem5-users"
> Date: 10/19/2017 03:47AM
> Subj
Dear All,
I want to study the MOESI cache coherence protocol. Can
anyone suggest some study material that can be useful in understanding
MOESI protocol for cache coherence.
Many Thanks
Avais
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Hi,
Does GEM5 follows any specific cache coherence protocol?
If yes? then which one?
Thanks
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Hi,
I want to create small table (256 entries) in gem5 that is accessed on each
cache miss and follows LRU replacement policy.
Can someone guide me how to do it? (Which classes i should use or inherit)
Many Thanks
Avais
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Hi,
I want to create simpoints for SPEC2006 benchmarks. Can anyone tell what to
set in "--maxinsts=" parameter while creating simpoints (particularly
sjeng, namd benchmarks)
Many Thanks
Avais
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Hi
Can anyone share with me simpoints for SPEC2006 benchmarks
(particularly sjeng, namd, bzip2)
Many Thanks
Best Regards
Avais
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Hi,
I have question regarding 'ResponseLatency' of Cache. Is it
technology dependent or has fixed value?
How to choose its value?
Thanks
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Hi,
I have one question regarding mostly exclusive cache in gem5
Although 'Mostly exclusive' cache in gem5 does not allocate blocks on miss
in higher level caches but i think filllatency and response latency are
still added for these blocks.
Is it true? How can it be avoided?
l
> target packet came from a non-caching source, or if we are performing a
> prefetch or LLSC.
>
> Andreas
>
> From: gem5-users <gem5-users-boun...@gem5.org> on behalf of Muhammad
> Avais <avais.suh...@gmail.com>
> Reply-To: gem5 users mailing list <gem5-users
Hi,
There is alloconfill() function in gem5. This determines whether data is
allocated in cache upon miss in L1 cache or not.
Ideally, If cache is mostly exclusive then data should not be allocated in
cache upon miss in L1 cache.
But this function loads data in 'mostly exclusive' upon miss in
I want to measure improvement in performance with decrease in write latency
of L2 cache.
But as i reduce the write latency of L2 cache, i observe no increase in
ipc.
Is it always the case or i have made some mistake?
Can anyone comment on this?
Should i see some other parameter as indication of
Hi,
what is the purpose of function subname() function used in base.cc file
Many THanks
Avais
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nt a mostly-exclusive cache, the caches
> closer to the CPU should set the "writeback_clean" parameter to true (and
> to false if the further cache is mostly-inclusive).
>
> Jason
>
> On Fri, Jul 14, 2017 at 3:16 AM Muhammad Avais <avais.suh...@gmail.com>
> wrote:
>
&g
Can someone explain following functions in Packet.hh file
Addr getOffset(unsigned int blk_size) const
Addr getBlockAddr(unsigned int blk_size) const
Many Thanks
Avais
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Dear All,
Gem5 contains BlkDirty bit as indication whether the cache line
is modified or not. How can i assign dirty bit for each byte in cache line.
How can i determine that which bytes of cache line are modified.
Many Thanks
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Dear all,
Can anyone guide me how to implement hybrid cache in
gem5.
Particularly, i want to implement Hybrid cache with each set composed of
two types of memories having different latencies
Many Thanks
Avais
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Hi,
I found one misleading stat in gem5. I added one 'Mostly
Exclusive' cache just below 'Data cache', that stores only dirty blocks
coming out of Data Cache. In stats file, i found that dirty writebacks out
of this 'Mostly Exclusive' cache are more than WritebackDirty_hits into
this
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